CN110661409B

CN110661409B - Feedforward control method and circuit of converter

Info

Publication number: CN110661409B
Application number: CN201910846624.8A
Authority: CN
Inventors: 尹向阳; 周阿铖; 曾正球
Original assignee: Shenzhen Nanyun Microelectronics Co ltd
Current assignee: Shenzhen Nanyun Microelectronics Co ltd
Priority date: 2019-09-09
Filing date: 2019-09-09
Publication date: 2021-01-15
Anticipated expiration: 2039-09-09
Also published as: CN110661409A

Abstract

The invention provides a front space control method and a circuit of a converter.A power tube is in a saturation region when the drain electrode conduction voltage of the power tube is larger than the saturation voltage drop of the power tube, and the current is directly limited by the internal bias current of which the internal is in inverse proportion to the input voltage through the start of the saturation mirror image control power tube; after the drain electrode conduction voltage of the power tube is smaller than the saturation voltage drop, the power tube enters a linear region, and the compensation current increased along with the voltage drop of the drain end of the power tube is superposed on the internal bias current to compensate the current loss of the power tube in the linear region. The invention compatibly solves the problems of chip heating and capacitive load when the constant voltage converters with the same power level and different input voltages set the starting limiting current; and chip pins are not needed to be arranged, PCB (printed circuit board) layout resources are saved, and meanwhile, the control of starting limiting current can be still realized within the range of +/-10% of the same input voltage, so that the starting heating and capacitive load capacity control are more flexible.

Description

Feedforward control method and circuit of converter

Technical Field

The invention is suitable for switch type converter, especially for feedforward control method and circuit of converter in full bridge type or push-pull type converter.

Background

Constant voltage power supply modules often employ full bridge converter and push-pull converter topologies. As shown in fig. 1, taking a full-bridge converter as an example, for a constant-voltage system, in a start-up or output short-circuit stage, an output voltage is close to zero, a voltage drop across a primary winding is clamped to be very low, most of the voltage drop falls at a drain terminal of a primary power tube, and at this time, the primary power tube is conducted and passes a very large saturation current, which is easily burnt. And in the steady state stage after the output is established, the secondary side load current directly determines the current flowing through the primary side power tube, and the burning danger is relieved. Compared with a full-bridge converter, the P-type power tube on the primary side of the push-pull converter is directly replaced by a conducting wire, and the problems are also caused.

In order to solve the problem that the primary power tube is easily burned in the starting and short-circuit stages, a mode of arranging a switching tube in a primary driving chip of a full-bridge or push-pull converter and setting a start limiting current is commonly adopted in the industry (as shown in fig. 2). But in order to ensure that the overcurrent point is in a full-load state of 2-3 times, the value of the start limiting current is not too small. Taking the system of 5V1W as an example, when the turn ratio of the primary side and the secondary side is close to 1:1, the startup limiting current value is about 500-600mA, in order to prevent the switching tube integrated in the chip from heating seriously, the current limiting time cannot be too long. And the starting limit current size and the current limiting time directly determine the capacitive load capacity of the converter.

In the prior art, the consideration of starting to limit current and capacitive load is mostly realized by controlling a driving chip.

The invention discloses a drive control method, which is a Chinese patent application with the publication number of CN106533187B and the invention name of drive control method and circuit. On the basis, the problems of capacitive load, load capacity of starting the machine and short-circuit heating of the constant voltage system can be solved in a compromise mode by designing a current limiting mode, a timing detection mode and a hiccup protection mode in a control chip. However, in a full-bridge or push-pull converter system with the same power level and different input voltages, it is difficult to select a proper start limiting current, because for a fixed start limiting current Ist and a fixed timing time Td, when the input voltage is high, heat is greatly generated in the timing time Td, and an over-temperature condition is easily generated; when the input voltage of the converter is low, referring to the formula (1), the turn ratio Np: Ns of the primary side and the secondary side is small, and the current transmitted to the secondary side for charging the output capacitor is small, namely the capacitive load is low.

To solve the problem that it is difficult to select the value of the start-up limiting current Ist when the system compatible with the multiple input ranges is used, it is naturally conceivable that the start-up limiting current Ist or the timing time Td needs to be designed to have a value varying with the input voltage. In the prior art, the start limiting current Ist is adjustable by externally arranging a current limiting resistor on a chip; and a soft start pin is also arranged, and the soft start timing time is adjusted by externally connecting a soft start capacitor, so that the timing time Td can be adjusted. However, these methods all require external chip pins and devices, and for a system with fixed primary and secondary turn ratios, within a variation range of ± 10% of the nominal input voltage, the fixed startup limit current Ist and the timing time Td cannot be adjusted any more, which is likely to cause the temperature rise of the system under the limit condition or the reduction of the capacitive load capacity.

Disclosure of Invention

In view of this, the present invention is to solve the defects in the prior art, adjust the startup limit current and the short circuit determination threshold on the premise of not externally installing chip pins and devices, solve the problems of system temperature rise and capacitive load when the constant voltage switch type full bridge and push-pull converters are compatible with different input voltages, and make the overcurrent points of the converters in the full input range substantially consistent.

The technical scheme for solving the technical problems is as follows:

a feed-forward control method of a converter is used for start-up limited current control of a primary side power tube in a full-bridge or push-pull converter, and comprises the following steps:

and a step of sectional control of the start-up limited current, which is to divide the control of the start-up limited current into two sections during the period that the voltage of the drain terminal of the primary power tube drops or is maintained along with the increase of the secondary output voltage in the stage of starting or outputting short circuit of the converter: in the first section, when the drain electrode conduction voltage of the power tube is larger than the saturation voltage drop, the power tube is in a saturation region, and the internal bias current controls the starting of the power tube to limit the current through a saturation mirror image; adding the compensation current, the first transconductance current and the reference bias current to obtain an internal bias current; the transconductance current I is inversely proportional to the converter input voltage; in the second stage, after the drain electrode conduction voltage of the power tube is smaller than the saturation voltage drop, the power tube enters a linear region, and the compensation current increased along with the voltage drop of the drain end of the power tube is superposed on the internal bias current to compensate the current loss of the power tube in the linear region;

and a short circuit judgment threshold value determining step, namely selecting a rated output voltage value with the output reaching 90% -95%, and calculating the corresponding drain end voltage of the primary side power tube as a short circuit judgment threshold value through the conversion of the turn ratio of the primary side to the secondary side, wherein the threshold value and the input voltage present a positive correlation trend.

As a further improvement of the above technical solution, the starting limited current segment control step includes the following processes:

(1) the second transconductance amplifier generates a first transconductance current and a second transconductance current which are in inverse proportion to the input voltage of the converter, the second transconductance current is used as the input bias current of the first transconductance amplifier, the first transconductance amplifier generates a compensation current, and the compensation current is increased along with the reduction of the drain electrode breakover voltage of the power tube and is reduced along with the increase of the input voltage of the converter;

(2) and superposing the reference bias current, the compensation current and the transconductance current into an internal bias current, and proportionally generating the start limiting current of the power tube through a saturated mirror image.

As a further improvement of the above technical solution, the short circuit determination threshold determining step includes the following steps:

and the third transconductance amplifier generates a third transconductance current which is in direct proportion to the input voltage of the converter, and the third transconductance current is dropped on the resistor to generate a short-circuit judgment threshold value of the starting stage of the converter, so that when the secondary side output reaches 90-95% of the rated output voltage value, the overcurrent point which is separated from the short-circuit protection is judged, and the short-circuit judgment threshold value is in direct proportion to the input voltage.

As a further improvement of the technical scheme, the short circuit judgment threshold is a reference voltage matched with the positive temperature coefficient of the power tube.

A feedforward control circuit of a converter is used for controlling a start-up limited current of a power tube in a full-bridge or push-pull converter and comprises a start-up limited current sectional control front-end unit, a current summing unit, a current mirror image unit and a short circuit judgment unit; the startup limited current segmentation control front-end unit generates a compensation current Icomp and a transconductance current I _ gvin 1 in the startup or output short-circuit stage of the converter, wherein the compensation current Icomp increases along with the voltage drop of the drain end of the power tube and decreases along with the voltage rise of the input of the converter during the period that the drain conduction voltage VDS _ on of the power tube decreases, and the transconductance current I _ gvin 1 is inversely proportional to the input voltage of the converter; the current summing unit is used for summing a compensation current Icomp, a transconductance current I _ gvin 1 and a reference bias current I _ bias1, wherein the compensation current Icomp, the transconductance current I _ gvin 1 and the reference bias current I _ bias1 are added to obtain an internal bias current Isum; the current mirror unit is used for enabling the internal bias current to proportionally generate the start limiting current of the power tube through the saturated mirror; the short circuit determination unit is used for determining a short circuit determination threshold value and determining a short circuit.

As a further improvement of the above technical solution, the current mirror unit includes a current mirror circuit 100, the current mirror circuit 100 includes a power transistor MN0 and a power transistor MN1, wherein a gate and a drain of the power transistor MN1 are shorted with a gate of the power transistor MN0, a source and a substrate of the power transistor MN1 and a source and a substrate of the power transistor MN0 are all grounded VSS, and a drain of the power transistor MN0 generates a start-up limiting current Ist.

As a further improvement of the above technical solution, the startup limited current segmented control front-end unit includes a transconductance amplifier 101 and a transconductance amplifier 102, where the transconductance amplifier 102 includes a positive-phase input terminal, an inverted-phase input terminal, an input bias current terminal, and an output terminal, and the ports of the transconductance amplifier 101 and the transconductance amplifier 102 are set the same;

a positive phase input end of the transconductance amplifier 102 is connected with a reference voltage Vref2, an inverting input end of the transconductance amplifier 102 is connected with a converter input voltage divided voltage Vin _ K, an input bias current of the transconductance amplifier 102 is connected with a reference bias current I _ bias2, a first output of an output end is a transconductance current I _ gvin 1, a second output of the output end is a transconductance current I _ gvin 2, and the transconductance current I _ gvin 1 and the transconductance current I _ gvin 2 are in inverse proportion to the converter input voltage;

the non-inverting input end of the transconductance amplifier 101 is connected with the reference voltage Vref1, the inverting input end of the transconductance amplifier 101 is connected with the conducting drain conducting voltage VDS _ on of the power tube MN0, the input bias current of the transconductance amplifier 101 is connected with the transconductance current I _ gvin 2, and the output end of the transconductance amplifier 101 outputs the compensation current Icomp.

As a further improvement of the above technical solution, the current summing unit includes a current summer 104, the current summer 104 includes three current input terminals and a current output terminal, the three current input terminals are respectively connected to the reference bias current I _ bias1, the compensation current Icomp and the transconductance current I _ gvin 1, the current output terminal outputs the internal bias current Isum, and the internal bias current Isum is connected to the gate of the power transistor MN 1.

As a further improvement of the above technical solution, the short circuit determination unit includes a transconductance amplifier 103, a resistor R1, and a short circuit protection comparator 105, the ports of the transconductance amplifier 103 and the transconductance amplifier 102 are set to be the same, the positive phase input terminal of the transconductance amplifier 103 is connected to a converter input voltage divided voltage Vin _ K, the negative phase input terminal of the transconductance amplifier 103 is connected to a reference voltage Vref3, the input bias current of the transconductance amplifier 103 is connected to a reference bias current I _ bias3, the output terminal of the transconductance amplifier 103 outputs a transconductance current I _ gvin 3, and the transconductance current I _ gvin 3 is in direct proportion to the converter input voltage;

as a further improvement of the above technical solution, the short-circuit protection comparator 105 includes a forward input terminal, a reverse input terminal, and an output terminal, the forward input terminal of the short-circuit protection comparator 105 is connected to the drain conduction voltage VDS _ on of the power transistor MN0, one end of the resistor R1 is connected to the transconductance current I _ gvin 3 and is connected to the reverse input terminal of the short-circuit protection comparator 105, the other end of the resistor R1 is connected to the ground VSS, the output terminal of the short-circuit protection comparator 105 outputs a signal OSP _ L, and the signal OSP _ L is used for logic control in the converter.

As a further improvement of the technical proposal, the power tube MN1 and the power tube MN0 are MOS tubes which are of the same type and matched with each other in size, and the size between the power tube MN1 and the power tube MN0 meets the requirement (W/L)_MN0/(W/L)_MN1＝K＝Ist/Isum，(W/L)_MN0Is the width-length ratio (W/L) of a power tube MN0_MN1For the width-to-length ratio of the power tube MN1, Ist limits the current for startup.

As a further improvement of the above technical solution, the ports of transconductance amplifier 101, transconductance amplifier 102, and transconductance amplifier 103 are configured the same, but the devices included therein or the sizes of the devices may be different.

As a further improvement of the above technical solution, transconductance amplifier 101, transconductance amplifier 102, and transconductance amplifier 103 all use components and connection relationships of transconductance amplifier 301;

the transconductance amplifier 301 comprises a PMOS transistor PM4, a PMOS transistor PM5, a PMOS transistor PM6, a PMOS transistor PM7, an NMOS transistor NM4, an NMOS transistor NM5, and an NMOS transistor NM 6;

the source of the PMOS transistor PM4 and the source of the PMOS transistor PM5 are connected to a working power supply potential VCC, the gate and the drain of the PMOS transistor PM4 are shorted with the gate of the PMOS transistor PM5 to serve as input bias current ends of the transconductance amplifier 301, the drain of the PMOS transistor PM5 is connected with the source of the PMOS transistor PM6 and the source of the PMOS transistor PM7, the gate of the PMOS transistor PM6 is a positive-phase input end of the transconductance amplifier 301, the drain of the PMOS transistor PM7 is shorted with the gate and the drain of the NMOS transistor NM5, the gate of the PMOS transistor PM7 is an inverted-phase input end of the transconductance amplifier 301, the drain of the PMOS transistor PM6 is shorted with the gate and the drain of the NMOS transistor NM4, the source and the substrate of the NMOS transistor NM4, NMOS transistor NM5 and NMOS transistor NM6 are both grounded VSS, the gate of the NMOS transistor NM5 is connected with the gate of the NMOS transistor NM6, the drain of the NMOS transistor NM6 is an output end of the PMOS transistor PM amplifier 301, and the drain of the PMOS transistor PM4, the PMOS transistor PM 63 5.

The working principle of the scheme provided by the invention will be described in detail in the specific embodiment, and the working principle of the invention is combined, so that the defects in the prior art are overcome, and the beneficial effects are as follows:

(1) the problems of chip heating and capacitive load when the constant-voltage converters with the same power level and different input voltages set the starting limiting current are solved;

(2) chip pins are not needed to be arranged, PCB (printed circuit board) layout resources are saved, and meanwhile, the control of starting limiting current can be still realized within the range of +/-10% of the same input voltage, so that the starting heating and capacitive load capacity control is more flexible;

(3) and in the whole startup or short-circuit output stage and the voltage reduction period of the drain terminal of the power tube, the constant-voltage converter is ensured to have enough capacitive load capacity in the whole output voltage rising process.

Drawings

FIG. 1 is a circuit schematic of a prior art constant voltage full bridge converter;

FIG. 2 is a schematic circuit diagram of a control chip applied to a constant-voltage full-bridge inverter in the prior art;

FIG. 3 is a waveform diagram illustrating various critical signals decreasing with the drain voltage of the power transistor according to an embodiment of the present invention;

FIG. 4 is a block diagram of an application circuit functioning in a control chip according to an embodiment of the present invention;

FIG. 5 is a functional block diagram of the feedforward control circuit of the present invention;

fig. 6 is a typical circuit of a transconductance amplifier according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail below with reference to the accompanying drawings and the first embodiment.

Example one

The idea of the feedforward control circuit of the converter of the embodiment is as follows:

fig. 3 is a waveform diagram illustrating changes of critical signals in a constant voltage converter applied by an embodiment of the invention as a drain voltage of a primary side power tube MN0 decreases. Combining the formula (2), it can be known that in the starting process of the converter, the drain conduction voltage VDS _ on of the primary power tube MN0 of the converter is very high initially due to low output voltage, where Vin is the input voltage of the converter, Vo is the output voltage of the converter, Vd is the forward conduction voltage drop of the secondary diode of the converter, Np: Ns is the turn ratio of the primary side to the secondary side of the converter:

when the converter works in the stage 1-1 in the figure 3, the primary side power tube MN0 is in a saturation region, and the initial grid voltage of the primary side power tube MN0 is set to Vgs under a fixed input voltage₀Thereby controlling the initial start-up limiting current to be Ist₀During the period, as the output voltage Vo of the converter slowly rises, the drain turn-on voltage VDS _ on of the primary power tube MN0 falls, and the turn-on internal resistance of the primary power tube MN0 also synchronously decreases.

After the converter is started, the forward conduction voltage drop Vd of the secondary side diode of the converter is reduced, the drain electrode conduction voltage VDS _ on of the primary side power tube MN0 is reduced to a saturation-linearity critical point A in the figure, the primary side power tube MN0 is close to a linear region, and the current formulas (3) and (4) of the saturation region and the linear region are combined to know that if the start limiting current Ist is not compensated at the moment, the initial gate voltage Vgs of the primary side power tube MN0 is still maintained₀Without change, the start-up limiting current Ist drops rapidly, so the forward conduction voltage of the secondary side diode of the converterWhen the Vd is close to the saturation voltage drop voltage, the compensation of the design start-up limiting current Ist is started, namely point A in the definition graph is the compensation starting point of the start-up limiting current.

A constant flow area:

a linear region:

in the formulae (3) and (4), μ_nDenotes the carrier mobility, C_oxThe unit area gate oxide layer capacitance is expressed, W/L is the width-length ratio of the MOS tube, V_THIs the threshold voltage of MOS transistor, V_DSAnd V_GSRespectively representing the drain-source voltage and the gate-source voltage of the MOS tube, and Id representing the current flowing between the drain and the source of the MOS tube.

At the end of the 1-2 stage, since the drain-on voltage VDS _ on of the primary power tube MN0 drops rapidly, even if there is a linear compensation current, the drain-source current with the linear region decreasing exponentially may be lower than the initial start-up limiting current Ist₀The normal phenomenon can be compensated by setting a certain margin for the current value in the 1-1 stage.

A stage 1 composed of stages 1-1 and 1-2 in fig. 3 is the current-limiting driving stage, after stage 1 is finished, the system enters stage 2 of steady-state operation, the output voltage Vo of the converter has already been established to reach a stable value, the primary power tube MN0 enters a linear region and is in hard driving, namely, the gate voltage is no longer limited, at this time, the drain conduction voltage VDS _ on of the primary power tube MN0 and the current Ids flowing between the drain and the source of the primary power tube MN0 determine that the secondary load is a constant value, and the conduction impedance of the power tube in a completely conducting state is also a fixed value.

When the converter starts to enter the stage 1-1 in fig. 3, the internal start-up time of the chip in the converter starts. If the output voltage does not rise to the set value within the timing time Td (determined by the current-limiting stage short-circuit protection threshold Vth1, namely the voltage at the point B in the figure), the short-circuit protection rest stage is determined to be entered, the chip is restarted after the rest timing is finished, and the feedforward circuit is controlled to work in the converter start or output short-circuit stage.

The system enters stage 1-2 in fig. 3, the drain-on voltage VDS _ on of the primary power tube MN0 corresponding to point B is defined as the short-circuit determination threshold Vthos in the current-limiting driving stage, and its selection is mainly related to the determination of the short-circuit protection disengagement by the increase of the percentage of the output voltage in the current-limiting stage. Based on a full-bridge topology, taking a system with 24V input, 9V input and 5V output as an example, respectively, selecting a moment when the output voltage Vo of the converter rises to 95% as a short-circuit judgment point, and assuming that the turn ratio of an original secondary side is Np: Ns ═ 24: ns 9 and Np: and 5.4, taking the forward conduction voltage drop Vd of the secondary side diode as 0.4V:

obtaining that Vthos _2405 is 1.11V; vthos _0905 ═ 0.42V; it is easy to deduce that the constant voltage system under the same output voltage gradually increases the required short circuit protection determination threshold value under the condition of keeping the overcurrent point of the output establishment stage consistent with the increase of the input voltage.

In a constant-voltage primary side control chip of an integrated power tube, due to corresponding switch tubes with the same size, initial startup limiting current Ist required under different input voltages₀Different, i.e. its initial gate voltage Vgs₀The drain turn-on voltage VDS _ on of the corresponding saturation-linearity critical point a may be different. However, as the input voltage Vin increases, the initial start-up limits the current Ist₀Should be reduced so that the initial gate voltage Vgs_0、The drain turn-on voltage VDS _ on corresponding to the saturation-linearity critical point a is decreased. In order to solve the problems of chip heating and capacitive load when the constant voltage converter with the same power level and different input voltages is set to start up to limit current, the current compensation at this stage needs to be designed.

Application circuit of feedforward control circuit of converter of this embodiment:

fig. 4 is a block diagram of an application circuit of the feedforward control circuit 100 in the embodiment of the invention, and as shown in fig. 4, the circuit 100 in the embodiment of the invention includes a voltage dividing resistor RA, a resistor RB, a feedforward control circuit 10, a reference voltage and current generating module 11, a power tube conducting voltage sampling circuit 12, a voltage selection circuit 13, a driving circuit 14, a converter N-type power tube MN01, a converter N-type power tube MN02, a P-type power tube MP01, a P-type power tube MP02, and two inverters, where VS1 and VS2 are two power ground ports of the circuit 100, VSs is a small signal ground port of the circuit 100, VD1 and VD2 are power tube drain ports, VIN2 is a power input port, and 6 ports correspond to the converter control chip ports shown in fig. 2.

The converter input voltage VIN generates VIN _ K signals proportional to the input voltage after being divided by the voltage dividing resistors RA and RB, the input voltage VIN further generates an internal circuit power VCC and an internal power supply PVCC through the reference voltage and current generating module 11, and generates a plurality of reference signals Vref at the same time to generate a plurality of reference currents I _ bias for the feedforward control circuit 10 to make a reference input voltage for feedforward determination and a bias current of the transconductance amplifier. The power tube on voltage sampling circuit 12 collects and stores drain voltages of the power tubes MN01 and MN02 during the on period as VDS _ on, and feeds back the magnitude of the secondary side output voltage Vo for short-circuit protection judgment in the feedforward control circuit 10. The feedforward control circuit 10 generates a current-limiting driving gate voltage V _ soft having an inverse correlation with the input voltage and simultaneously generates a short-circuit protection determination signal OSP _ L based on the reference voltages Vref1, Vref2, and Vref3, the reference currents I _ bias1, I _ bias2, and I _ bias3 generated by the reference voltage and current generation module 11, Vin _ K having a proportional relationship with the input voltage, and the drain turn-on voltages VDS _ on of the power tubes MN01 and MN02 during turn-on. Under the action of the voltage selector 13, when the short-circuit protection determination signal OSP _ L is at a low level, the high value of the driving level received by the driving circuit 14 is V _ soft; when the short-circuit protection determination signal OSP _ L is at a high level, the driving level received by the driving circuit 14 is at a high value PVCC, and the driving circuit 14 amplifies the complementary clock signals CLK and CLK' inside the chip step by step to generate a pair of complementary gate voltages VGN1 and VGN2 for driving the power transistors MN01 and MN 02. That is, when the system is determined to be in the power-on or short-circuit state, the high level of the gate voltage VGN1 of the power transistor MN01 and the high level of the gate voltage VGN2 of the power transistor MN02 will be V _ soft, and when the system is determined to be in the stable state of non-power-on and non-short-circuit, the high level of the gate voltage VGN1 of the power transistor MN01 and the high level of the gate voltage VGN2 of the power transistor MN02 will be PVCC. The gate levels VGN1 and VGN2 of the N-type power transistors output by the driving circuit 14 generate the gate levels of the P-type power transistors MP01 and MP02, respectively, through an inverter.

The feedforward control circuit 10 plays a specific role in an application circuit, namely, the drive level high value under the generated current-limiting drive is V _ soft, the short-circuit protection threshold value is related to the input voltage Vin, the V _ soft level is in inverse proportion to the input voltage Vin, the short-circuit protection threshold value is in direct proportion to the input voltage Vin, and feedforward control is realized.

The structure of the feedforward control circuit 10 of the converter of the present embodiment:

fig. 5 is a schematic block diagram of the feedforward control circuit 10 and the N-type power transistor MN0 (representing MN01 or MN02 in fig. 4) of the converter according to the embodiment of the present invention. As shown in fig. 5, the circuit of the embodiment of the present invention includes a current mirror circuit 100, a transconductance amplifier 101, a transconductance amplifier 102, a current summer 104, a transconductance amplifier 103, a resistor R1, and a short-circuit protection comparator 105.

The current mirror circuit 100 comprises a MOS transistor MN0 and a MOS transistor MN1, wherein the gate and the drain of the MOS transistor MN1 are in short circuit with the gate of the power transistor MN0, the source and the substrate of the MOS transistor MN1 and the source and the substrate of the power transistor MN0 are all grounded to VSS, and the drain of the power transistor MN0 generates a start-up limiting current Ist.

Transconductance amplifier 102 includes a positive-phase input terminal, an inverse-phase input terminal, an input bias current terminal, and an output terminal, and the ports of transconductance amplifier 101 and transconductance amplifier 102 are set the same;

the non-inverting input end of the transconductance amplifier 101 is connected with the reference voltage Vref1, the inverting input end of the transconductance amplifier 101 is connected with the drain conduction voltage VDS _ on of the power tube MN0, the input bias current of the transconductance amplifier 101 is connected with the transconductance current I _ gvin 2, and the output end of the transconductance amplifier 101 outputs the compensation current Icomp. The drain turn-on voltage VDS _ on of the power tube MN0 is obtained by a sample-and-hold circuit in the converter sampling during the turn-on period of the power tube MN0 and holding during the turn-off period of the power tube MN 0.

The current summer 104 includes three current input terminals and three current output terminals, the three current input terminals are respectively connected to the reference bias current I _ bias1, the compensation current Icomp and the transconductance current I _ gvin 1, the current output terminal outputs the internal bias current Isum, and the internal bias current Isum is connected to the gate of the power tube MN 1.

The MOS transistor MN1 is similar to the MOS transistor MN0 in size matching, and the size between the MOS transistor MN1 and the MOS transistor MN0 satisfies (W/L)_MN0/(W/L)_MN1And K is Ist/Isum, namely the ratio of the width-length ratio of the MOS transistor MN0 to the width-length ratio of the MOS transistor MN1 is equal to the ratio of the start-up limiting current Ist to the internal bias current Isum.

The ports of transconductance amplifier 103 and transconductance amplifier 102 are arranged in the same manner, the non-inverting input terminal of transconductance amplifier 103 is connected to the input voltage divided voltage Vin _ K of the converter, the inverting input terminal of transconductance amplifier 103 is connected to the reference voltage Vref3, the input bias current of transconductance amplifier 103 is connected to the reference bias current I _ bias3, the output terminal of transconductance amplifier 103 outputs transconductance current I _ gvin 3, and transconductance current I _ gvin 3 is proportional to the input voltage of the transformer.

The devices included in transconductance amplifier 101, transconductance amplifier 102, and transconductance amplifier 103 are different in size. Transconductance amplifier 101, transconductance amplifier 102, and transconductance amplifier 103 all use the components of transconductance amplifier 301 shown in fig. 6 and their connection relationships, and the components include transconductance amplifier 301 including PMOS transistor PM4, PMOS transistor PM5, PMOS transistor PM6, PMOS transistor PM7, NMOS transistor NM4, NMOS transistor NM5, and NMOS transistor NM 6; the connection relationship of the components is as follows: the source of the PMOS transistor PM4 and the source of the PMOS transistor PM5 are connected to a working power supply potential VCC, the gate and the drain of the PMOS transistor PM4 are shorted with the gate of the PMOS transistor PM5 to serve as input bias current ends of the transconductance amplifier 301, the drain of the PMOS transistor PM5 is connected with the source of the PMOS transistor PM6 and the source of the PMOS transistor PM7, the gate of the PMOS transistor PM6 is a positive-phase input end of the transconductance amplifier 301, the drain of the PMOS transistor PM7 is shorted with the gate and the drain of the NMOS transistor NM5, the gate of the PMOS transistor PM7 is an inverted-phase input end of the transconductance amplifier 301, the drain of the PMOS transistor PM6 is shorted with the gate and the drain of the NMOS transistor NM4, the source and the substrate of the NMOS transistor NM4, NMOS transistor NM5 and NMOS transistor NM6 are both grounded VSS, the gate of the NMOS transistor NM5 is connected with the gate of the NMOS transistor NM6, the drain of the NMOS transistor NM6 is an output end of the PMOS transistor PM amplifier 301, and the drain of the PMOS transistor PM4, the PMOS transistor PM 63 5.

The short-circuit protection comparator 105 comprises a positive input end, a negative input end and an output end, the positive input end of the short-circuit protection comparator 105 is connected with a drain conducting voltage VDS _ on of the power tube MN0, one end of a resistor R1 is connected with a transconductance current I _ gvin 3 and is connected with the negative input end of the short-circuit protection comparator 105, the other end of the resistor R1 is grounded VSS, the output end of the short-circuit protection comparator 105 outputs a signal OSP _ L, and the signal OSP _ L is used for logic control in the converter.

The working process of the feedforward control circuit of the converter of the embodiment is as follows:

a desired feedforward input voltage range is designed by setting a suitable input voltage division ratio K (Vin _ K — K Vin) based on transconductance amplifier 102 and selecting reference voltage Vref 2. Taking an input range of 9 to 24V as an example, selecting K1/10 and Vref2 1.65V, adjusting the input-to-bandwidth ratio of the transconductance amplifier to obtain a transconductance output current I _ gvin 2 with a linear change value of I _ bias2 to 0 correspondingly under the input of 9 to 24V, and obtaining a current value with a proper magnitude through different current mirror proportions to facilitate subsequent design.

(1) In the first stage, the MOS transistor MN0 is in a saturation region:

transconductance current I _ gvin 1 generated by transconductance amplifier 102 and transconductance current I _ gvin 1 are inversely proportional to converter input voltage, and are superposed on reference bias current I _ bias1, and the transconductance current I _ gvin 1 determines the start-up limiting current of MOS transistor MN0 through saturated mirror image, so that the start-up limiting current of MOS transistor MN0 is reduced as converter input voltage increases.

(2) In the second stage, the MOS transistor MN0 enters the linear region:

the appropriate reference voltage Vref1 is selected to make the drain turn-on voltage VDS _ on of the MOS transistor MN0 decrease to the vicinity of the saturation voltage drop (point a in fig. 3) of the power transistor, so as to adjust and increase the compensation current Icomp.

In the stage that the MOS transistor MN0 is in the linear region, the compensation current Icomp increases with the decrease of the drain on voltage VDS _ on of the MOS transistor MN 0; meanwhile, since the input bias current of the transconductance amplifier 101 is the transconductance current I _ gvin 2 which is output by the transconductance amplifier 102 and inversely proportional to the input voltage Vin, the compensation current Icomp signal is changed along with the drain on voltage VDS _ on of the MOS transistor MN0, and is also reduced along with the increase of the input voltage Vin, so as to achieve the purpose of starting to provide the compensation current after the MOS transistor MN0 enters the linear region.

(3) Determining a short circuit judgment threshold value, namely selecting a rated output voltage value with the output reaching 90% -95%, wherein the drain electrode breakover voltage of a corresponding MOS (metal oxide semiconductor) transistor MN0 is the short circuit judgment threshold value:

the input of the transconductance amplifier 103 is set and selected with reference to two inputs of the transconductance amplifier 102, and accordingly, a transconductance output current I _ gvin 3 with a value of I _ bias3 to 0 linear variation is obtained, the transconductance output current I _ gvin 3 increased along with the rise of the input voltage is converted into a corresponding short-circuit protection threshold through a resistor R1, and then the short-circuit protection threshold and the conducting drain voltage VDS _ on of the power tube MN0 are used as the input end of the comparator 105 to compare and output a short-circuit protection determination signal OSP _ L for controlling the logic in the variation period.

Claims

1. A feedforward control method of a converter is used for the start-up limited current control of a power tube in a full-bridge or push-pull converter, and comprises the following steps:

and a step of sectional control of the start-up limited current, wherein in the stage of starting or outputting short circuit of the converter, the control of the start-up limited current is divided into two sections along with the rise of the secondary side output voltage and the fall or maintenance of the voltage of the drain terminal of the primary side power tube: in the first section, when the drain electrode conduction voltage of the power tube is larger than the saturation voltage drop, the power tube is in a saturation region, and the internal bias current controls the starting of the power tube to limit the current through a saturation mirror image; adding the compensation current, the first transconductance current and the reference bias current to obtain an internal bias current; the transconductance current I is inversely proportional to the converter input voltage; in the second stage, after the drain electrode conduction voltage of the power tube is smaller than the saturation voltage drop, the power tube enters a linear region, and the compensation current increased along with the voltage drop of the drain end of the power tube is superposed on the internal bias current to compensate the current loss of the power tube in the linear region;

2. The control method according to claim 1, wherein the startup-limited-current-segment control step includes the steps of:

3. The control method according to claim 1, wherein the short circuit determination threshold value determining step includes the steps of:

4. A feed forward control method of a converter according to claim 1, characterized in that: the short circuit judgment threshold is a reference voltage matched with the positive temperature coefficient of the power tube.

5. A feedforward control circuit of a converter is used for starting limited current control of a power tube in a full-bridge or push-pull converter and is characterized by comprising a starting limited current segmented control front-end unit, a current summing unit, a current mirror unit and a short circuit judgment unit; the startup limited current segmentation control front-end unit generates a compensation current Icomp and a transconductance current I _ gvin 1 in the startup or output short-circuit stage of the converter, wherein the compensation current Icomp increases along with the voltage drop of the drain end of the power tube and decreases along with the voltage rise of the input of the converter during the period that the drain conduction voltage VDS _ on of the power tube decreases, and the transconductance current I _ gvin 1 is inversely proportional to the input voltage of the converter; the current summing unit is used for summing a compensation current Icomp, a transconductance current I _ gvin 1 and a reference bias current I _ bias1, wherein the compensation current Icomp, the transconductance current I _ gvin 1 and the reference bias current I _ bias1 are added to obtain an internal bias current Isum; the current mirror unit is used for enabling the internal bias current to proportionally generate the start limiting current of the power tube through the saturated mirror; the short circuit determination unit is used for determining a short circuit determination threshold value and determining a short circuit.

6. The control circuit of claim 5, wherein: the current mirror unit comprises a current mirror circuit 100, the current mirror circuit 100 comprises a power tube MN0 and a power tube MN1, wherein a grid electrode and a drain electrode of the power tube MN1 are in short circuit with a grid electrode of the power tube MN0, a source electrode and a substrate of the power tube MN1 and a source electrode and a substrate of the power tube MN0 are all grounded to VSS, and a drain electrode of the power tube MN0 generates a start-up limiting current Ist.

7. The control circuit of claim 5, wherein: the startup limited current segmentation control front-end unit comprises a transconductance amplifier 101 and a transconductance amplifier 102, wherein the transconductance amplifier 102 comprises a positive phase input end, an inverse phase input end, an input bias current end and an output end, and the ports of the transconductance amplifier 101 and the transconductance amplifier 102 are arranged in the same way;

the non-inverting input end of the transconductance amplifier 101 is connected with the reference voltage Vref1, the inverting input end of the transconductance amplifier 101 is connected with the drain conduction voltage VDS _ on of the power tube, the input bias current of the transconductance amplifier 101 is connected with the transconductance current I _ gvin 2, and the output end of the transconductance amplifier 101 outputs the compensation current Icomp.

8. The control circuit of claim 5, wherein: the current summing unit comprises a current summer 104, the current summer 104 comprises three current input ends and three current output ends, the three current input ends are respectively connected into a reference bias current I _ bias1, a compensation current Icomp and a transconductance current I _ gvin 1, the current output ends output an internal bias current Isum, and the internal bias current Isum is connected into a grid electrode of a power tube MN 1.

9. The control circuit of claim 5, wherein: the short circuit determination unit comprises a transconductance amplifier 103, a resistor R1 and a short circuit protection comparator 105;

the transconductance amplifier 103 comprises a positive phase input end, an inverse phase input end, an input bias current end and an output end, the positive phase input end of the transconductance amplifier 103 is connected with a converter input voltage divided voltage Vin _ K, the inverse phase input end of the transconductance amplifier 103 is connected with a reference voltage Vref3, the input bias current end of the transconductance amplifier 103 is connected with a reference bias current I _ bias3, the output end of the transconductance amplifier 103 outputs a transconductance current I _ gvin 3, and the transconductance current I _ gvin 3 is in direct proportion to the converter input voltage;

the short-circuit protection comparator 105 comprises a positive input end, a negative input end and an output end, the positive input end of the short-circuit protection comparator 105 is connected with a drain electrode conducting voltage VDS _ on of the power tube, one end of a resistor R1 is connected with a transconductance current I _ gvin 3 and is connected with the negative input end of the short-circuit protection comparator 105, the other end of the resistor R1 is grounded with VSS, the output end of the short-circuit protection comparator 105 outputs a signal OSP _ L, and the signal OSP _ L is used for logic control in the converter.

10. The control circuit of claim 8, wherein: the power tube MN1 and the power tube MN0 are MOS tubes which are of the same type and matched in size, and the size between the power tube MN1 and the power tube MN0 meets the requirement (W/L)_MN0/(W/L)_MN1＝K＝Ist/Isum，(W/L)_MN0Is the width-length ratio (W/L) of a power tube MN0_MN1For the width-to-length ratio of the power tube MN1, Ist limits the current for startup.

11. The control circuit of claim 7, wherein: both transconductance amplifier 101 and transconductance amplifier 102 adopt the components and connection relationship of transconductance amplifier 301:

12. The control circuit of claim 9, wherein: the transconductance amplifier 103 adopts the components and connection relationship of the transconductance amplifier 301: