CN110660666A - Transistor epitaxial growth method and preparation method of transistor - Google Patents

Transistor epitaxial growth method and preparation method of transistor Download PDF

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Publication number
CN110660666A
CN110660666A CN201910922368.6A CN201910922368A CN110660666A CN 110660666 A CN110660666 A CN 110660666A CN 201910922368 A CN201910922368 A CN 201910922368A CN 110660666 A CN110660666 A CN 110660666A
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precursor
base electrode
electrode layer
thermal annealing
transistor
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颜志泓
林志东
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Integrated Circuit Co Ltd Is Pacified By Xiamen City Three
Xiamen Sanan Integrated Circuit Co Ltd
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Integrated Circuit Co Ltd Is Pacified By Xiamen City Three
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234—Bipolar junction transistors [BJT]
    • H01L29/6631—Bipolar junction transistors [BJT] with an active layer made of a group 13/15 material
    • H01L29/66318—Heterojunction transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H01L21/3245—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering of AIIIBV compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1004—Base region of bipolar transistors

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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Bipolar Transistors (AREA)

Abstract

The application provides a transistor epitaxial growth method and a transistor preparation method, and relates to the technical field of semiconductors and communication. The transistor epitaxial growth method comprises the following steps: introducing a first precursor to form a base electrode layer; turning off the first precursor, and carrying out thermal annealing treatment on the base electrode layer; and introducing a second precursor to the base electrode layer after the thermal annealing treatment to form an emitter layer. The base electrode layer is subjected to thermal annealing treatment, so that the carbon doped bonding form in the base electrode layer is stable, the carbon atoms are prevented from being cracked again after the carbon doped bonding is subjected to bias energy during the operation of the device, the p-type doping concentration in the base electrode layer is prevented from being increased, the current gain is prevented from being increased, and the transient effect is improved.

Description

Transistor epitaxial growth method and preparation method of transistor
Technical Field
The application relates to the technical field of semiconductors and communication, in particular to a transistor epitaxial growth method and a transistor preparation method.
Background
The current gain of a Heterojunction Bipolar Transistor (HBT) is determined by the p-type doping concentration (doping concentration) of the Base electrode layer (Base layer), and the precursor (precursor) for p-type doping is typically carbon doped (carbon doped). During the epitaxial growth of the epitaxial wafer, hydrogen (hydrogen) is used as a carrier gas (carrier gas) to form a carbon doped bond which is reacted or not reacted, and the current gain of the HBT is confirmed after the epitaxial growth.
However, when the device is properly biased, the base-emitter junction obtains a bias voltage, so that the carbon doped bonds of the base electrode layer obtain energy to crack carbon atoms again, and the p-type doping concentration of the base electrode layer is increased to increase the current gain, which is called transient effect (transient effect), and the transient effect makes the circuit design and application unstable.
Therefore, it is an urgent technical problem to design a method for epitaxial growth of a transistor, which can improve the transient effect of current gain.
Disclosure of Invention
In view of the above, the present application aims to provide a method for epitaxially growing a transistor and a method for manufacturing a transistor to improve the above problems.
The embodiment of the application provides a transistor epitaxial growth method, which comprises the following steps:
introducing a first precursor to form a base electrode layer;
turning off the first precursor, and carrying out thermal annealing treatment on the base electrode layer;
and introducing a second precursor to the base electrode layer after the thermal annealing treatment to form an emitter layer.
In the step of performing the thermal annealing treatment on the base electrode layer, a temperature range of the thermal annealing treatment is as follows: 500-700 ℃.
In the step of performing thermal annealing treatment on the base electrode layer, the duration range of the thermal annealing treatment is as follows: 1min to 10 min.
In the above-mentioned transistor epitaxial growth method, the first precursor is one of group iii precursors or one of group v precursors.
In the above transistor epitaxial growth method, the group iii precursor includes TMGa, TMAl, TMIn, TEGa, TEAl, TEIn.
In the above method for epitaxial growth of a transistor, the group five precursor comprises AsH3、TMAs、TBAs、PH3、TBP。
In the above transistor epitaxial growth method, the step of forming an emitter layer, after the step of forming an emitter layer, includes:
and turning off the second precursor, and carrying out thermal annealing treatment on the emitter layer.
In the above transistor epitaxial growth method, the step of forming an emitter layer, after the step of forming an emitter layer, includes:
introducing a third precursor on the emitter layer to form a cap layer;
and turning off the third precursor, and carrying out thermal annealing treatment on the cap layer.
In the above method for epitaxial growth of a transistor, the step of performing thermal annealing treatment on the cap layer includes:
introducing a fourth precursor on the cap layer to form an ohmic contact layer;
and turning off the fourth precursor, and carrying out thermal annealing treatment on the ohmic contact layer.
The embodiment of the application also provides a preparation method of the transistor, and the preparation method of the transistor comprises the epitaxial growth method of the transistor.
The transistor epitaxial growth method and the transistor preparation method provided by the embodiment of the application have the beneficial effects that:
the base electrode layer is subjected to thermal annealing treatment, so that the carbon doped bonding form in the base electrode layer is stable, the carbon atoms are prevented from being cracked again after the carbon doped bonding is subjected to bias energy during the operation of the device, the p-type doping concentration in the base electrode layer is prevented from being increased, the current gain is prevented from being increased, and the transient effect is improved.
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.
Fig. 1 is a core step of a transistor epitaxial growth method according to an embodiment of the present application.
Fig. 2 is a flowchart of a transistor epitaxial growth method according to an embodiment of the present disclosure.
Fig. 3-5 are schematic structural diagrams of a transistor epitaxial growth process.
Fig. 6 shows the result of the thermal annealing process performed on the base electrode layer without turning off the first precursor.
Fig. 7 shows the result of performing a thermal annealing process on the base electrode layer with the first precursor turned off.
Icon: 100-epitaxial structure; 200-a substrate; 300-subcollector layer; 400-etching a stop layer; 500-a collector layer; a 600-base electrode layer; 700-an emitter layer; 800-a cap layer; 900-ohmic contact layer.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. The components of the embodiments of the present application, generally described and illustrated in the figures herein, can be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present application, presented in the accompanying drawings, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In a conventional device, when a bias voltage is applied to a base-emitter junction, a carbon doped bond of a base electrode layer obtains energy and further splits carbon atoms, so that a p-type doping concentration of the base electrode layer is increased to increase a current gain, which is referred to as a transient effect (transient effect), and an embodiment of the present application provides a transistor epitaxial growth method for improving the transient effect of the device.
The core of the transistor epitaxial growth method provided by the embodiment of the application is as follows: and after the base electrode layer is formed, temporarily turning off the precursor, carrying out thermal annealing treatment on the base electrode layer in a time period when the precursor is turned off, and introducing the precursor to form the emitter layer after the thermal annealing treatment is finished. Please refer to fig. 1:
s01: introducing a first precursor to form a base electrode layer 600;
s02: turning off the first precursor, and performing thermal annealing treatment on the base electrode layer 600;
s03: a second precursor is introduced to the base electrode layer 600 after the thermal annealing process, thereby forming an emitter layer 700.
Referring to fig. 2, the present embodiment provides a method for epitaxial growth of a transistor, including the following steps:
s1: a substrate 200 is prepared.
Referring to fig. 3, the material of the substrate 200 may be GaAs or InP.
S2: sub-collector layer 300, etch stop layer 400, and collector layer 500 are sequentially formed on substrate 200.
Referring to fig. 4, the material of sub-collector layer 300 can be selected from GaAs (gallium arsenide-based HBT) or InGaAs (indium phosphide-based HBT).
S3: a first precursor is introduced to form the base electrode layer 600.
The material of the base electrode layer 600 may be selected from GaAs (gallium arsenide-based HBT) or InGaAs (indium phosphide-based HBT).
The base electrode layer 600 is p-doped, where the p-doping is carbon doping. The precursor for p-type doping can be selected from CBr4、CBrCl3、CCl4And the like.
The first precursor used for the base electrode layer 600 is one of group iii precursors or one of group v precursors. IIIThe family precursors include TMGa, TMAl, TMIn, TEGa, TEAl, TEIn. The five-group precursor comprises AsH3、TMAs、TBAs、PH3、TBP。
S4: the first precursor is turned off, and the base electrode layer 600 is thermally annealed.
Firstly, turning off a first precursor;
then, a thermal annealing treatment is performed. Wherein, in order to avoid the poor surface quality of the layer, the temperature of the thermal annealing treatment needs to be higher than the crystal growth temperature, and the temperature range which can be selected is as follows: 500-700 ℃, and the duration range of the thermal annealing treatment is as follows: 1min to 10 min. The thermal annealing process is an in-situ annealing process performed in a Metal Organic Chemical Vapor Deposition (MOCVD).
Proper thermal annealing can result in a device with a low rate of change of current gain, i.e., an indication that the current gain does not change significantly with the bias conditions under which the device is operated.
Under the conditions of the temperature range and the time length range, the thermal annealing treatment is performed on the base electrode layer 600, and at least two technical effects are achieved:
1. the thermal annealing treatment is performed on the base electrode layer 600, so that the carbon-doped bonding pattern in the base electrode layer 600 is stable, the carbon atoms are prevented from being cracked again after the carbon-doped bonding is obtained due to bias voltage during the operation of the device, the p-type doping concentration in the base electrode layer 600 is prevented from being increased, the current gain is prevented from being increased, and the transient effect is improved;
2. under the conditions of the temperature range and the time length range, the thermal annealing treatment can avoid the phenomenon of poor surface crystal quality caused by improper precursor proportion, and can also avoid the phenomenon of poor crystal quality caused by surface atomization or cracks and the like caused by the shutdown of the precursor in the process of interface temperature rise and drop or pressure rise.
To fully discuss the above technical effects, the following experiments were performed.
Experiment 1: in the case where the first precursor is not turned off, the thermal annealing process is performed on the base electrode layer 600, and the experimental data is as shown in fig. 6, in which the upper dotted line shows the change curve of the current gain after the thermal annealing process is performed on the base electrode layer 600, and the lower solid line shows the change curve of the current gain without the thermal annealing process being performed on the base electrode layer 600.
As can be seen from fig. 6, the rate of change in current gain was > 30% when the base electrode layer 600 was thermally annealed without turning off the first precursor.
Experiment 2: when the first precursor was turned off, the base electrode layer 600 was subjected to the thermal annealing treatment, and the experimental data is shown in fig. 7, in which the upper dotted line shows the change curve of the current gain after the thermal annealing treatment was performed on the base electrode layer 600, and the lower solid line shows the change curve of the current gain without the thermal annealing treatment being performed on the base electrode layer 600.
As can be seen from fig. 7, when the thermal annealing process is performed on the base electrode layer 600 with the first precursor turned off, the rate of change in the current gain is < 3%.
As can be seen, in the present embodiment, when the first precursor is turned off, the thermal annealing treatment is performed on the base electrode layer 600, which has the effects of reducing the change rate of the current gain and improving the transient effect.
S5: a second precursor is introduced to the base electrode layer 600 after the thermal annealing process, thereby forming an emitter layer 700.
Referring to fig. 5, the material of the emitter layer 700 is selected from AIGaAs, GaInP (gallium arsenide-based HBT), InP, InAlP (indium phosphide-based HBT). The second precursor used for the emitter layer 700 is one of group iii precursors or one of group v precursors. The group III precursor includes TMGa, TMAl, TMIn, TEGa, TEAl, and TEIn. The five-group precursor comprises AsH3、TMAs、TBAs、PH3And TBP. Preferably, the second precursor is different from the first precursor.
S6: a capping layer 800 and an ohmic contact layer 900 are sequentially prepared on the emitter layer 700.
The material of the cap layer 800 is selected from GaAs (gallium arsenide-based HBT) and InGaAs (indium phosphide-based HBT), and the material of the ohmic contact layer 900 is selected from InGaAs.
In the present embodiment, after the base electrode layer 600 is formed, the first precursor is turned off, and the base electrode layer 600 is subjected to a thermal annealing process, so that the transient effect can be improved, and the phenomenon of poor surface crystal quality can be avoided.
In other embodiments, the operation of turning off the precursor and performing the thermal annealing treatment on other layer structures can also be selected, and the effects of improving the transient effect and avoiding the poor quality of the surface crystal can also be achieved. Other layer structures may be the emitter layer 700, the cap layer 800, or the ohmic contact layer 900.
For example, after the second precursor is introduced to the base electrode layer 600 after the thermal annealing process to form the emitter layer 700, the second precursor may be turned off to perform the thermal annealing process on the emitter layer 700. The conditions of the thermal annealing treatment here are the same as those of the counter electrode layer 600, and the temperature ranges are: 500-700 ℃, the time length range is as follows: 1min to 10 min. The second precursor may also be one of the three family precursors or one of the five family precursors. Thus, the transient effect of the base electrode layer 600 can be improved.
For example, after the emitter layer 700 is formed, a third precursor is introduced on the emitter layer 700 to form the cap layer 800; the third precursor is then turned off and a thermal anneal process is performed on cap layer 800. Thus, the transient effect of the base electrode layer 600 can be improved. The third precursor used for the cap layer 800 is one of group iii precursors or one of group v precursors. The group III precursor includes TMGa, TMAl, TMIn, TEGa, TEAl, and TEIn. The five-group precursor comprises AsH3、TMAs、TBAs、PH3And TBP. Preferably, the third precursor is the same as the first precursor.
For another example, a fourth precursor is introduced on the cap layer 800 to form an ohmic contact layer 900; and then the fourth precursor is turned off, and the ohmic contact layer 900 is subjected to thermal annealing treatment. Thus, the transient effect of the base electrode layer 600 can be improved. The fourth precursor used in the ohmic contact layer 900 is one of group iii precursors or one of group v precursors. The group III precursor includes TMGa, TMAl, TMIn, TEGa, TEAl, and TEIn. The five-group precursor comprises AsH3、TMAs、TBAs、PH3And TBP. Preferably, the fourth precursor is different from the second precursor.
It can be seen that, in the transistor epitaxial growth method provided in this embodiment, in addition to performing the thermal annealing treatment on the base electrode layer 600, the thermal annealing treatment may also be selectively performed on the epitaxial layer after the base electrode layer 600, where the epitaxial layer includes the emitter layer 700, the cap layer 800, and the ohmic contact layer 900. The specific selection of epitaxial layers for thermal annealing can be flexibly determined according to the needs.
The embodiment also provides a preparation method of a transistor, which comprises the above-mentioned epitaxial growth method of the transistor, so as to further process the epitaxial structure 100 into the transistor.
The epitaxial structure 100 prepared by the method of the present embodiment can be suitable for processing into a heterojunction bipolar transistor HBT including a heterojunction indium gallium phosphide transistor device (InGaP HBT), a heterojunction indium phosphide transistor device (InP HBT), and a heterojunction aluminum gallium arsenide transistor device (AlGaAs HBT).
The transistor epitaxial growth method and the transistor preparation method provided by the embodiment have the beneficial effects that:
1. the carbon-doped bonding form in the device can be stabilized, the carbon-doped bonding is prevented from cracking out carbon atoms again after being subjected to energy under the conventional bias operation, the p-type doping concentration is prevented from increasing, the current gain is prevented from increasing, and the transient effect is improved;
2. the phenomenon of poor surface crystal quality caused by improper precursor proportion can be avoided, and the phenomenon of poor crystal quality such as surface atomization or cracks caused by precursor shutoff in the interface temperature rise and fall or pressure rise and fall process can also be avoided, so that other defects caused by the precursor shutoff to the preparation of the device can be avoided.
Only the example of applying the transistor epitaxial growth method to the HBT manufacturing method is described in detail in this application, but the transistor epitaxial growth method provided in this application may also be applied to the manufacturing of transistors with other structural forms, and details are not described herein, and as long as the concept of applying the turn-off precursor and performing the thermal annealing treatment provided in this application is applied, the method should fall within the scope of the claims of this application.
The epitaxial structure 100 and the transistor formed by the preparation method provided in the present application should also belong to the scope of the present application, and the epitaxial structure 100 and the transistor formed by the preparation method may also be applied to a power amplifier or other electrical appliances, and all should belong to the scope of the present application.
It should be noted that the numerical values mentioned in the present application, including the temperature value, the time length value, and the like, are only reliable numerical values obtained by the applicant through experiments and calculation, and it is not strictly limited that the corresponding parameters only can be the values. Those skilled in the art may make further experiments based on the scheme of the present application to obtain other values with similar effects, which do not depart from the core of the present application and should also fall within the scope of the protection claimed in the present application.
The materials used for the layer structures and the precursors in the present application are only the more reliable materials obtained by the applicant through experiments, and are not strictly limited to only use these materials. Those skilled in the art may make further experiments based on the solution of the present application to obtain other materials with similar effects, which do not depart from the core of the present application and should fall within the protection scope of the present application.
The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims (10)

1. A method of epitaxial growth of a transistor, comprising:
introducing a first precursor to form a base electrode layer (600);
turning off the first precursor, and carrying out thermal annealing treatment on the base electrode layer (600);
and introducing a second precursor to the base electrode layer (600) after the thermal annealing treatment to form an emitter layer (700).
2. The method for epitaxial growth of a transistor according to claim 1, wherein in the step of performing a thermal annealing process on the base electrode layer (600), the temperature range of the thermal annealing process is as follows: 500-700 ℃.
3. The method for epitaxial growth of a transistor according to claim 1, wherein in the step of performing a thermal annealing treatment on the base electrode layer (600), the duration of the thermal annealing treatment is in the range of: 1min to 10 min.
4. The method of claim 1 wherein the first precursor is one of a group iii precursor or one of a group v precursor.
5. The method of claim 4 wherein the group III precursor comprises TMGa, TMAl, TMIn, TEGa, TEAl, TEIn.
6. The method of claim 4 wherein the group five precursor comprises AsH3、TMAs、TBAs、PH3、TBP。
7. Transistor epitaxial growth method according to claim 1, characterized in that said step of forming an emitter layer (700) is followed by:
the second precursor is turned off, and the emitter layer (700) is thermally annealed.
8. Transistor epitaxial growth method according to claim 1 or 7, characterized in that said step of forming an emitter layer (700) is followed by:
introducing a third precursor on the emitter layer (700) to form a cap layer (800);
and turning off the third precursor, and carrying out thermal annealing treatment on the cap layer (800).
9. The method of epitaxial growth of a transistor according to claim 8, wherein said step of thermal annealing said cap layer (800) is followed by:
introducing a fourth precursor on the cap layer (800) to form an ohmic contact layer (900);
and turning off the fourth precursor, and carrying out thermal annealing treatment on the ohmic contact layer (900).
10. A method for manufacturing a transistor, comprising the method for epitaxial growth of a transistor according to any one of claims 1 to 9.
CN201910922368.6A 2019-09-27 2019-09-27 Transistor epitaxial growth method and preparation method of transistor Pending CN110660666A (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010026971A1 (en) * 1998-08-19 2001-10-04 Sharp Kabushiki Kaisha Method of manufacturing hetero-junction bipolar transistor
US20020125498A1 (en) * 2001-01-08 2002-09-12 Kopin Corporation Method of preparing indium phosphide heterojunction bipolar transistors
CN104465725A (en) * 2014-11-24 2015-03-25 华南理工大学 In0.3Ga0.7As thin film growing on Si substrate and preparing method
CN105428403A (en) * 2015-12-10 2016-03-23 中国电子科技集团公司第十三研究所 InP-based double-heterojunction bipolar-transistor epitaxial layer structure

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010026971A1 (en) * 1998-08-19 2001-10-04 Sharp Kabushiki Kaisha Method of manufacturing hetero-junction bipolar transistor
US20020125498A1 (en) * 2001-01-08 2002-09-12 Kopin Corporation Method of preparing indium phosphide heterojunction bipolar transistors
CN104465725A (en) * 2014-11-24 2015-03-25 华南理工大学 In0.3Ga0.7As thin film growing on Si substrate and preparing method
CN105428403A (en) * 2015-12-10 2016-03-23 中国电子科技集团公司第十三研究所 InP-based double-heterojunction bipolar-transistor epitaxial layer structure

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