CN110660650A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

Info

Publication number
CN110660650A
CN110660650A CN201910043381.4A CN201910043381A CN110660650A CN 110660650 A CN110660650 A CN 110660650A CN 201910043381 A CN201910043381 A CN 201910043381A CN 110660650 A CN110660650 A CN 110660650A
Authority
CN
China
Prior art keywords
photoresist
semiconductor device
layer
encapsulant
seed layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201910043381.4A
Other languages
Chinese (zh)
Other versions
CN110660650B (en
Inventor
郭宏瑞
李明潭
郭正铮
陆德源
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of CN110660650A publication Critical patent/CN110660650A/en
Application granted granted Critical
Publication of CN110660650B publication Critical patent/CN110660650B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004—Photosensitive materials
    • G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
    • G03F7/11—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers having cover layers or intermediate layers, e.g. subbing layers
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/40—Treatment after imagewise removal, e.g. baking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0272—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers for lift-off processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H01L21/0275—Photolithographic processes using lasers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/288—Deposition of conductive or insulating materials for electrodes conducting electric current from a liquid, e.g. electrolytic deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5386—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/19—Manufacturing methods of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68372—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to support a device or wafer when forming electrical connections thereto
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/20—Structure, shape, material or disposition of high density interconnect preforms
    • H01L2224/21—Structure, shape, material or disposition of high density interconnect preforms of an individual HDI interconnect
    • H01L2224/214—Connecting portions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1035—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047—Details of electrical connections between containers
    • H01L2225/1058—Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

Semiconductor devices and methods of fabricating conductive connections are provided. In an embodiment, an opening is formed in the photoresist by adjusting a center point of the focus region during the exposure process. Once the photoresist has been developed to form the openings, a post-development bake process is used to reshape the openings. Once reshaped, a conductive material is formed within the opening to assume the shape of the opening. Embodiments of the invention also relate to semiconductor devices and methods of manufacturing the same.

Description

Semiconductor device and method for manufacturing the same
Technical Field
Embodiments of the invention relate to a semiconductor device and a method of manufacturing the same.
Background
The semiconductor industry has experienced rapid growth due to the ever-increasing integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, this improvement in integration density comes from the repeated reduction in minimum feature size (e.g., scaling semiconductor process nodes to sub-20 nm nodes), which allows more components to be integrated into a given area. With the increasing demand for miniaturization, higher speed and higher bandwidth, and lower power consumption and delay in recent years, there is an increasing demand for smaller and more inventive packaging techniques for semiconductor dies.
With the further development of semiconductor technology, stacked and bonded semiconductor devices have become an effective alternative to further reduce the physical size of semiconductor devices. In stacked semiconductor devices, active circuits such as logic, memory, processor circuits, etc., are fabricated at least partially on separate substrates and then physically and electrically bonded together to form a functional device. Such a bonding process utilizes a complicated technique, and needs improvement.
Disclosure of Invention
An embodiment of the present invention provides a method of manufacturing a semiconductor device, the method including: applying a photoresist on the seed layer; exposing the photoresist to a patterned energy source having an in-focus region with a center point located below a surface of the photoresist facing the seed layer; developing the photoresist to form an opening; and plating an external connection into the opening.
Another embodiment of the present invention provides a method of manufacturing a semiconductor device, the method including: exposing a photoresist to a patterned energy source, the photoresist being on the encapsulant between the semiconductor die and the encapsulant via; developing the photoresist to form an opening having a first shape; performing a post-development bake process to reshape the opening into a second shape different from the first shape, wherein the second shape comprises a flare near a bottom of the opening; and plating a conductive material into the opening.
Still another embodiment of the present invention provides a semiconductor device including: a semiconductor die; an encapsulant encapsulating the semiconductor die; an encapsulant through-hole extending from a first side of the encapsulant to a second side of the encapsulant; a passivation layer over the encapsulant; and an external connection over the sealant, the external connection comprising: a first portion having a first width, the first portion extending through the passivation layer; a second portion having a second width greater than the first width, the second portion being located outside the passivation layer; and a tapered portion extending from the second portion to the first portion.
Drawings
Various aspects of the invention are best understood from the following detailed description when read with the accompanying drawing figures. It should be emphasized that, in accordance with the standard practice in the industry, various features are not drawn to scale and are used for illustration purposes only. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.
Fig. 1 illustrates formation of interposer vias according to some embodiments.
Fig. 2 illustrates a semiconductor device according to some embodiments.
Fig. 3 illustrates placement of a semiconductor device according to some embodiments.
Fig. 4 illustrates the sealing of interposer vias and semiconductor devices according to some embodiments.
FIG. 5 illustrates the placement of a photoresist according to some embodiments.
Fig. 6A-6D illustrate exposure of a photoresist according to some embodiments.
Fig. 7A-7B illustrate development of a photoresist according to some embodiments.
Fig. 8 illustrates a post-development annealing process according to some embodiments.
Fig. 9 illustrates the formation of an external connection according to some embodiments.
Fig. 10 illustrates patterning of a seed layer according to some embodiments.
Fig. 11 illustrates the formation of conductive bumps on external connections according to some embodiments.
Fig. 12 illustrates debonding of a carrier wafer according to some embodiments.
Fig. 13 illustrates bonding of a second package according to some embodiments.
FIG. 14 illustrates segmentation according to some embodiments.
Detailed Description
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the dimensions of the elements are not limited to the disclosed ranges or values, but may depend on the process conditions and/or desired properties of the device. Further, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, such that the first and second features may not be in direct contact. Various components may be arbitrarily drawn in different scales for simplicity and clarity.
Furthermore, spatial relationship terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein to describe one element or component's relationship to another element or component as illustrated in the figures for ease of description. Spatial relationship terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial relationship descriptors used herein interpreted accordingly as such.
Referring now to fig. 1, a carrier substrate 101 is shown with an adhesion layer 103, a polymer layer 105, and a first seed layer 107 over the carrier substrate 101. For example, the carrier substrate 101 includes a silicon-based material (e.g., glass or silicon oxide) or other material (e.g., aluminum oxide), a combination of any of these materials, and the like. The carrier substrate 101 is planar in order to accommodate attachment of semiconductor devices, such as a first semiconductor device 201 and a second semiconductor device 301 (not shown in fig. 1, but shown and discussed below with reference to fig. 2-3).
An adhesive layer 103 is placed on the carrier substrate 101 to facilitate adhesion of the above structure (e.g., the polymer layer 105). In one embodiment, the adhesive layer 103 may comprise an ultraviolet glue that loses adhesion when exposed to ultraviolet light. However, other types of adhesives may also be used, such as pressure sensitive adhesives, radiation curable adhesives, epoxies, combinations of these, and the like. The adhesive layer 103 may be placed on the carrier substrate 101 in a semi-liquid or gel form, which is easily deformable under pressure.
The polymer layer 105 is placed on the adhesive layer 103 and once the first semiconductor device 201 and the second semiconductor device 301 are attached, the polymer layer 105 is used to provide protection for the first semiconductor device 201 and the second semiconductor device 301, for example. In one embodiment, polymer layer 105 may be Polybenzoxazole (PBO), but any suitable material may be used, such as polyimide or a polyimide derivative, Solder Resist (SR), or ajinomoto laminate film (ABF). The polymer layer 105 may be placed to a thickness of between about 2 μm and about 15 μm, for example about 5 μm, using, for example, a spin coating process, although any suitable method and thickness may be used.
A first seed layer 107 is formed on the polymer layer 105. In one embodiment, the first seed layer 107 is a thin layer of conductive material that facilitates the formation of a thicker layer during subsequent processing steps. The first seed layer 107 may comprise aboutA thick titanium layer, followed by about
Figure BDA0001948332740000042
A thick copper layer. The first seed layer 107 may be generated using a process such as sputtering, evaporation or PECVD processes, depending on the desired material. The first seed layer 107 may be formed to have between about 0A thickness between 3 μm and about 1 μm, for example about 0.5 μm.
Fig. 1 also shows the placement and patterning of a photoresist 109 over the first seed layer 107. In one embodiment, the photoresist 109 may be placed on the first seed layer 107 to a height between about 50 μm and about 250 μm, for example, about 120 μm, using, for example, a spin coating technique. Once in place, the photoresist 109 may then be patterned by exposing the photoresist 109 to a patterned energy source (e.g., a patterned light source) so as to cause a chemical reaction that causes a physical change in those portions of the photoresist 109 that are exposed to the patterned light source. A developer is then applied to the exposed photoresist 109 to selectively remove either the exposed portions of the photoresist 109 or the unexposed portions of the photoresist 109 according to a desired pattern using physical changes.
In one embodiment, the pattern formed in the photoresist 109 is a pattern for the via 111. The via 111 is formed to be located at a position on different sides of the subsequently attached devices (e.g., the first semiconductor device 201 and the second semiconductor device 301). However, any suitable arrangement of the pattern for the vias 111 may be utilized, for example by positioning such that the first semiconductor device 201 and the second semiconductor device 301 are placed on opposite sides of the vias 111.
In one embodiment, vias 111 are formed within photoresist 109. In one embodiment, the vias 111 comprise one or more conductive materials, such as copper, tungsten, other conductive metals, and the like, and may be formed, for example, by electroplating, electroless plating, and the like. In one embodiment, an electroplating process is used, wherein the first seed layer 107 and the photoresist 109 are immersed or immersed in an electroplating solution. The first seed layer 107 surface is electrically connected to the negative side of an external DC power source so that the first seed layer 107 serves as a cathode in the electroplating process. A solid conductive anode (e.g., a copper anode) is also immersed in the solution and attached to the positive side of the power supply. The atoms from the anode dissolve in the solution and the cathode (e.g., first seed layer 107) picks up the dissolved atoms from the solution, plating the exposed conductive regions of the first seed layer 107 within the openings of the photoresist 109.
Once the via 111 is formed using the photoresist 109 and the first seed layer 107, the photoresist 109 (not shown in fig. 1, but seen in fig. 3 below) may be removed using a suitable removal process. In one embodiment, the photoresist 109 may be removed using a plasma ashing process, whereby the temperature of the photoresist 109 may be increased until the photoresist 109 undergoes thermal decomposition and may be removed. However, any other suitable process, such as wet stripping, may be used. Removing the photoresist 109 may expose portions of the underlying first seed layer 107.
Once exposed, removal of the exposed portions of the first seed layer 107 (not shown in fig. 1, but seen in fig. 3 below) may be performed. In one embodiment, the exposed portions of the first seed layer 107 (e.g., those portions not covered by the vias 111) may be removed by, for example, a wet or dry etch process. For example, in a dry etching process, the reactant may be introduced to the first seed layer 107 using the via hole 111 as a mask. In another embodiment, an etchant may be sprayed or otherwise brought into contact with the first seed layer 107 to remove the exposed portions of the first seed layer 107. After the exposed portions of the first seed layer 107 are etched away, a portion of the polymer layer 105 is exposed between the vias 111.
Fig. 2 shows a first semiconductor device 201 to be attached to the polymer layer 105 (not shown in fig. 2, but shown and described below with reference to fig. 3) within the via 111. In one embodiment, the first semiconductor device 201 includes a first substrate 203, a first active device (not separately shown), a first metallization layer 205, a first contact pad 207, a first passivation layer 211, and a first external connection 209. The first substrate 203 may include an active layer of a doped or undoped bulk silicon or silicon-on-insulator (SOI) substrate. Typically, the SOI substrate comprises a layer of semiconductor material, such as silicon, germanium, silicon germanium, SOI, Silicon Germanium On Insulator (SGOI), or combinations thereof. Other substrates that may be used include multilayer substrates, gradient substrates, or hybrid orientation substrates.
The first active device includes various active and passive devices, such as capacitors, resistors, inductors, etc., which may be used to create the desired structural and functional requirements of the design of the first semiconductor device 201. The first active devices may be formed within the first substrate 203 or on the first substrate 203 using any suitable method.
A first metallization layer 205 is formed over the first substrate 203 and the first active devices and is designed to connect the various active devices to form functional circuitry. In one embodiment, the first metallization layer 205 is formed from alternating layers of dielectric and conductive materials, and may be formed by any suitable process (e.g., deposition, damascene, dual damascene, etc.). In one embodiment, there may be four metallization layers separated from the first substrate 203 by at least one interlayer dielectric layer (ILD), but the exact number of first metallization layers 205 depends on the design of the first semiconductor device 201.
A first contact pad 207 may be formed over the first metallization layer 205 and in electrical contact with the first metallization layer 205. The first contact pad 207 may comprise aluminum, but other materials may be used, such as copper. A deposition process such as sputtering may be used to form a material layer (not shown) and then portions of the material layer may be removed by a suitable process (e.g., photolithographic masking and etching) to form the first contact pads 207. However, any other suitable process may be utilized to form the first contact pad 207. The first contact pad 207 may be formed to have a thickness between about 0.5 μm and about 4 μm, for example about 1.45 μm.
A first passivation layer 211 may be formed on the first substrate 203 over the first metallization layer 205 and the first contact pad 207. The first passivation layer 211 may be made of one or more suitable dielectric materials, such as silicon oxide, silicon nitride, low-k dielectrics (e.g., carbon-doped oxides), very low-k dielectrics (e.g., porous carbon-doped silicon dioxide), combinations thereof, and the like. The first passivation layer 211 may be formed by a process such as Chemical Vapor Deposition (CVD), but any suitable process may be used and may have a thickness between about 0.5 μm and about 5 μm, for example about
Figure BDA0001948332740000061
The first external connection 209 may be formed to provide a conductive area for contact between the first contact pad 207 and, for example, the first redistribution layer 501 (not shown in fig. 2, but shown and described below with reference to fig. 5). In one embodiment, the first external connection 209 may be a conductive pillar and may be formed by initially forming a photoresist (not shown) on the first passivation layer 211 to a thickness between about 5 μm and about 20 μm (e.g., about 10 μm). The photoresist may be patterned to expose portions of the first passivation layer through which the conductive pillars will extend. Once patterned, the photoresist may then be used as a mask to remove desired portions of the first passivation layer 211, thereby exposing those portions of the underlying first contact pad 207 that will be in contact with the first external connection 209.
The first external connection 209 may be formed within an opening of both the first passivation layer 211 and the photoresist. The first external connection 209 may be formed of a conductive material such as copper, but other conductive materials such as nickel, gold, or metal alloys, combinations of these, or the like may also be used. In addition, the first external connection member 209 may be formed using a process such as plating, by which a current flows through a conductive portion of the first contact pad 207 desired to form the first external connection member 209, and the first contact pad 207 is immersed in a solution. The solution and current deposit, for example, copper within the openings to fill and/or overfill the openings of the photoresist and first passivation layer 211 to form the first external connection 209. Then, the excess conductive material and the photoresist located outside the opening of the first passivation layer 211 may be removed using, for example, an ashing process, a Chemical Mechanical Polishing (CMP) process, a combination of these, or the like.
However, as one of ordinary skill in the art will appreciate, the above-described process of forming the first external connection 209 is merely one such description and is not meant to limit the embodiments to this precise process. Rather, the processes described are merely illustrative, as any suitable process for forming the first external connection 209 may be used. All suitable processes are fully intended to be included within the scope of embodiments of the present invention.
On a side of the first substrate 203 opposite the first metallization layer 205, a Die Attach Film (DAF)213 may be formed to assist in attaching the first semiconductor device 201 to the polymer layer 105. In one embodiment, die attach film 213 is an epoxy, phenolic, acrylic rubber, silica filler, or a combination thereof, and is applied using a lamination technique. However, any other suitable material and formation method may be used.
Fig. 3 shows a first semiconductor device 201 and a second semiconductor device 301 placed on the polymer layer 105. In one embodiment, the second semiconductor device 301 may include a second substrate 303, a second active device (not separately shown), a second metallization layer 305, a second contact pad 307, a second passivation layer 311, and a second external connection 309. In one embodiment, the second substrate 303, the second active device, the second metallization layer 305, the second contact pad 307, the second passivation layer 311 and the second external connection 309 may be similar to the first substrate 203, the first active device, the first metallization layer 205, the first contact pad 207, the first passivation layer 211 and the first external connection 209, but they may also be different.
In one embodiment, the first semiconductor device 201 and the second semiconductor device 301 may be placed on the polymer layer 105 using, for example, a pick and place process. However, any other method of placing the first semiconductor device 201 and the second semiconductor device 301 may be used.
Fig. 4 shows the sealing of the via 111, the first semiconductor device 201 and the second semiconductor device 301. The sealing may be performed in a molding apparatus (not separately shown in fig. 4), which may include a top molding portion and a bottom molding portion separate from the top molding portion. When the top mold portion is lowered adjacent to the bottom mold portion, mold cavities for the carrier substrate 101, the vias 111, the first semiconductor devices 201, and the second semiconductor devices 301 may be formed.
During the sealing process, the top mold portion may be placed adjacent to the bottom mold portion, thereby enclosing the carrier substrate 101, the vias 111, the first semiconductor device 201, and the second semiconductor device 301 within the mold cavity. Once closed, the top and bottom mold portions may form a hermetic seal to control the flow of gas into and out of the mold cavity. Once sealed, the encapsulant 401 may be placed within the molding cavity. The encapsulant 401 may be a molding compound resin such as polyimide, PPS, PEEK, PES, heat resistant crystalline resin, combinations thereof, and the like. The encapsulant 401 may be placed in the mold cavity before the top and bottom mold portions are aligned, or may be injected into the mold cavity through an injection port.
Once the encapsulant 401 is placed into the mold cavity such that the encapsulant 401 encapsulates the carrier substrate 101, the vias 111, the first semiconductor device 201, and the second semiconductor device 301, the encapsulant 401 may be cured to harden the encapsulant 401 for optimal protection. While the precise curing process depends at least in part on the particular material selected for the encapsulant 401, in embodiments where a molding compound is selected as the encapsulant 401, curing may be performed for about 60 seconds to about 3000 seconds, for example, about 600 seconds, by a process such as heating the encapsulant 401 to between about 100 ℃ and about 130 ℃ (e.g., about 125 ℃). Additionally, an initiator and/or catalyst may be included in the encapsulant 401 to better control the curing process.
However, as one of ordinary skill in the art will appreciate, the above-described curing process is merely an exemplary process and is not meant to limit the present embodiments. Other curing processes may be used, such as irradiation or even allowing the encapsulant 401 to harden at ambient temperature. Any suitable curing process may be used, and all such processes are fully intended to be included within the scope of the embodiments discussed herein.
Fig. 4 also shows thinning of the encapsulant 401 to expose the vias 111, the first semiconductor device 201, and the second semiconductor device 301 for further processing. The thinning may be performed, for example, using a mechanical grinding or Chemical Mechanical Polishing (CMP) process, whereby the encapsulant 401, the first semiconductor device 201, and the second semiconductor device 301 are reacted and the encapsulant 401, the first semiconductor device 201, and the second semiconductor device 301 are ground using a chemical etchant and an abrasive until the via 111, the first external connection 209 (on the first semiconductor device 201), and the second external connection 309 (on the second semiconductor device 301) are exposed. In this way, the first semiconductor device 201, the second semiconductor device 301, and the via hole 111 may have a flat surface, which is also coplanar with the sealant 401.
However, while the above-described CMP process is presented as one illustrative embodiment, it is not intended to limit the embodiment. Any other suitable removal process may be used to thin the encapsulant 401, the first semiconductor device 201, and the second semiconductor device 301 and expose the vias 111. For example, a series of chemical etches may be used. This process and any other suitable processes may be utilized to thin encapsulant 401, first semiconductor device 201, and second semiconductor device 301, and all such processes are fully intended to be included within the scope of the embodiments.
Alternatively, after thinning the sealant 401, the through hole 111, the first external connection member 209, and the second external connection member 309 may be recessed within the sealant 401. In one embodiment, the via 111, the first external connection 209, and the second external connection 309 may be recessed using, for example, an etching process that utilizes an etchant that is selective to the material (e.g., copper) of the via 111, the first external connection 209, and the second external connection 309. The via 111, the first external connection 209 and the second external connection 309 may be recessed to a depth of between about 20 μm and about 300 μm, for example about 180 μm.
Fig. 5 illustrates a cross-sectional view of the formation of a first redistribution layer (RDL)501, a second redistribution layer 505, and a third redistribution layer 509 to interconnect the first semiconductor device 201, the second semiconductor device 301, and the via 111. In one embodiment, first redistribution layer 501 may be formed by initially forming a seed layer (not shown) of a titanium-copper alloy by a suitable formation process (e.g., CVD or sputtering). A photoresist (also not shown) may then be formed to cover the seed layer, and then the photoresist may be patterned to expose those portions of the seed layer where it is desired to locate the first redistribution layer 501.
Once the photoresist is formed and patterned, a conductive material, such as copper, may be formed on the seed layer by a deposition process, such as plating. The conductive material may be formed to have a thickness between about 1 μm and about 10 μm, for example about 5 μm. However, while the materials and methods discussed are suitable for forming conductive materials, these materials are merely exemplary. Any other suitable material (e.g., AlCu or Au) and any other suitable formation process (e.g., CVD or PVD) may be used to form the first redistribution layer 501.
Once the conductive material is formed, the photoresist may be removed by a suitable removal process (e.g., ashing). In addition, after removing the photoresist, those portions of the seed layer covered by the photoresist may be removed by a suitable etching process, for example using the conductive material as a mask.
Fig. 5 also shows that a third passivation layer 503 is formed over the first redistribution layer 501 to provide protection and isolation for the first redistribution layer 501 and other underlying structures. In one embodiment, the third passivation layer 503 may be Polybenzoxazole (PBO), but any suitable material may be used, such as polyimide or a polyimide derivative. The third passivation layer 503 may be placed to a thickness between about 5 μm and about 25 μm, for example about 7 μm, using, for example, a spin coating process, although any suitable method and thickness may be used.
After forming the third passivation layer 503, first openings 504 (only one of which is shown in fig. 5 for clarity) may be made through the third passivation layer 503 by removing portions of the third passivation layer 503 to expose at least portions of the underlying first redistribution layer 501. The first opening 504 allows contact between the first redistribution layer 501 and a second redistribution layer 505 (described further below). The first opening 504 may be formed using a suitable photolithographic masking and etching process, but any suitable process may be used to expose portions of the first redistribution layer 501.
The second redistribution layer 505 may be formed to provide additional routing and connections and electrically connected to the first redistribution layer 501. In one embodiment, the second redistribution layer 505 may be formed similarly to the first redistribution layer 501. For example, a seed layer may be formed, a photoresist may be placed and patterned on top of the seed layer, and a conductive material may be electroplated into the patterned openings through the photoresist. Once formed, the photoresist may be removed, the underlying seed layer may be etched, the second redistribution layer 505 may be covered by a fourth passivation layer 507 (which may be similar to the third passivation layer 503), and the fourth passivation layer 507 may be patterned to form second openings 506 (only one of which is shown in fig. 5 for clarity) and to expose conductive portions of the underlying second redistribution layer 505.
A third redistribution layer 509 may be formed to provide additional routing and electrical connections to the second redistribution layer 505. In one embodiment, the third redistribution layer 509 may be formed using similar materials and processes as the first redistribution layer 501. For example, a seed layer may be formed, a photoresist may be placed and patterned in a desired pattern of the third redistribution layer 509 on top of the seed layer, a conductive material may be plated into the patterned openings of the photoresist, the photoresist removed, and the seed layer etched.
However, in addition to simply rerouting the electrical connections (similar to the second redistribution layer 505), the third redistribution layer 509 may also include bond pads that will be used to form electrical connections to, for example, the above third external connectors 901 (described further below). The bonding pads may be shaped to make appropriate physical and electrical connections with the third external connector 901.
Once the third redistribution layer 509 is formed, the third redistribution layer 509 may be covered by a fifth passivation layer 511. The fifth passivation layer 511 may be formed of a polymer such as PBO, similar to the third passivation layer 503, or may be formed of a material (e.g., polyimide or a polyimide derivative) similar to the third passivation layer 503. The fifth passivation layer 511 may be formed to have a thickness between about 2 μm and about 15 μm, for example, about 5 μm.
Once in place over the third redistribution layer 509, the fifth passivation layer 511 may planarize with the third redistribution layer 509. In one embodiment, the planarization may be performed using, for example, a chemical mechanical polishing process, whereby an etchant and an abrasive are used with a rotating platen to chemically and mechanically remove portions of the fifth passivation layer 511 until the fifth passivation layer 511 is coplanar with the third redistribution layer 509. However, any suitable planarization process may be used, such as a series of one or more etching or mechanical grinding processes.
After forming and planarizing the fifth passivation layer 511, a sixth passivation layer 513 may be placed and patterned on the fifth passivation layer 511 and the third redistribution layer 509. In one embodiment, the sixth passivation layer 513 may be a similar material (e.g., PBO) as the fifth passivation layer 511, and the sixth passivation layer 513 may be patterned to expose portions of the underlying third redistribution layer 509. In one embodiment, the sixth passivation layer 513 may be patterned using a photolithographic masking and etching process, whereby a photoresist is deposited and patterned and then used as a mask during the etching process in order to remove portions of the sixth passivation layer 513 and expose portions of the third redistribution layer 509. However, any suitable method of patterning the sixth passivation layer 513 may be used.
After forming and patterning the sixth passivation layer 513, a second seed layer 515 is deposited over the sixth passivation layer 513. In one embodiment, the second seed layer 515 is a thin layer of conductive material that facilitates the formation of thicker layers in subsequent processing steps. The second seed layer 515 may comprise a layer of titanium of about 1000 angstroms followed by a layer of copper of about 5000 angstroms thick. A process such as sputtering, evaporation, or PECVD processes may be used to create the second seed layer 515, depending on the desired material. The second seed layer 515 may be formed to have a thickness between about 0.3 μm and about 1 μm, for example, about 0.5 μm.
Once the second seed layer 515 is deposited, a photoresist 517 may be placed on the second seed layer 515 in preparation for forming the third external connection 901. In one embodiment, photoresist 517 comprises a photoresist polymer resin and one or more photoactive compounds (PACs) in a photoresist solvent. In one embodiment, the photoresist polymer resin may comprise a hydrocarbon structure (e.g., an alicyclic hydrocarbon structure) containing one or more groups to be decomposed (e.g., acid labile groups) or otherwise reacted upon mixing with an acid, a base, or a radical generated by PAC (as further described below with reference to fig. 6A). In one embodiment, the hydrocarbon structure comprises a repeating unit that forms the backbone of the photoresist polymer resin. The repeating units may include acrylates, methacrylates, crotonates, vinyl esters, maleic diesters, fumaric diesters, itaconic diesters, (meth) acrylonitriles, (meth) acrylamides, styrenes, vinyl ethers, combinations of these, and the like.
Specific structures of repeating units that may be used in the hydrocarbon structure include methyl acrylate, ethyl acrylate, n-propyl acrylate, isopropyl acrylate, n-butyl acrylate, isobutyl acrylate, t-butyl acrylate, n-hexyl acrylate, 2-ethylhexyl acrylate, acetoxyethyl acrylate, phenyl acrylate, 2-hydroxyethyl acrylate, 2-methoxyethyl acrylate, 2-ethoxyethyl acrylate, 2- (2-methoxyethoxy) ethyl acrylate, cyclohexyl acrylate, benzyl acrylate, 2-alkyl-2-adamantyl (meth) acrylate or (1-adamantyl) (meth) dialkyl acrylate, methyl methacrylate, ethyl methacrylate, n-propyl methacrylate, n-butyl methacrylate, isobutyl methacrylate, isopropyl acrylate, n-butyl acrylate, isobutyl acrylate, n-butyl, T-butyl methacrylate, n-hexyl methacrylate, 2-ethylhexyl methacrylate, acetoxyethyl methacrylate, phenyl methacrylate, 2-hydroxyethyl methacrylate, 2-methoxyethyl methacrylate, 2-ethoxyethyl methacrylate, 2- (2-methoxyethoxy) ethyl methacrylate, cyclohexyl methacrylate, benzyl methacrylate, 3-chloro-2-hydroxypropyl methyl methacrylate acrylate, 3-acetoxy-2-hydroxypropyl methacrylate, 3-chloroacetyloxy-2-hydroxypropyl methacrylate, butyl crotonate, hexyl crotonate, and the like. Examples of vinyl esters include vinyl acetate, vinyl propionate, vinyl butyrate, vinyl methoxyacetate, vinyl benzoate, dimethyl maleate, diethyl maleate, dibutyl maleate, dimethyl fumarate, diethyl fumarate, dibutyl fumarate, dimethyl itaconate, diethyl itaconate, dibutyl itaconate, acrylamide, methacrylamide, ethyl acrylamide, propyl acrylamide, n-butyl acrylamide, t-butyl acrylamide, cyclohexyl acrylamide, 2-methoxyethyl acrylamide, dimethyl acrylamide, diethyl acrylamide, phenyl acrylamide, benzyl acrylamide, methacrylamide, methyl methacrylamide, ethyl methacrylamide, propyl methacrylamide, n-butyl methacrylamide, t-butyl methacrylamide, cyclohexyl methacrylamide, methyl acrylamide, n-butyl methacrylamide, n, 2-methoxyethyl methacrylamide, dimethyl methacrylamide, diethyl methacrylamide, phenyl methacrylamide, benzyl methacrylamide, methyl vinyl ether, butyl vinyl ether, hexyl vinyl ether, methoxyethyl vinyl ether, dimethylaminoethyl vinyl ether, and the like. Examples of styrene include styrene, methylstyrene, dimethylstyrene, trimethylstyrene, ethylstyrene, isopropylstyrene, butylstyrene, methoxystyrene, butoxystyrene, acetoxystyrene, chlorostyrene, dichlorostyrene, bromostyrene, vinyl benzoate, α -methylstyrene, maleimide, vinylpyridine, vinylpyrrolidone, vinylcarbazole, combinations thereof, and the like.
In one embodiment, the repeating units of the hydrocarbon structure may also have a substituted monocyclic or polycyclic hydrocarbon structure, or the monocyclic or polycyclic hydrocarbon structure may be a repeating unit to form an alicyclic hydrocarbon structure. Specific examples of monocyclic structures that can be used include bicycloalkanes, tricycloalkanes, tetracycloalkanes, cyclopentanes, cyclohexanes, and the like. Specific examples of polycyclic structures that may be used include adamantane, norbornane, isobornane, tricyclodecane, tetracyclododecane, and the like.
The decomposed group (also referred to as a leaving group, or in embodiments where PAC is a photoacid generator, an acid labile group) is attached to the hydrocarbon structure to allow it to react with the acid/base/free radical generated by PAC during exposure. In one embodiment, the group to be decomposed may be a carboxylic acid group, a fluorinated alcohol group, a phenolic alcohol group, a sulfonic acid group, a sulfonamide group, a sulfonimide group, an (alkylsulfonyl) (alkylcarbonyl) methylene, an (alkylsulfonyl) (alkylcarbonyl) imino, a bis (alkylcarbonyl) methylene, a bis (alkylcarbonyl) imino, a bis (alkylsulfonyl) methylene, a bis (alkylsulfonyl) imino, a tris (alkylcarbonylmethylene), a tris (alkylsulfonyl) methylene, combinations thereof, and the like. Specific groups that may be used for the fluorinated alcohol group include fluorinated hydroxyalkyl groups, such as hexafluoroisopropanol groups. Specific groups that may be used for the carboxylic acid group include acrylic groups, methacrylic groups, and the like.
In one embodiment, the photoresist polymer resin may also contain other groups attached to the hydrocarbon structure, which help to improve various properties of the polymerizable resin. For example, the inclusion of the lactone group in the hydrocarbon structure helps to reduce the amount of line edge roughness after developing the photoresist 517, thereby helping to reduce the number of defects that occur during development. In one embodiment, the lactone group can include a 5-7 membered ring, but any suitable lactone structure can be used for the lactone group.
The photoresist polymer resin may also include groups that may help increase the adhesion of the photoresist 517 to the underlying structure. In one embodiment, polar groups may be used to help increase adhesion, and polar groups that may be used in this embodiment include hydroxyl, cyano, and the like, although any suitable polar group may be used.
Optionally, the photoresist polymer resin may further comprise one or more alicyclic hydrocarbon structures that do not contain a group to be decomposed. In one embodiment, hydrocarbon structures that do not contain a group that will decompose can include structures such as 1-adamantyl (meth) acrylate, tricyclodecyl (meth) acrylate, cyclohexyl (meth) acrylate, combinations of these, and the like.
In addition, photoresist 517 also contains one or more PACs. PAC may be a photoactive component, such as a photoacid generator, photobase generator, radical generator, and the like, and PAC may be positive-acting or negative-acting. In embodiments where the PAC is a photoacid generator, the PAC may include halogenated triazines, onium salts, diazonium salts, aromatic diazonium salts, onium salts, sulfonium salts, iodonium salts, imide sulfonates, oxime sulfonates, diazodisulfones, disulfones, o-nitrobenzyl sulfonates, sulfonated esters, halosulfonyloxydimethylimides, diazodisulfones, alpha-cyanooxysulfonates, imide sulfonates, ketodiazosulfones, sulfonyldiazepines, 1, 2-bis (arylsulfonyl) hydrazines, nitrobenzyl esters, and s-triazine derivatives, suitable combinations of these, and the like.
Specific examples of photoacid generators that may be used include α - (trifluoromethylsulfonyloxy) -bicyclo [2.2.1] hept-5-ene-2, 3-dicarbonimide (MDT), N-hydroxynaphthalimide (DDSN), benzoin tosylate, t-butylphenyl α - (p-toluenesulfonyloxy) -acetic acid methyl ester and t-butyl α - (p-toluenesulfonyloxy) -acetic acid methyl ester, triarylsulfonium and diaryliodohexafluoroantimonate, hexafluoroarsenate, trifluoromethanesulfonate, iodoperfluorooctanesulfonate, N-camphorsulfonyloxynaphthalimide, N-pentafluorophenylsulfonyloxynaphthalimide, ionic iodosulfonates such as diaryliodonium (alkyl or aryl) sulfonate and bis (di-t-butylphenyl) iodoborneol sulfonate, perfluoroalkyl sulfonates such as perfluoropentane sulfonate, perfluoropentane sulfonate, Perfluorooctanesulfonate, perfluoromethanesulfonate, aryl (e.g., phenyl or benzyl) triphenylsulfonium triflate, such as triflate or bis- (tert-butylphenyl) iodotriflate; pyrogallol derivatives (e.g., trimesic acid of pyrogallol), trifluoromethanesulfonic acid esters of hydroxyimides, α' -bis-sulfonyl-diazomethane, sulfonic acid esters of nitro-substituted benzyl alcohols, naphthoquinone-4-diazides, alkyl disulfones, and the like.
In embodiments where the PAC is a free radical generator, the PAC may comprise N-phenylglycine, aromatic ketones (e.g., benzophenone), N '-tetramethyl-4, 4' -diaminobenzophenone, N '-tetraethyl-4, 4' -diaminobenzophenone, 4-methoxy-4 '-dimethylaminobenzone, 3' -dimethyl-4-methoxybenzophenone, p '-bis (dimethylamino) benzophenone, p' -bis (diethylamino) benzophenone, anthraquinone, 2-ethylanthraquinone, naphthoquinones, and phenanthraquinones, benzoins, such as benzoin, benzoin methyl ether, benzoin ethyl ether, benzoin propyl ether, benzoin-N-butyl ether, benzoin-phenyl ether, methylbenzoin, and ethylbenzoin, Benzyl derivatives, e.g. benzyl, benzyldiamyldithio and benzyldimethylpyridine, acridine derivatives, e.g. 9-phenylacridine and 1, 7-bis (9-acridinyl) heptane, thioxanthones, e.g. 2-chlorothioxanthone, 2-methylthioxanthone, 2, 4-diethyl-2, 4-dimethylthioxanthone and 2-isopropylthioxanthone, acetophenones, e.g. 1, 1-dichloroacetophenone, p-tert-butyldichloro-acetophenone, 2-diethoxyacetophenone, 2-dimethoxy-2-phenylacetophenone, 2-dichloro-4-phenoxyacetophenone, 2,4, 5-triarylimidazole dimers, e.g. 2- (o-chlorophenyl) -4, 5-diphenylimidazole dimer, dimer, 2- (o-chlorophenyl) -4, 5-di-m-methoxyphenyl imidazole dimer, 2- (o-fluorophenyl) -4, 5-diphenylimidazole dimer, 2- (o-methoxyphenyl) -4, 5-diphenylimidazole dimer, 2- (p-methoxyphenyl) -4, 5-diphenylimidazole dimer, 2, 4-di (p-methoxyphenyl) -5-phenylimidazole dimer, 2- (2, 4-dimethoxyphenyl) -4, 5-diphenylimidazole dimer, and 2- (p-methylmercaptophenyl) -4, 5-diphenylimidazole dimer, suitable combinations of these, and the like.
In embodiments where the PAC is a photobase generator, the PAC may comprise quaternary ammonium dithiocarbamates, alpha aminoketones, oxime-carbamate containing molecules, such as dibenzobenzoximehexamethylenediurea, ammonium tetravanadyl borate, and N- (2-nitrobenzyloxycarbonyl) cyclic amines, suitable combinations of these, and the like. However, as one of ordinary skill in the art will recognize, the chemical compounds listed herein are intended only as illustrative examples of PACs and are not intended to limit the embodiments to only those PACs specifically described. Rather, any suitable PAC may be used, and all such PACs are fully intended to be included within the scope of the present embodiments.
The components of the photoresist 517 may be placed in a photoresist solvent to aid in the mixing and placement of the photoresist 517. To facilitate the mixing and placement of the photoresist 517, the photoresist solvent is selected based at least in part on the materials selected for the photoresist polymer resin and the PAC. In particular, the photoresist solvent is selected such that the photoresist polymer resin and PAC can be uniformly dissolved and distributed in the photoresist solvent.
In one embodiment, the photoresist solvent may be an organic solvent, and may comprise any suitable solvent, such as ketones, alcohols, polyols, ethers, glycol ethers, cyclic ethers, aromatic hydrocarbons, esters, propionates, lactates, alkylene esters, glycol monoalkyl ethers, alkyl lactates, alkyl alkoxy propionates, cyclic lactones, ring-containing monoketone compounds, alkylene carbonates, alkyl alkoxy acetates, alkyl pyruvates, lactates, ethylene glycol alkyl ether acetates, diethylene glycols, propylene glycol alkyl ether acetates, alkyl glycol alkyl ester ether esters, alkylene glycol monoalkyl esters, and the like.
Specific examples of materials that can be used as a photoresist solvent for photoresist 517 include acetone, methanol, ethanol, toluene, xylene, 4-hydroxy-4-methyl-2-pentanone, tetrahydrofuran, methyl ethyl ketone, cyclohexanone, methyl isoamyl ketone, 2-heptanone, ethylene glycol monoacetate, ethylene glycol dimethyl ether, ethylene glycol methyl ethyl ether, ethylene glycol monoether ether, methyl acetate, ethyl cellosolve acetate, diethylene glycol monoacetate, diethylene glycol monomethyl ether, diethylene glycol diethyl ether, diethylene glycol dimethyl ether, diethylene glycol ethyl methyl ether, diethylene glycol monoethyl ether, diethylene glycol monobutyl ether, ethyl 2-hydroxypropionate, methyl 2-hydroxy-2-methylpropionate, 2-hydroxyethyl-2-methylpropionate, ethyl acetate, methyl isoamyl ketone, 2-heptanone, ethylene glycol monoacetate, ethylene glycol monomethyl ether, ethylene glycol dimethyl ether, diethylene glycol ethyl methyl ether, Ethyl ethoxyacetate, ethyl glycolate, methyl 2-hydroxy-2-methylbutyrate, methyl 3-methoxypropionate, ethyl 3-methoxypropionate, methyl 3-ethoxypropionate, ethyl acetate, butyl acetate, methyl lactate and ethyl lactate, propylene glycol monoacetate, propylene glycol monoethyl ether acetate, propylene glycol monomethyl ether acetate, propylene glycol monopropyl ether methyl acetate, propylene glycol monobutyl ether acetate, propylene glycol monomethyl ether propionate, propylene glycol monoethyl ether propionate, propylene glycol ethyl ether acetate, ethylene glycol monomethyl ether acetate, ethylene glycol monoethyl ether acetate, propylene glycol monomethyl ether, propylene glycol monoethyl ether, propylene glycol monopropyl ether, propylene glycol monobutyl ether, ethylene glycol monomethyl ether, propylene glycol methyl ether, propylene glycol monoethyl ether, propylene glycol monopropyl ether, propylene glycol monobutyl ether, propylene glycol monomethyl ether, propylene glycol, Ethylene glycol monoethyl ether, methyl lactate, ethyl lactate, propyl lactate and butyl lactate, ethyl 3-ethoxypropionate, methyl 3-methoxypropionate, methyl 3-ethoxypropionate and ethyl 3-methoxypropionate, beta-propiolactone, beta-butyrolactone, gamma-butyrolactone, alpha-methyl-gamma-butyrolactone, beta-methyl-gamma-butyrolactone, gamma-valerolactone, gamma-caprolactone, gamma-octalactone, alpha-hydroxy-gamma-butyrolactone, 2-butanone, 3-methylbutanone, pinacolone, 2-pentanone, 3-pentanone, 4-methyl-2-pentanone, 2-methyl-3-pentanone, 4-dimethyl-2-pentanone, methyl lactate, ethyl lactate, propyl lactate and butyl lactate, ethyl 3-ethoxypropionate, methyl 3-methoxypropionate, methyl 3-ethoxypropionate and ethyl 3-methoxypropionate, gamma, 2, 4-dimethyl-3-pentanone, 2,4, 4-tetramethyl-3-pentanone, 2-hexanone, 3-hexanone, 5-methyl-3-hexanone, 2-heptanone, 3-heptanone, 4-heptanone, 2-methyl-3-heptanone, 5-methyl-3-heptanone, 2, 6-dimethyl-4-heptanone, 2-octanone, 3-octanone, 2-nonanone, 3-nonanone, 5-nonanone, 2-decanone, 3-decanone, 4-decanone, 5-hexen-2-one, 3-penten-2-one, cyclopentanone, 2-methylcyclopentanone, 3-methylcyclopentanone, 2-dimethylcyclopentanone, 2-hexanone, 3-hexanone, 5-methyl-3-heptanone, 2-hexanone, 2-methyl-pentanone, 2-methyl, 2,4, 4-trimethylcyclopentanone, cyclohexanone, 3-methylcyclohexanone, 4-ethylcyclohexanone, 2-dimethylcyclohexanone, 2, 6-dimethylcyclohexanone, 2, 6-trimethylcyclohexanone, cycloheptanone, 2-methylcycloheptanone, 3-methylcycloheptanone, methylene carbonate, vinylene carbonate, ethylene carbonate, butylene carbonate, 2-methoxyethyl acetate, 2-ethoxyethyl acetate, 2- (2-ethoxyethoxy) ethyl acetate, 3-methoxy-3-methylbutyl acetate, 1-methoxy-2-propyl acetate, dipropylene glycol, monomethyl ether monoethyl ether, monopropyl ether, monobutyl ether, Monoethyl ether, dipropylene glycol monoacetate, dioxane, methyl lactate, ethyl lactate, methyl acetate, ethyl acetate, butyl acetate, purified methyl propyl ester, ethyl pyruvate, propyl pyruvate, methyl methoxypropionate, ethyl ethoxypropionate, N-methylpyrrolidone (NMP), 2-methoxyethyl ether (diglyme), ethylene glycol monoethyl ether, propylene glycol monomethyl ether; ethyl lactate or methyl lactate, methyl pyruvate, ethyl pyruvate and ethoxypropionate, methyl ethyl ketone, cyclohexanone, 2-heptanone, carbon dioxide, cyclopentanone, cyclohexanone, ethyl 3-ethylpropionate, ethyl lactate, Propylene Glycol Methyl Ether Acetate (PGMEA), methylene cellosolve, butyl acetate, 2-ethoxyethanol, N-methylformamide, N-dimethylformamide, N-methylformamide, N-methylacetamide, N-dimethylacetamide, N-methylpyrrolidone, dimethyl sulfoxide, benzylethyl ether, dihexyl ether, acetonylacetone, isophorone, hexanoic acid, octanoic acid, 1-octanol, 1-nonanol, benzyl alcohol, benzyl acetate, ethyl benzoate, diethyl oxalate, diethyl maleate, gamma-butyrolactone, gamma-butanol, and mixtures thereof, Ethylene carbonate, propylene carbonate, phenyl cellosolve acetate, and the like.
However, as one of ordinary skill in the art will recognize, the above listed and described materials as examples of materials that may be used for the photoresist solvent component of the photoresist 517 are illustrative only and not intended to limit the embodiments. Rather, any suitable material that can dissolve the photoresist polymer resin and PAC can be utilized to aid in mixing and applying the photoresist 517. All such materials are fully intended to be included within the scope of the embodiments.
In addition, although each of the above materials may be used as a photoresist solvent for the photoresist 517, in an embodiment, more than one of the above materials may be used. For example, the photoresist solvent may comprise a combination mixture of two or more of the materials. All such combinations are fully intended to be included within the scope of the embodiments.
Optionally, a photoresist crosslinker may also be added to the photoresist 517. The photoresist crosslinker reacts with the photoresist polymer resin in photoresist 517 after exposure, contributing to an increase in the crosslink density of the photoresist, which contributes to an improvement in the photoresist pattern and dry etch resistance. In one embodiment, the photoresist crosslinking agent can be a melamine-based reagent, a urea-based reagent, an ethylene urea-based reagent, an propylene urea-based reagent, a glycoluril-based reagent, an aliphatic cyclic hydrocarbon having a hydroxyl group, a hydroxyalkyl group, or a combination of these, an oxygenated derivative of an aliphatic cyclic hydrocarbon, a glycoluril compound, an etherified amino resin, a combination of these, or the like.
Specific examples of materials that can be used as the photoresist crosslinker include melamine, acetoguanamine, benzoguanamine, urea, ethylene urea, or a combination of glycoluril with formaldehyde, glycoluril with formaldehyde and lower alcohols, hexamethoxymethylmelamine, dimethoxymethylurea, bismethoxymethylbisethyleneurea, tetramethoxymethylglycoluril and tetrabutoxymethylglycoluril, mono-, di-, tri-or tetrakis hydroxymethylated glycoluril, mono-, di-, tri-and/or tetrakis-methoxymethylated glycoluril, mono-, di-, tri-and/or tetrakis-ethoxymethylated glycoluril, mono-, di-, tri-and/or tetrakis-propoxymethylated glycoluril and mono-, di-, tri-and/or tetrabutoxymethylated glycoluril, 2, 3-dihydroxy-5-hydroxymethylnorbornane, 2-hydroxy-5, 6-bis (hydroxymethyl) norbornane, cyclohexanedimethanol, 3,4,8 (or 9) -trihydroxytricyclodecane, 2-methyl-2-adamantanol, 1, 4-dioxane-2, 3-diol and 1,3, 5-trihydroxycyclohexane, tetramethoxymethylglycoluril, methylpropyltetramethoxyoxiranylglycoluril and methylphenyltetramethoxymethylglycoluril, 2, 6-bis (hydroxymethyl) p-cresol, N-methoxymethyl-or N-butoxymethyl-melamine. In addition, a compound obtained by reacting formaldehyde, or formaldehyde and a lower alcohol with an amino group-containing compound (e.g., melamine, acetoguanamine, benzoguanamine, urea, ethyleneurea and glycoluril) and substituting the hydrogen atom of the amino group with a hydroxymethyl group or a lower alkoxymethyl group, for example, hexamethoxymethylmelamine, dimethoxymethylurea, dimethoxymethyldimethyleneurea, tetramethoxymethylglycoluril and tetrabutoxymethylglycoluril, a copolymer of 3-chloro-2-hydroxypropyl methacrylate and methacrylic acid, a copolymer of 3-chloro-2-hydroxypropyl methacrylate, cyclohexyl methacrylate and methacrylic acid, a copolymer of 3-chloro-2-hydroxypropyl methacrylate and benzyl methacrylate and methacrylic acid, bisphenol A-bis (3-chloro-2-hydroxypropyl) ether, bisphenol A-bis (2-hydroxypropyl) ether, poly (3-chloro-2-hydroxypropyl) ether of phenol novolac resins, pentaerythritol tetrakis (3-chloro-2-hydroxypropyl) ether, trimethylolmethane tris (3-chloro-2-hydroxypropyl) ether phenol, bisphenol a-bis (3-acetoxy-2-hydroxypropyl) ether, poly (3-acetoxy-2-hydroxypropyl) ether of phenol novolac resins, pentaerythritol tetrakis (3-acetoxy-2-hydroxypropyl) ether, pentaerythritol poly (3-chloroacetyloxy-2-hydroxypropyl) ether, trimethylolmethane tris (3-acetoxy-2-hydroxypropyl) ether, combinations thereof, and the like.
In addition to the photoresist polymer resin, PAC, free radical inhibitor, photoresist solvent, and photoresist crosslinker, photoresist 517 may also include many other additives that will help photoresist 517 achieve the highest resolution. For example, photoresist 517 may also include surfactants, quenchers, stabilizers, plasticizers, colorants, adhesion additives, surface leveling agents, combinations of these, and the like. Any suitable additive may be used.
In one embodiment, the photoresist polymer resin, PAC, free radical inhibitor, and any desired additives or other agents are added to the photoresist solvent for application. Once added, the mixture is then mixed to obtain a uniform composition throughout the photoresist 517 to ensure that there are no defects caused by uneven mixing or non-constant composition of the photoresist 517. Once mixed together, the photoresist 517 may be stored prior to use or may be used immediately.
Once ready, photoresist 517 may be utilized by first applying photoresist 517 onto second seed layer 515. The photoresist 517 may be applied to the second seed layer 515 such that the photoresist 517 coats an upper exposed surface of the second seed layer 515, and may be applied using a process of a spin coating process, a dip coating process, an air knife coating process, a curtain coating process, a wire bar coating process, a gravure coating process, a lamination process, an extrusion coating process, a combination of these, or the like. In one embodiment, the photoresist 517 may be applied such that it has a thickness between about 10nm and about 300nm, for example about 150nm, on the surface of the second seed layer 515.
Once the photoresist 517 is applied to the semiconductor substrate, a pre-bake of the photoresist 517 is performed to cure and dry the photoresist 517 prior to exposure to complete the application of the photoresist 517. Curing and drying the photoresist 517 removes the photoresist solvent components while leaving the photoresist polymer resin, PAC, free radical inhibitor, photoresist crosslinker, and other selected additives. In one embodiment, the pre-bake may be performed at a temperature suitable to evaporate the photoresist solvent, for example, between about 40 ℃ and 150 ℃, but the exact temperature depends on the material selected for the photoresist 517. The pre-bake is performed for a time sufficient to cure and dry the photoresist 517, for example, for about 10 seconds to about 5 minutes, for example, about 90 seconds.
Fig. 6A illustrates exposure of the photoresist 517 to form exposed regions 601 and unexposed regions 603 within the photoresist 517. In one embodiment, the exposure may be initiated by placing the semiconductor device 100 and the photoresist 517, which once cured and dried, enters the imaging device 600 for exposure. The imaging device 600 may include a support plate 605, an energy source 607, a patterned mask 609 between the support plate 605 and the energy source 607, and optics 617. In one embodiment, the support plate 605 is a surface on which the semiconductor device 100 and the photoresist 517 are placed or attached that provides support and control to the carrier substrate 101 during exposure of the photoresist 517. In addition, the support plate 605 may be moved along one or more axes and provide any desired heating or cooling to the carrier substrate 101 and the photoresist 517 to prevent temperature gradients from affecting the exposure process.
In one embodiment, the energy source 607 provides energy 611, such as light, to the photoresist 517 so as to initiate a reaction of the PAC, which in turn reacts with the polymer resin to chemically alter those portions of the photoresist 517 that the energy 611 impinges upon. In one embodiment, the energy 611 may be electromagnetic radiation, such as g-rays (wavelength about 436nm), i-rays (wavelength about 365nm), ultraviolet radiation, extreme ultraviolet radiation, X-rays, electron beams, and the like. The energy source 607 may be an electromagnetic radiation source and may be a KrF excimer laser (wavelength 248nm), an ArF excimer laser (wavelength 193nm), an F2 excimer laser (wavelength 157nm), or the like, although any other suitable energy source 611 may be used, such as a mercury vapor lamp, a xenon lamp, a carbon arc lamp, or the like.
The patterned mask 609 is positioned between the energy source 607 and the photoresist 517 so as to block portions of the energy 611 to form patterned energy 615 before the energy 611 actually impinges on the photoresist 517. In one embodiment, patterned mask 609 may include a series of layers (e.g., substrate, absorbing layer, anti-reflective coating, shielding layer, etc.) to reflect, absorb, or otherwise block portions of energy 611 from reaching those portions of photoresist 517 that are not intended to be illuminated. By forming openings through the patterned mask 609 in a desired illumination shape, a desired pattern can be formed in the patterned mask 609.
Optics (represented by the trapezoid labeled 617 in fig. 6A) may be used to focus, spread, reflect, or otherwise control the energy 611 as it exits the energy source 607, is patterned by the patterned mask 609, and directed toward the photoresist 517. In one embodiment, optics 617 includes one or more lenses, mirrors, filters, combinations of these, and the like, to control energy 611 along its path. Additionally, although the optics 617 are shown in fig. 6A between the patterned mask 609 and the photoresist 517, elements of the optics 617 (e.g., individual lenses, mirrors, etc.) can be located anywhere between the energy source 607 (generating energy 611) and the photoresist 517.
In one embodiment, a semiconductor device 100 having a photoresist 517 is placed on the support plate 605. Once the pattern has been aligned with the semiconductor device 100, the energy source 607 generates the required energy 611 (e.g. light), which 611 passes through the patterned mask 609 and optics 617 to the photoresist 517. The patterned energy 615 impinging on portions of the photoresist 517 causes a reaction of the PAC within the photoresist 517. The chemical reaction products (e.g., acid/base/radicals) of the PAC absorbing the patterned energy 615 then react with the polymer resin, chemically altering the photoresist 517 in those portions illuminated through the patterned mask 609.
FIG. 6B shows a close-up view of the box labeled 621 in FIG. 6A during the exposure process. It can be seen that during the exposure process, the desired energy 611 (e.g., light) is not directed downward, but rather is made up of a plurality of individual beams that first converge and then surround the center point CPDivergence. When the individual beams converge close enough to each other, and before the individual beams are separated far enough from each other, the individual beams will be focused with respect to each other and with respect to the photoresist 517. In one embodiment, the energy 611 is focused such that all of the various diverging beams of energy 611 converge and concentrate to a focal region 613 having a desired width. In a particular embodiment, the focus region 613 will have a first width W between about 5 μm and about 500 μm1For example about 40 μm. However, any suitable width may be used.
In addition, the focusing area 613 has a first width W1In the embodiment of (1), the focusing area 613 will also have the first height H centered on the center point Cp of the focusing area 6131. First height H1May be between about 1 μm and about 100 μm, for example about 40 μm. However, any suitable size may be used.
However, to help the subsequently formed third external connector 901 avoid cracking and reduce stress, the exposure process of the photoresist 517 is adjusted to help shape the final structure of the third external connector 901. For example, in one embodiment, focus is appliedCenter point C of region 613PIs not placed within the photoresist 517 itself. Instead, the center point C of the focusing area 613PA first distance D disposed below an uppermost surface of second seed layer 5151To (3). For example, in one embodiment, center point C of focus area 613 may be arrangedPSo that the first distance D1Between about 60 μm and about 70 μm, for example about 65 μm, below the uppermost surface of the second seed layer 515.
FIG. 6C shows another embodiment in which the focus area 613 is located off center in the photoresist 517. However, in this embodiment, the center point C is replacedPIs offset downwardly such that the center point CPBelow the bottom surface of the photoresist 517, the center point CP is shifted in the opposite direction so that the center point CP is located above the photoresist 517. In this embodiment, the center point CP may be offset by a second distance D2A second distance D2Between about 0 μm and about 60 μm, for example about 10 μm. However, any suitable size may be used.
FIG. 6D shows one resulting structure of photoresist 517 after exposure of photoresist 517, where the center point C of focus region 613PShifted under the photoresist 517. It can be seen that the center point CPAfter the shift, the bottom of the unexposed area 603 is not straight, but is angled with respect to the rest of the sidewalls of the unexposed area 603. In addition, the unexposed regions 603 are angled with respect to the second seed layer 515. This angled shape facilitates the formation of a third external connector 901 (not shown in fig. 6D, but further shown and described below with reference to fig. 9).
After exposure of the photoresist 517, a post-exposure bake may be used to aid in the generation, dispersion, and reaction of the acid/base/free radicals generated by the patterning energy 615 impinging on the PAC during exposure. This assistance helps to create or enhance a chemical reaction that creates a chemical difference between the exposed 601 and unexposed 603 regions within the photoresist 517. These chemical differences also cause solubility differences between exposed regions 601 and unexposed regions 603. In one embodiment, this post-exposure bake may be conducted at a temperature of about 40 ℃ to about 200 ℃ for a time of about 10 seconds to about 10 minutes. However, any suitable temperature and time may be used.
Fig. 7A-7B illustrate the development of the photoresist 517 using a developer 701 after exposure of the photoresist 517 (fig. 7B illustrates a close-up view of the dashed box labeled 621 in fig. 7A). After the photoresist 517 is exposed and the post-exposure bake has occurred, the photoresist 517 may be developed using a negative or positive developer, depending on the desired pattern of the photoresist 517. In embodiments where it is desired to remove the unexposed regions 603 of the photoresist 517 to form negative-tone, a negative-tone developer (e.g., an organic solvent or critical fluid) can be utilized to remove those portions of the photoresist 517 that are not exposed to the patterned energy 615, and thus retain their original solubility. Specific examples of materials that may be used include hydrocarbon solvents, alcohol solvents, ether solvents, ester solvents, critical fluids, combinations of these, and the like. Specific examples of materials that can be used for the negative solvent include hexane, heptane, 2-heptanone, N-butyl acetate, octane, toluene, xylene, methylene chloride, chloroform, carbon tetrachloride, trichloroethylene, methanol, ethanol, propanol, butanol, critical carbon dioxide, diethyl ether, dipropyl ether, dibutyl ether, ethyl vinyl ether, dioxane, propylene oxide, tetrahydrofuran, cellosolve, methyl cellosolve, butyl cellosolve, methyl carbitol, diethylene glycol monoethyl ether, acetone, methyl ethyl ketone, methyl isobutyl ketone, isophorone, cyclohexanone, methyl acetate, ethyl acetate, propyl acetate, butyl acetate, pyridine, formamide, N-dimethylformamide and the like.
If a positive-working developer is desired, a positive-working developer such as an aqueous alkaline solution may be used to remove those portions of the photoresist 517 that are exposed to the patterned energy 615 and have modified and altered their solubility by chemical reaction. Such aqueous alkaline solutions may include tetramethylammonium hydroxide (TMAH), tetrabutylammonium hydroxide, sodium hydroxide, potassium hydroxide, sodium carbonate, sodium bicarbonate, sodium silicate, sodium metasilicate, aqueous ammonia, monomethylamine, dimethylamine, trimethylamine, monoethylamine, diethylamine, triethylamine, monoisopropylamine, diisopropylamine, triisopropylamine, monobutylamine, dibutylamine, monoethanolamine, diethanolamine, triethanolamine, dimethylaminoethanol, diethylaminoethanol, ammonia, caustic soda, caustic potash, sodium metasilicate, potassium metasilicate, sodium carbonate, tetraethylammonium hydroxide, combinations thereof, and the like.
However, as one of ordinary skill in the art will recognize, the above description of positive-working and negative-working developers is intended to be illustrative only and is not intended to limit the embodiments to only the developers listed above. Rather, any suitable type of developer may be utilized, including acid developers or even water developers, which may be used to selectively remove a portion of photoresist 517 that has different properties (e.g., solubility) than another portion of photoresist 517. And all such developers are fully intended to be included within the scope of the embodiments.
Fig. 7A shows the application of developer 701 to photoresist 517 using, for example, a spin-on process. In this process, developer 701 is applied to the photoresist 517 from above the photoresist 517 while the semiconductor device 100 (and the photoresist 517) are rotated. In one embodiment, developer 701 may be supplied at a flow rate between about 10ml/min and about 2000ml/min, such as about 1000ml/min, while semiconductor device 100 is rotated at a speed between about 100rpm and about 3500rpm, such as about 1500 rpm. In one embodiment, the developer 701 may be at a temperature between about 10 ℃ to about 80 ℃, such as about 50 ℃, and development may last for about 1 minute to about 60 minutes, such as about 30 minutes.
However, while the spin coating method described herein is one suitable method for developing the photoresist 517 after exposure, it is intended to be illustrative and not to limit the embodiments. Rather, any suitable development method may be used, including immersion processes, bath processes, spray processes, combinations of these, and the like. All such development processes are fully intended to be included within the scope of the embodiments.
Fig. 7B shows a cross-section of a development process in which a negative developer is used. As shown, a developer 701 is applied to the photoresist 517 and dissolves the unexposed regions 603 of the photoresist 517. The dissolution and removal of the unexposed areas 603 of the photoresist 517 leaves openings in the photoresist 517, patterning the photoresist 517 in the shape of the patterned energy 615, thereby transferring the pattern of the patterned mask 609 to the photoresist 517.
Fig. 7B also shows that after the development process is complete and the developer 701 has been removed from the photoresist 517, the openings in the photoresist 517 will have an angled bottom to intercept the second seed layer 515. In one embodiment, the bottom portion may be at a first angle α between about 5 ° and about 85 °1For example about 45. However, any suitable angle may be used.
In addition, the bottom portion may be formed to have a second width W of between about 0.1 μm and about 10 μm2For example about 5 μm. The bottom portion can also have a second height H between about 0.1 μm and about 10 μm2For example about 5 μm. However, any suitable size may be used.
Fig. 8 shows a close-up view of the dashed box labeled 621 in fig. 7A during a post-development annealing process (represented by the wavy line labeled 801 in fig. 8) for assisting in reshaping openings through photoresist 517. In one embodiment, the annealing process 801 may be a thermal anneal in which the photoresist 517 is heated in an inert atmosphere, for example, in a furnace. The annealing process 801 may be performed at a temperature above the glass transition temperature (Tg), such as between about 100 ℃ and about 130 ℃, for example about 120 ℃, and may last for a period of time between about 120 seconds and about 7 minutes, for example about 5 minutes. However, any suitable process conditions may be used.
During the annealing process 801, the temperature will rise above the glass transition temperature of the photoresist 517, and the photoresist 517 will slightly melt and partially reshape itself, thereby also reshaping the openings through the photoresist 517. Thus, there is still an angled bottom portion after the annealing process 801, the annealing process 801 will at least partially reshape the bottom portion such that after the annealing process 801 the bottom portion may be at the second angle α2Or flare angle, second angle alpha2Different from the first angle alpha1Second angle alpha2For example between about 10 ° and about 85 °, for example about 45 °. Furthermore, after the annealing process 801, the bottom portion may be formed to have a thickness between about 0.5 μm and about 11 μmThird width W3E.g., about 5 μm, and a third height H between about 0.5 μm and about 11 μm3For example about 5 μm. However, any suitable size may be used.
Fig. 9 shows a close-up view of the dashed box labeled 621 in fig. 7A, where a third external connection 901 may be formed within the opening of the photoresist 517 once the photoresist 517 has been patterned and the annealing process 801 has been performed. In one embodiment, the third external connector 901 may be, for example, a copper pillar, and may include one or more conductive materials, such as copper, tungsten, other conductive metals, and the like, and may be formed, for example, by electroplating, electroless plating, and the like. In one embodiment, an electroplating process is used in which the second seed layer 515 and the photoresist 517 are immersed or immersed in an electroplating solution, for example, containing copper sulfate (CuSO)4) The solution of (1). The second seed layer 515 surface is electrically connected to the negative side of an external DC power source so that the second seed layer 515 functions as a cathode in the electroplating process. A solid conductive anode (e.g., a copper anode) is also immersed in the solution and attached to the positive side of the power supply. Atoms from the anode dissolve in the solution and the cathode (e.g., second seed layer 515) picks up the dissolved atoms from the solution, thereby plating the exposed conductive regions of the second seed layer 515 within the openings of the photoresist 517.
However, by using the exposure process and the reshaping process described herein, at least some of the negative effects of the plating process can be reduced or eliminated. In particular, by reshaping the openings through photoresist 517, the profile can help avoid plating solutions (e.g., CuSO)4Plating solution) penetrates into the photoresist and causes a risk of bottom-out during the plating process.
Once the third external connection 901 is formed using the photoresist 517 and the second seed layer 515, the photoresist 517 may be removed using a suitable removal process. In one embodiment, the photoresist 517 may be removed using a plasma ashing process, whereby the temperature of the photoresist 517 may be increased until the photoresist 517 undergoes thermal decomposition and may be removed. However, any other suitable method, such as wet stripping, may be used. Removing photoresist 517 may expose portions of underlying second seed layer 515.
By plating the third external connector 901 into the opening formed through the photoresist 517, the third external connector 901 will assume the shape of the opening through the photoresist 517. In this way, the third external connection 901 will also have an intermediate portion located outside the sixth passivation layer 513 and the second seed layer 515, wherein the intermediate portion is angled inwardly at an angle to the underlying seed layer. In one embodiment, the intermediate portion has a second angle α2A third width W3And a third height H3. However, any suitable size may be used.
Fig. 10 illustrates that once the second seed layer 515 is exposed, removal of the exposed portion of the second seed layer 515 may be performed. In one embodiment, exposed portions of the second seed layer 515 (e.g., those portions not covered by the third external connection 901) may be removed by, for example, a wet or dry etch process. For example, in the dry etching process, the reactant may be introduced to the second seed layer 515 using the third external connection 901 as a mask, thereby forming the second seed layer 515 to have a straight sidewall perpendicular to the surface of the sixth passivation layer 513. In another embodiment, an etchant may be sprayed or otherwise brought into contact with the second seed layer 515 to remove exposed portions of the second seed layer 515.
By forming the third external connection 901 as described above, the profile of the third external connection 901 may be modified to undercut the third external connection 901 and help reduce or eliminate cracks that may form between the third external connection 901 and the underlying passivation layer. In particular, the undercut of the third external connector 901 helps to reduce the compressive stress during reliability break-in testing. As the likelihood of crack generation decreases, smaller pitch sizes may be obtained while still passing the fracture test.
Fig. 11 shows that a fourth external connector 1101 is formed on the third external connector 901. In one embodiment, the fourth external connection 1101 may be a contact bump, such as a micro-bump or a controlled collapse chip connection (C4) bump, and may comprise a material such as tin or other suitable material, such as silver or copper. In embodiments where the fourth external connection 1101 is a contact bump, the fourth external connection 1101 may comprise a material such as tin, or other suitable material, such as silver, lead-free tin, or copper. In embodiments where the fourth external connection 1101 is a solder bump, the fourth external connection 1101 may be formed by first forming a layer of tin having a thickness of, for example, about 100 μm by conventional methods such as evaporation, plating, printing, solder transfer, ball placement, and the like. Once the tin layer is formed on the structure, reflow may be performed to shape the material into a desired bump shape, which may have a critical dimension between about 60 μm and about 100 μm, and may be formed in a circular or oval shape.
In addition, in one embodiment, the fourth external connection 1101 may be formed in a circular shape in a plan view. However, this is merely illustrative and is not intended to limit the embodiments. Rather, any suitable shape may be used, such as an oval or a combination of shapes.
Fig. 12 shows the debonding of the carrier substrate 101 from the first semiconductor device 201 and the second semiconductor device 301. In one embodiment, the fourth external connection 1101, and thus the structure comprising the first semiconductor device 201 and the second semiconductor device 301, may be attached to the ring structure 1201. The ring structure 1201 may be a metal ring for providing support and stability to the structure during and after the debonding process. In one embodiment, the fourth external connection 1101, the first semiconductor device 201, and the second semiconductor device 301 are attached to the ring structure using, for example, an ultraviolet tape 1203, although any other suitable adhesive or attachment may be used.
Once the fourth external connection 1101, and thus the structure comprising the first semiconductor device 201 and the second semiconductor device 301, is attached to the ring structure 1201, the carrier substrate 101 may be debonded from the structure comprising the first semiconductor device 201 and the second semiconductor device 301 using, for example, a thermal process to change the adhesive properties of the adhesive layer 103. In particular embodiments, the energy source (e.g., Ultraviolet (UV) laser, carbon dioxide (CO)2) Laser or Infrared (IR) laser) is used to irradiate and heat the adhesive layer 103 until the adhesive layer 103 loses at least some of its adhesive properties. Once implemented, the carrier linerThe base 101 and the adhesive layer 103 may be physically separated and removed from the structure including the fourth external connection 1101, the first semiconductor device 201, and the second semiconductor device 301.
Fig. 12 additionally shows the patterning of the polymer layer 105 to expose the vias 111 (and associated first seed layer 107). In one embodiment, polymer layer 105 may be patterned using, for example, a laser drilling process. In this method, a protective layer, such as a light-to-heat conversion (LTHC) layer or a hogomax layer (not separately shown in fig. 12), is first deposited on the polymer layer 105. Once protected, the laser is directed to those portions of polymer layer 105 that are desired to be removed to expose the underlying vias 111. In a laser drilling process, the drilling energy may be in the range of 0.1mJ to about 30mJ, and the drilling angle relative to the normal to polymer layer 105 is about 0 ° (perpendicular to polymer layer 105) to about 85 °. In one embodiment, patterning may be performed to form a fourth opening 1205 over via 111 to have a width between about 100 μm and about 300, for example about 200 μm.
In another embodiment, the polymer layer 105 may be patterned by first applying a photoresist (not separately shown in fig. 12) to the polymer layer 105 and then exposing the photoresist to a patterned energy source (e.g., a patterned light source) to induce a chemical reaction that causes a physical change in those portions of the photoresist that are exposed to the patterned light source. A developer is then applied to the exposed photoresist to selectively remove either the exposed portions of the photoresist or the unexposed portions of the photoresist using physical changes and according to a desired pattern, and the exposed portions of the underlying polymer layer 105 are removed using, for example, a dry etching process. However, any other suitable method for patterning the polymer layer 105 may be used.
Fig. 13 shows the placement of a backside ball pad 1301 within the opening of the polymer layer 105 to protect the now exposed via 111. In one embodiment, the backside ball pad 1301 may comprise a conductive material, such as solder on solder paste or oxygen solder mask (OSP), although any suitable material may be used. In one embodiment, the backside ball pads 1301 may be applied using a stencil, but any suitable application method may be used, followed by reflow to form the bump shapes.
Fig. 13 also shows the placement and patterning of the backside protection layer 1303 on the backside ball pads 1301, effectively sealing the bond between the backside ball pads 1301 and the vias 111 to prevent moisture ingress. In one embodiment, the backside protection layer 1303 may be a protective material such as PBO, Solder Resist (SR), Laminate Compound (LC) tape, ajinomoto laminate film (ABF), non-conductive paste (NCP), non-conductive film (NCF), Patterned Underfill (PUF), warpage-improving adhesive (WIA), liquid molding compound V9, combinations of these, and the like. However, any suitable material may be used. The backside protection layer 1303 may be applied to a thickness between about 1 μm and about 200 μm using a process such as screen printing, lamination, spin coating, etc.
Fig. 13 also shows that once the back side protective layer 1303 is placed, the back side protective layer 1303 may be patterned to expose the back side ball pads 1301. In one embodiment, the back side protective layer 1303 may be patterned using, for example, a laser drilling method by which laser light is directed to those portions of the back side protective layer 1303 that are desired to be removed in order to expose the back side ball pads 1301. In the laser drilling process, the drilling energy may range from 0.1mJ to about 30mJ, and the drilling angle with respect to the normal of the back surface protective layer 1303 is about 0 degrees (perpendicular to the back surface protective layer 1303) to about 85 degrees. In one embodiment, the exposure may form openings having a diameter between about 30 μm and about 300 μm, for example about 150 μm.
In another embodiment, the back side protective layer 1303 may be patterned by first applying a photoresist (not separately shown in fig. 13) to the back side protective layer 1303 and then exposing the photoresist to a patterned energy source (e.g., a patterned light source) to induce a chemical reaction, thereby causing a physical change in those portions of the photoresist exposed to the patterned light source. A developer is then applied to the exposed photoresist to selectively remove either the exposed portions of the photoresist or the unexposed portions of the photoresist according to a desired pattern using physical changes, and the exposed portions of the underlying backside protection layer 1303 are removed using, for example, a dry etching process. However, any other suitable method for patterning the back side protective layer 1303 may be used.
Fig. 13 also shows the bonding of the backside ball pad 1301 to the first package 1300. In one embodiment, first package 1300 may include a third substrate 1305, a third semiconductor device 1307, a fourth semiconductor device 1309 (bonded to third semiconductor device 1307), third contact pads 1311, a second encapsulant 1313, and fifth external connections 1315. In one embodiment, third substrate 1305 may be, for example, a package substrate including internal interconnects (e.g., substrate vias 1317) to connect third semiconductor device 1307 and fourth semiconductor device 1309 to backside ball pads 1301.
In another embodiment, the third substrate 1305 may be an interposer used as an intermediate substrate to connect the third semiconductor device 1307 and the fourth semiconductor device 1309 to the backside ball pad 1301. In this embodiment, the third substrate 1305 may be an active layer such as a doped or undoped silicon substrate or a silicon-on-insulator (SOI) substrate. However, the third substrate 1305 may also be a glass substrate, a ceramic substrate, a polymer substrate, or any other substrate that may provide suitable protection and/or interconnect functionality. These and any other suitable materials may be used for the third substrate 1305.
The third semiconductor device 1307 may be a semiconductor device designed for the intended purpose, such as a logic die, a Central Processing Unit (CPU) die, a memory die (e.g., a DRAM die), a combination of these, or the like. In one embodiment, the third semiconductor device 1307 comprises an integrated circuit device required for a particular function, such as a transistor, capacitor, inductor, resistor, metallization layer (not shown), and the like. In one embodiment, the third semiconductor device 1307 is designed and fabricated to work in conjunction with or at the same time as the first semiconductor device 201.
The fourth semiconductor device 1309 may be similar to the third semiconductor device 1307. For example, the fourth semiconductor device 1309 may be a semiconductor device (e.g., a DRAM die) designed for the intended purpose and include an integrated circuit device for the desired function. In one embodiment, the fourth semiconductor device 1309 is designed to operate in conjunction with or simultaneously with the first semiconductor device 201 and/or the third semiconductor device 1307.
The fourth semiconductor device 1309 may be bonded to the third semiconductor device 1307. In one embodiment, the fourth semiconductor device 1309 is physically bonded to only the third semiconductor device 1307, for example by using an adhesive. In this embodiment, the fourth semiconductor device 1309 and the third semiconductor device 1307 may be electrically connected to the third substrate 1305 using, for example, wire bonds 1319, but any suitable electrical bond may be used.
In another embodiment, the fourth semiconductor device 1309 can be physically and electrically bonded to the third semiconductor device 1307. In this embodiment, the fourth semiconductor device 1309 may comprise an external connection (not separately shown in fig. 13) which is connected to an external connection (also not separately shown in fig. 13) on the third semiconductor device 1307 in order to interconnect the fourth semiconductor device 1309 with the third semiconductor device 1307.
Third contact pads 1311 may be formed on the third substrate 1305 to form an electrical connection between the third semiconductor device 1307 and, for example, a fifth external connection 1315. In one embodiment, third contact pads 1311 may be formed on electrical wiring (such as substrate vias 1317) within third substrate 1305 and in electrical contact with electrical wiring within third substrate 1305. The third contact pad 1311 may comprise aluminum, but other materials, such as copper, may be used. Third contact pad 1311 may be formed using a deposition process such as sputtering to form a material layer (not shown), and then portions of the material layer may be removed by a suitable process such as photolithography masking and etching to form third contact pad 1311. However, any other suitable process may be utilized to form third contact pad 1311. The third contact pad 1311 may be formed to have a thickness of between about 0.5 μm and about 4 μm, for example, about 1.45 μm.
The second sealant 1313 can be used for sealing and protecting the third semiconductor device 1307, the fourth semiconductor device 1309, and the third substrate 1305. In one embodiment, the second encapsulant 1313 may be a molding compound and may be placed using a molding device (not shown in fig. 13). For example, the third substrate 1305, the third semiconductor device 1307, and the fourth semiconductor device 1309 can be placed within a cavity of a molding apparatus, and the cavity can be hermetically sealed. The second sealant 1313 may be placed in the cavity before the cavity is hermetically sealed, or may be injected into the cavity through an injection port. In one embodiment, the second encapsulant 1313 may be a molding compound resin, such as polyimide, PPS, PEEK, PES, heat resistant crystalline resin, combinations of these, and the like.
Once second encapsulant 1313 is placed in the cavity such that second encapsulant 1313 seals the areas around third substrate 1305, third semiconductor device 1307, and fourth semiconductor device 1309, second encapsulant 1313 may be cured to harden second encapsulant 1313 for optimal protection. While the exact curing process depends at least in part on the particular material selected for the second encapsulant 1313, in embodiments where a molding compound is selected as the second encapsulant 1313, curing may occur by a process such as heating the second encapsulant 1313 to between about 100 ℃ to about 130 ℃, e.g., about 125 ℃, for a time period of about 60 seconds to about 3000 seconds, e.g., about 600 seconds. Additionally, an initiator and/or catalyst may be included in the second encapsulant 1313 to better control the curing process.
However, as one of ordinary skill in the art will appreciate, the above-described curing process is merely an exemplary process and is not meant to limit the present embodiments. Other curing processes may be used, such as radiation or even allowing the second encapsulant 1313 to harden at ambient temperatures. Any suitable curing process may be used, and all such processes are fully intended to be included within the scope of the embodiments discussed herein.
In one embodiment, fifth external connections 1315 may be formed to provide external connections between third substrate 1305 and, for example, backside ball pads 1301. The fifth external connections 1315 may be contact bumps, such as micro-bumps or controlled collapse chip connection (C4) bumps, and may comprise a material such as tin, or other suitable material, such as silver or copper. In embodiments where the fifth external connections 1315 are solder bumps, the fifth external connections 1315 may be formed by initially forming a layer of tin by any suitable method (e.g., evaporation, plating, printing, solder transfer, solder ball placement, etc.) to a thickness of, for example, about 100 μm. Once the tin layer is formed on the structure, reflow is performed to shape the material into the desired bump shape.
Once the fifth external connection 1315 is formed, the fifth external connection 1315 is aligned with and in physical contact with the backside ball pad 1301 and bonding is performed. For example, in embodiments where the fifth external connections 1315 are solder bumps, the bonding process may include a reflow process, whereby the temperature of the fifth external connections 1315 is raised to a point where the fifth external connections 1315 will liquefy and flow, thus bonding the first package 1300 to the backside ball pad 1301 once the fifth external connections 1315 re-solidify.
Fig. 13 additionally shows the bonding of a second package 1321 to the backside ball pad 1301. In one embodiment, the second package 1321 may be similar to the first package 1300 and may be bonded to the backside ball pad 1301 using a similar process. However, the second package 1321 may also be different from the first package 1300.
Fig. 14 shows the debonding of the fourth external connection 1101 from the ring structure 1201 and the singulation of the structure to form a first integrated fan-out stack-up package (InFO-POP) structure 1400. In one embodiment, the fourth external connector 1101 may be debonded from the ring structure 1201 by first bonding the first and second encapsulants 1300, 1321 to the second ring structure using, for example, a second ultraviolet tape. Once joined, the ultraviolet tape 1203 may be irradiated with ultraviolet radiation, and once the ultraviolet tape 1203 loses its adhesiveness, the fourth external connection member 1101 may be physically separated from the ring structure 1201.
Once de-bonded, singulation of the structure is performed to form the first InFO-POP structure 1400. In one embodiment, singulation may be performed by cutting through the polymer layer 105 between the encapsulant 401 and the vias 111 using a saw blade (not shown) to separate one section from another to form the first InFO-POP structure 1400. However, as one of ordinary skill in the art will recognize, the use of a saw blade to singulate the first InFO-POP structure 1400 is merely an illustrative embodiment and is not limiting. Other methods for singulating the first InFO-POP structure 1400 may also be used, such as using one or more etches to singulate the first InFO-POP structure 1400. These methods and any other suitable method may be utilized to segment the first InFO-POP structure 1400.
According to one embodiment, a method of manufacturing a semiconductor device includes: applying a photoresist on the seed layer; exposing the photoresist to a patterned energy source, the patterned energy source having a focus region with a center point located below a surface of the photoresist facing the seed layer; developing the photoresist to form an opening; and plating an external connection into the opening. In one embodiment, the method further comprises annealing the photoresist after developing the photoresist, wherein annealing the photoresist reshapes the openings. In one embodiment, the annealing of the photoresist raises the temperature of the photoresist to between about 110 ℃ and about 130 ℃. In one embodiment, the center point is located a distance between about 60 μm and about 70 μm below the surface of the photoresist. In one embodiment, the method further comprises removing portions of the seed layer not covered by the external connections. In one embodiment, developing the photoresist includes removing unexposed portions of the photoresist. In one embodiment, a seed layer is over the encapsulant and the encapsulant vias around the semiconductor device.
According to another embodiment, a method of manufacturing a semiconductor device includes: exposing a photoresist to a patterned energy source, the photoresist being on the encapsulant between the semiconductor die and the encapsulant via; developing the photoresist to form an opening having a first shape; performing a post-development bake process to reshape the opening to a second shape different from the first shape, wherein the second shape includes a flare near a bottom of the opening; and plating a conductive material into the opening. In one embodiment, exposing the photoresist focuses a patterned energy source to form a focus region having a center point located below the photoresist. In one embodiment, the center point is located a distance between about 60 μm and about 70 μm below the photoresist. In one embodiment, the post-development bake process raises the temperature of the photoresist to a temperature between about 100 ℃ and about 130 ℃. In one embodiment, the flare extends a first distance in a first direction parallel to the major surface of the encapsulant, the first distance being between about 0.1 μm and about 10 μm. In one embodiment, the flare extends a second distance in a second direction perpendicular to the major surface of the encapsulant, the second distance being between about 0.5 μm and about 10 μm. In one embodiment, the flare is at an opening angle between about 10 ° and about 85 °.
According to still another embodiment, a semiconductor device includes: a semiconductor die; an encapsulant encapsulating the semiconductor die; a sealant through hole extending from a first side of the sealant to a second side of the sealant; a passivation layer over the sealant; an external connection over the sealant, the external connection comprising: a first portion having a first width, the first portion extending through the passivation layer; and a second portion having a second width greater than the first width, the second portion being located outside the passivation layer; a tapered portion extending from the second portion to the first portion. In one embodiment, the tapered portion is at a taper angle to a line parallel to the major surface of the encapsulant, the taper angle being between about 10 ° and about 85 °. In one embodiment, the semiconductor device further includes a solder ball in physical contact with the external connection, the solder ball having an elliptical shape. In one embodiment, the semiconductor device further includes a solder ball in physical contact with the external connection, the solder ball having a circular shape. In one embodiment, the semiconductor device further includes a seed layer between the external connection and the passivation layer, the seed layer having straight sidewalls perpendicular to a surface of the passivation layer. In one embodiment, the semiconductor device further includes a redistribution layer between the external connection and the encapsulant.
The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the present invention. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims (10)

1. A method of manufacturing a semiconductor device, the method comprising:
applying a photoresist on the seed layer;
exposing the photoresist to a patterned energy source having an in-focus region with a center point located below a surface of the photoresist facing the seed layer;
developing the photoresist to form an opening; and
plating an external connection into the opening.
2. The method of claim 1, further comprising annealing the photoresist after developing the photoresist, wherein annealing the photoresist reshapes the opening.
3. The method of claim 2, wherein the annealing of the photoresist raises the temperature of the photoresist to between 110 ℃ and 130 ℃.
4. The method of claim 1, wherein the center point is located below the surface of the photoresist a distance between 60 μ ι η and 70 μ ι η.
5. The method of claim 1, further comprising removing portions of the seed layer not covered by the external connections.
6. The method of claim 1, wherein developing the photoresist comprises removing unexposed portions of the photoresist.
7. The method of claim 1, wherein the seed layer is over the encapsulant and encapsulant via around the semiconductor device.
8. A method of manufacturing a semiconductor device, the method comprising:
exposing a photoresist to a patterned energy source, the photoresist being on the encapsulant between the semiconductor die and the encapsulant via;
developing the photoresist to form an opening having a first shape;
performing a post-development bake process to reshape the opening into a second shape different from the first shape, wherein the second shape comprises a flare near a bottom of the opening; and
plating a conductive material into the opening.
9. The method of claim 8, wherein exposing the photoresist focuses the patterned energy source to form a focus region having a center point located below the photoresist.
10. A semiconductor device, comprising:
a semiconductor die;
an encapsulant encapsulating the semiconductor die;
an encapsulant through-hole extending from a first side of the encapsulant to a second side of the encapsulant;
a passivation layer over the encapsulant; and
an external connection over the sealant, the external connection comprising:
a first portion having a first width, the first portion extending through the passivation layer;
a second portion having a second width greater than the first width, the second portion being located outside the passivation layer; and
a tapered portion extending from the second portion to the first portion.
CN201910043381.4A 2018-06-29 2019-01-17 Semiconductor device and method for manufacturing the same Active CN110660650B (en)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US201862691878P 2018-06-29 2018-06-29
US62/691,878 2018-06-29
US16/148,649 2018-10-01
US16/148,649 US10861710B2 (en) 2018-06-29 2018-10-01 Methods of manufacturing semiconductor devices

Publications (2)

Publication Number Publication Date
CN110660650A true CN110660650A (en) 2020-01-07
CN110660650B CN110660650B (en) 2022-09-13

Family

ID=66995631

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910043381.4A Active CN110660650B (en) 2018-06-29 2019-01-17 Semiconductor device and method for manufacturing the same

Country Status (5)

Country Link
US (2) US10861710B2 (en)
KR (1) KR102288340B1 (en)
CN (1) CN110660650B (en)
DE (1) DE102018125161B3 (en)
TW (1) TWI709181B (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112420685A (en) * 2020-11-09 2021-02-26 东莞阿尔泰显示技术有限公司 Manufacturing method of LED display module
WO2024045154A1 (en) * 2022-09-02 2024-03-07 SK Hynix NAND Product Solutions Corp. (dba Solidigm) Systems and methods for reducing stress and improving surface adhesion in a die

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11676855B2 (en) 2020-02-26 2023-06-13 Taiwan Semiconductor Manufacturing Co., Ltd. Patterning interconnects and other structures by photo-sensitizing method
US11127632B1 (en) * 2020-03-19 2021-09-21 Nanya Technology Corporation Semiconductor device with conductive protrusions and method for fabricating the same
TWI772001B (en) * 2020-04-30 2022-07-21 台灣積體電路製造股份有限公司 Resin, photoresist composition, and method of manufacturing semiconductor device

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004046003A (en) * 2002-07-15 2004-02-12 Seiko Epson Corp Fine structure, manufacturing method of fine structure and manufacturing device thereof
CN101167161A (en) * 2005-11-04 2008-04-23 韩国科学技术院 Polymer or resist pattern, and metal film pattern, metal pattern and plastic mold using the same, and fabrication methods thereof
CN101458457A (en) * 2007-12-13 2009-06-17 中芯国际集成电路制造(上海)有限公司 Method for obtaining focusing position of exposure apparatus and focusing detecting method
JP2011118344A (en) * 2009-11-02 2011-06-16 Mejiro Precision:Kk Method for forming three-dimensional pattern
US8198015B2 (en) * 2008-03-26 2012-06-12 Lapis Semiconductor Co., Ltd. Method of forming mask pattern
CN104882373A (en) * 2015-04-24 2015-09-02 石以瑄 Method for manufacturing transistor T-shaped gate
CN107203099A (en) * 2016-03-18 2017-09-26 台湾积体电路制造股份有限公司 Semiconductor devices and its manufacture method

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10128206B2 (en) 2010-10-14 2018-11-13 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive pillar structure
US9117881B2 (en) * 2013-03-15 2015-08-25 Taiwan Semiconductor Manufacturing Company, Ltd. Conductive line system and process
US9318429B2 (en) * 2014-03-31 2016-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Integrated structure in wafer level package
US9842826B2 (en) 2015-07-15 2017-12-12 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of manufacture
US10658199B2 (en) 2016-08-23 2020-05-19 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method
WO2018063324A1 (en) * 2016-09-30 2018-04-05 Intel Corporation Chip assemblies employing solder bonds to back-side lands including an electrolytic nickel layer
JP7013872B2 (en) 2016-10-05 2022-02-15 東レ株式会社 Resin compositions, cured films, semiconductor devices and methods for manufacturing them
US11062915B2 (en) * 2018-03-29 2021-07-13 Taiwan Semiconductor Manufacturing Company, Ltd. Redistribution structures for semiconductor packages and methods of forming the same

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004046003A (en) * 2002-07-15 2004-02-12 Seiko Epson Corp Fine structure, manufacturing method of fine structure and manufacturing device thereof
CN101167161A (en) * 2005-11-04 2008-04-23 韩国科学技术院 Polymer or resist pattern, and metal film pattern, metal pattern and plastic mold using the same, and fabrication methods thereof
CN101458457A (en) * 2007-12-13 2009-06-17 中芯国际集成电路制造(上海)有限公司 Method for obtaining focusing position of exposure apparatus and focusing detecting method
US8198015B2 (en) * 2008-03-26 2012-06-12 Lapis Semiconductor Co., Ltd. Method of forming mask pattern
JP2011118344A (en) * 2009-11-02 2011-06-16 Mejiro Precision:Kk Method for forming three-dimensional pattern
CN104882373A (en) * 2015-04-24 2015-09-02 石以瑄 Method for manufacturing transistor T-shaped gate
CN107203099A (en) * 2016-03-18 2017-09-26 台湾积体电路制造股份有限公司 Semiconductor devices and its manufacture method

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
伊福廷等: "微细加工新技术―LIGA技术", 《微细加工技术》 *

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112420685A (en) * 2020-11-09 2021-02-26 东莞阿尔泰显示技术有限公司 Manufacturing method of LED display module
WO2024045154A1 (en) * 2022-09-02 2024-03-07 SK Hynix NAND Product Solutions Corp. (dba Solidigm) Systems and methods for reducing stress and improving surface adhesion in a die

Also Published As

Publication number Publication date
TWI709181B (en) 2020-11-01
US20200006086A1 (en) 2020-01-02
US10861710B2 (en) 2020-12-08
US20210118697A1 (en) 2021-04-22
KR20200002580A (en) 2020-01-08
KR102288340B1 (en) 2021-08-11
CN110660650B (en) 2022-09-13
DE102018125161B3 (en) 2019-07-11
TW202002106A (en) 2020-01-01

Similar Documents

Publication Publication Date Title
TWI708331B (en) Semiconductor device and method
CN107203099B (en) Semiconductor device and method for manufacturing the same
CN110660650B (en) Semiconductor device and method for manufacturing the same
US11842896B2 (en) Semiconductor devices and methods of manufacturing
TWI780358B (en) Methof of manufacturing semiconductor device and photoresist
TWI720151B (en) Method of manufacturing semiconductor device
US20230307251A1 (en) Semiconductor Device
TWI790664B (en) Semiconductor devices and methods of manufacture
TWI836316B (en) Method of manufacturing semiconductor device and photoresist
US20230064162A1 (en) Semiconductor Device and Methods of Manufacture

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant