CN110660438B - Flash memory device and programming method thereof - Google Patents
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Abstract
The invention provides a flash memory device and a programming method thereof. Programming of flash memory includes: setting an initial programming voltage, and performing a first programming action on a plurality of flash memory cells according to the initial programming voltage; after the first programming action, detecting the threshold voltage of the flash memory cell and obtaining the highest threshold voltage; setting a target threshold voltage, and generating a second programming voltage according to the target threshold voltage, the initial programming voltage and the highest threshold voltage; performing a second programming operation on the flash memory cell according to the second programming voltage; after the second programming action, the flash memory cell is verified by the same or different verification voltages, and based on the second programming voltage, the flash memory cell is subjected to an increasing action according to the programming step value to generate at least one third programming voltage; performing at least one third programming operation on the flash memory cell according to at least one third programming voltage; and passing the flash memory cell through a verify voltage according to the final programming voltage.
Description
Technical Field
The invention relates to a flash memory device and a programming method thereof.
Background
With the popularization of electronic products, it is becoming one of the important specifications of electronic products to provide high-quality data storage media in response to the large amount of information demands of users. In the field of technology today, flash memory devices capable of providing data writing and reading capabilities have become the requisite data storage media for electronic products.
When programming a flash memory, it is difficult to set a first programming voltage, and when the first programming voltage is too large, a poor threshold voltage distribution of the memory cell is easily generated, and when the first programming voltage is too small, a long programming time is generated. In addition, because the memory cells are distributed over multiple locations in the integrated circuit, the results of the programming operation are easily correlated with the locations where the memory cells are located, and the threshold voltage distribution of the memory cells cannot be programmed better. In addition, the programming result is easily related to the erasing and programming times of the memory cells based on the characteristic variation of the memory cells after multiple erasing and programming.
Disclosure of Invention
The invention provides a flash memory device and a programming method thereof, which can control the distribution state of the critical voltage of a programmed memory cell and optimize the programming time of the flash memory cell.
The invention provides a programming method of a flash memory, which comprises the following steps: setting an initial programming voltage, and performing a first programming action on a plurality of flash memory cells according to the initial programming voltage; after the first programming action, detecting the threshold voltage of the flash memory cell and obtaining the highest threshold voltage; setting a target threshold voltage, and generating a second programming voltage according to the target threshold voltage, the initial programming voltage and the highest threshold voltage; performing a second programming operation on the flash memory cell according to the second programming voltage; after the second programming action, based on the second programming voltage, carrying out increment action according to the programming step value to generate at least one third programming voltage; and performing at least one third programming operation on the flash memory cell according to at least one third programming voltage.
The invention provides a flash memory device, which comprises a flash memory and a controller. The flash memory has a plurality of flash memory cells. The controller is coupled to the flash memory and is used for: setting an initial programming voltage, and performing a first programming action on a plurality of flash memory cells according to the initial programming voltage; after the first programming action, detecting the threshold voltage of the flash memory cell and obtaining the highest threshold voltage; setting a target threshold voltage, and generating a second programming voltage according to the target threshold voltage, the initial programming voltage and the highest threshold voltage; performing a second programming operation on the flash memory cell according to the second programming voltage; after the second programming action, based on the second programming voltage, carrying out increment action according to the programming step value to generate at least one third programming voltage; and performing at least one third programming operation on the flash memory cell according to at least one third programming voltage.
Based on the above, the flash memory device provided by the present invention controls the distribution range of the threshold voltage of the programmed flash memory cells through multiple programming operations for the flash memory cells. Thus, a lower initial programming voltage can be set and the flash memory cells can be programmed by gradually adjusting the initial programming voltage, thereby optimizing the threshold voltage distribution of the programmed memory cells.
In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
Fig. 1 illustrates a flowchart of a programming method of a flash memory according to an exemplary embodiment of the present invention.
Fig. 2A to 2C are schematic diagrams illustrating threshold voltage distribution states of respective programming actions of a flash memory according to an exemplary embodiment of the present invention.
Fig. 3 illustrates a flowchart of a programming method of a flash memory according to another exemplary embodiment of the present invention.
Fig. 4 illustrates a flowchart of a programming method of a flash memory according to another exemplary embodiment of the present invention.
FIG. 5 illustrates a block diagram of a flash memory storage device according to an exemplary embodiment of the invention.
[ notation ] to show
Z0-Z3: programmed state
RV 0: initial read voltage
Vstep: reading step values
RV 1: read voltage
RV: maximum critical voltage
PV: first verification voltage
PV 1: second verification voltage
VTh: target critical voltage
OT: offset voltage value
V0: initial programming voltage
V1: second time programming voltage
V: third time post program voltage
Vstep 1: programming step value
S101 to S111, S301 to S331, S401 to S429: step of programming
500: flash memory device
510: flash memory
520: controller
Detailed Description
Fig. 1 illustrates a flowchart of a programming method of a flash memory according to an exemplary embodiment of the present invention. Referring to fig. 1, step S101 sets an initial programming voltage, and performs a first programming operation on a plurality of flash memory cells in the flash memory according to the initial programming voltage. Referring to fig. 1 and fig. 2A, fig. 2A illustrates a threshold voltage distribution status diagram of each programming step of the flash memory according to an exemplary embodiment of the invention. Specifically, before the first programming operation is not performed, the threshold voltage distribution of the flash memory cells is in the erased state Z0, and through the process of step S101, the threshold voltage distribution of the flash memory cells may be changed to the programmed state Z1 (i.e., the threshold voltages of the programmed flash memory cells are all smaller than the target threshold voltage).
It should be noted that the initial programming voltage is set in a manner correlated to the process parameters of the memory, and an engineer can set a relatively low initial programming voltage according to the process parameters of the memory to perform a programming operation on the flash memory cell in an erased state.
Next, step S103 detects the threshold voltages of the flash memory cells after the first programming operation and obtains the highest threshold voltage of the threshold voltages in the flash memory cells. Specifically, since the threshold voltage of the flash memory cell may be distributed in the programmed state Z1 after the first programming operation, the highest threshold voltage RV of the flash memory cell can be obtained through the process of step S103. Specifically, the index value n may be initialized, and the initial read voltage RV0 and the read step value Vstep are set, and the read voltage RV1 is set equal to RV0+ Vstep × n. Therefore, the verification operation of reading the flash memory cell is performed according to the reading voltage RV1 to determine whether the threshold voltages of the flash memory cell are all less than the reading voltage RV 1. If all the flash memory cells are verified to have threshold voltages smaller than the read voltage RV1, the read voltage RV1 is set to the maximum threshold voltage RV. If the threshold voltages of all the flash memory cells are not all smaller than the read voltage RV1, the index value N is incremented by 1, and the read verification is performed again under the condition that the index value N is not greater than the threshold value N. Step S105 sets a target threshold voltage, and generates a second programming voltage according to the target threshold voltage, the initial programming voltage and the highest threshold voltage, wherein the target threshold voltage is a maximum value of the predetermined threshold voltages. Specifically, a target threshold voltage VTh may be preset and a second programming voltage V1 may be calculated to be equal to V0+ (VTh-RV) + Voffset. Where V0 is the initial programming voltage set in step S101, and voffset is the preset offset voltage value.
It should be noted that the preset offset voltage voffset may be set by an engineer according to requirements and actual states of the flash memory, wherein the preset offset voltage voffset may be greater than, less than or equal to 0 v.
Then, step S107 performs a second programming operation on the flash memory cell according to the second programming voltage V1 obtained in step S105. Please refer to fig. 1 and fig. 2B simultaneously, wherein fig. 2B illustrates a threshold voltage distribution state diagram of each programming operation of the flash memory according to an exemplary embodiment of the invention. Specifically, the threshold voltage distribution of the flash memory cells is in the programmed state Z1 before the second programming operation is not performed, and the threshold voltage distribution of the flash memory cells is changed to the programmed state Z2 by performing the step S107 (i.e., the threshold voltages of the flash memory cells are not all greater than the second verification voltage PV 1). Step S109 increments the second programming voltage according to the programming step value after the second programming operation and generates at least one third programming voltage. Specifically, the program step value Vstep1 can be preset to calculate that the third program voltage V2 is equal to V1+ m Vstep 1. Where V1 is the second programming voltage and m is the number of times of programming. Finally, step S111 performs one or more third programming operations on the flash memory cell according to at least one third programming voltage V2. Please refer to fig. 2C simultaneously, wherein fig. 2C illustrates a threshold voltage distribution status diagram of each programming action of the flash memory according to an exemplary embodiment of the present invention. Specifically, the threshold voltage distribution of the flash memory cells can be controlled to be in the programmed state Z3 by performing steps S318-S331 or steps S416-S429, wherein the state Z3 is controlled between the first verification voltage PV and the target threshold voltage VTh, and the first verification voltage PV and the second verification voltage PV1 have an offset voltage OT therebetween. Steps S318 to S331 and steps S416 to S429 are further described in the following embodiments.
By the steps, the invention can program the flash memory by gradually adjusting the programming voltage to control the threshold voltage of the flash memory within a preset range (i.e. between the first verification voltage PV and the target threshold voltage VTh), thereby optimizing the threshold voltage distribution of the flash memory.
Fig. 3 illustrates a flowchart of a programming method of a flash memory according to another exemplary embodiment of the present invention. Referring to fig. 3, step S301 initializes an index value n equal to 0. In step S303, an initial programming voltage V0 is set, and the flash memory cell is programmed according to the initial programming voltage V0. Step S305 performs a corresponding verifying operation on the flash memory cell according to the first verifying voltage PV, and verifies whether the programming operation of the flash memory cell is completed. When all flash memory cells can pass verification, the programming action is complete. On the contrary, when not all of the flash memory cells can pass the verification (fail), step S307 is executed (i.e., the threshold voltages of the flash memory cells are not all greater than the first verification voltage PV).
Step S307 sets the initial read voltage RV0 and the read step value Vstep, and sets the read voltage RV1 equal to RV0+ Vstep × n. Step S309 performs a read verification operation on the flash memory cells according to the read voltage RV1 to determine whether the threshold voltages of the flash memory cells are all less than the read voltage RV1, if it is verified in step S309 that the threshold voltages of all the flash memory cells are all less than the read voltage RV1, step S315 is executed, and if it is verified in step S309 that the threshold voltages of all the flash memory cells are not all less than the read voltage RV1, the index N is incremented by 1 (step S311), and steps S307 and S309 are executed again under the condition that the index N is not greater than the threshold N (step S313).
Through steps S307 to S313, the maximum threshold voltage value RV in the flash memory cell can be tracked by performing a read verify operation on the threshold voltage of the flash memory cell by increasing the read voltage RV 1. Here, by setting the step value Vstep, the accuracy and tracking speed of tracking the maximum threshold voltage RV can be adjusted. In contrast, when the step value Vstep is set to be relatively small, the maximum threshold voltage RV may be calculated more precisely.
On the other hand, in step S313, when the index value N is greater than the threshold value N, the tracking operation of the maximum threshold voltage value RV is stopped, and step S315 is executed.
Continuing with the above description, step S315 begins further programming operations. By setting the target threshold voltage VTh in step S317, and calculating the second program voltage V1 to be equal to V0+ (VTh-RV) + Voffset 1. Voffset1 is a predetermined offset value. Step S318 is to perform a further programming operation on the flash memory cell according to the second programming voltage V1. In step S319, a corresponding verification operation is performed on the flash memory cell according to the second verification voltage PV 1. Specifically, after the further programming operation, the corresponding verifying operation is performed on the flash memory cell according to the second verifying voltage PV1, and is used to verify whether the programming operations of the flash memory cell are all completed. When all flash memory cells can pass verification, the programming action is complete. On the contrary, when not all of the flash memory cells can be verified (failed verification), step S321 is performed (i.e., the threshold voltages of the flash memory cells are not all greater than the second verification voltage PV 1).
Next, step S321 initializes the index value m to be equal to 1. Step S323 presets the program step value Vstep1 to set the third programming voltage V2, and calculates the third programming voltage V2 to be equal to V1+ m × Vstep 1. Step S325 is performed to further program the flash memory cell according to the third programming voltage V2. Step S327 performs a corresponding verification operation on the flash memory cell according to the first verification voltage PV. Specifically, after the further programming operation, the corresponding verifying operation is performed on the flash memory cell according to the first verifying voltage PV, and the verifying operation is used for verifying whether the programming operations of the flash memory cell are all completed. When all flash memory cells can pass verification, the programming action is complete. In contrast, when all of the flash memory cells can pass the verification (fail verification) (i.e., the threshold voltages of the flash memory cells are not all greater than the first verification voltage PV), the index M is incremented by 1 (step S329), and steps S323, S325 and S327 are re-executed under the condition that the index M is not greater than the threshold M (step S331).
Through the proceeding of steps S323 to S331, the final threshold voltage distribution of the flash memory cells can be controlled between the verification voltage and the target threshold voltage VTh by increasing the third programming voltage V2 to program and verify the flash memory cells.
Fig. 4 illustrates a flowchart of a programming method of a flash memory according to another exemplary embodiment of the present invention. Referring to fig. 4, step S401 initializes an index value n equal to 0. In step S403, an initial programming voltage V0 is set, and the flash memory cell is programmed according to the initial programming voltage V0. Step S405 performs a corresponding verifying operation on the flash memory cell according to the first verifying voltage PV, and verifies whether the programming operations of the flash memory cell are all completed. When all flash memory cells can pass verification, the programming action is complete. On the other hand, when not all of the flash memory cells can pass the verification (fail), step S407 is performed (i.e., the threshold voltages of the flash memory cells are not all greater than the first verification voltage PV).
Step S407 sets the initial read voltage RV0 and the step value Vstep, and sets the read voltage RV1 equal to RV0+ Vstep × n. It is noted that in step S407, the calculation of the second programming voltage V1 is performed simultaneously. With the increment of the read voltage RV1, the second programming voltage V1 tracks the increment of the index n, and the second programming voltage V1 is equal to V0+ (VTh-RV 0) -Vstep × n + Voffset2, where RV0 is the initial verify voltage and Voffset2 is the preset offset voltage.
Step S409 performs a read verification operation on the flash memory cells according to the read voltage RV1 to determine whether the threshold voltages of the flash memory cells are all less than the read voltage RV1, if step S409 verifies that the threshold voltages of all the flash memory cells are all less than the read voltage RV1, step S415 is performed, and if step S409 verifies that the threshold voltages of all the flash memory cells are not all less than the read voltage RV1, the index N is incremented by 1 (step S411), and steps S407 and S409 are re-performed under the condition that the index N is not greater than the threshold N (step S413).
As can be understood from the above description, when the verifying operation of step S409 is completed, the second programming voltage V1 can also be generated synchronously.
Then, step S415 starts to perform a further programming operation according to the second programming voltage V1. Step S416 is to perform a further programming operation on the flash memory cell according to the second programming voltage V1. In step S417, a corresponding verification operation is performed on the flash memory cell according to the second verification voltage PV 1. Specifically, after the further programming operation, the corresponding verifying operation is performed on the flash memory cell according to the second verifying voltage PV1, and is used to verify whether the programming operations of the flash memory cell are all completed. When all flash memory cells can pass verification, the programming action is complete. On the contrary, when not all of the flash memory cells can be verified (failed verification), step S419 is performed (i.e., the threshold voltages of the flash memory cells are not all greater than the second verification voltage PV 1).
Next, step S419 initializes the index value m to be equal to 1. Step S421 presets the program step value Vstep1 to set the third programming voltage V2, and calculates the third programming voltage V2 to be equal to V1+ m × Vstep 1. Step S423 performs a further programming operation on the flash memory cell according to the third programming voltage V2. Step S425 performs a corresponding verifying operation on the flash memory cell according to the first verifying voltage PV. Specifically, after the further programming operation, the corresponding verifying operation is performed on the flash memory cell according to the first verifying voltage PV, and the verifying operation is used for verifying whether the programming operations of the flash memory cell are all completed. When all flash memory cells can pass verification, the programming action is complete. In contrast, when all of the flash memory cells can pass verification (fail verification) (i.e., the threshold voltages of the flash memory cells are not all greater than the first verification voltage PV), the index M is incremented by 1 (step S427), and steps S421, S423 and S425 are executed again under the condition that the index M is not greater than the threshold M (step S429).
FIG. 5 illustrates a block diagram of a flash memory storage device according to an exemplary embodiment of the invention. Referring to fig. 5, the flash memory device 500 of the present embodiment includes a flash memory 510 and a controller 520. The flash memory 510 has a plurality of flash memory cells, and the controller includes a memory 521 and is coupled to the flash memory 510. When the operation flow of the embodiment shown in fig. 3 and 4 is performed, the maximum threshold voltage RV and the second programming voltage V1 are calculated, and then the maximum threshold voltage RV and the second programming voltage V1 can be stored in the memory 521 or the flash memory 510. The controller 520 may also include an arithmetic operator, such as an adder. When the operation flow of the embodiment of fig. 3 is performed as described above, the operation of step S317 may be performed by the arithmetic operator to directly calculate the second programming voltage V1. In addition, according to the operation flow of the embodiment of FIG. 4 of the present invention, the second programming voltage V1 is generated according to the step-by-step tracking of the read step value, and it is not necessary to apply an arithmetic operator to generate the second programming voltage.
The flash memory 510 may be a NOR type flash memory or a NAND type flash memory. The flash memory storage device 500 may be a memory card or a Solid State Drive (SSD), and the flash memory storage device 500 may be set in any electronic device such as a digital camera, a mobile phone, a music player, a tablet computer, or a personal computer. And controller 520 may be a processor with computing capabilities. Alternatively, the controller 520 may be a Hardware Circuit such as a tester or a flash memory controller, which is designed by Hardware Description Language (HDL) or any other digital Circuit design known to those skilled in the art and implemented by Field Programmable Gate Array (FPGA), Complex Programmable Logic Device (CPLD) or Application-specific Integrated Circuit (ASIC). Flash memory 510 may contain an arithmetic processor.
Details of the programming operation of the flash memory device have been described in the foregoing embodiments, and are not repeated herein.
In summary, the flash memory device provided in the present invention controls the distribution range of the threshold voltage of the flash memory cells by performing multiple programming operations on the flash memory cells. Thus, a lower initial programming voltage can be set and the flash memory cells can be programmed by gradually adjusting the initial programming voltage, thereby optimizing the threshold voltage distribution of the programmed memory cells. In addition, the invention can program the flash memory cells by setting a lower initial programming action so as to distribute the threshold voltage of the flash memory cells in a preset voltage range. Therefore, the uniformity of the electrical characteristics of the flash memory cell can be controlled, and the performance of the flash memory can be improved.
Although the present invention has been described with reference to the above embodiments, it should be understood that various changes and modifications can be made therein by those skilled in the art without departing from the spirit and scope of the invention.
Claims (14)
1. A method of programming a flash memory, comprising:
setting an initial programming voltage, and performing a first programming operation on a plurality of flash memory cells according to the initial programming voltage;
after the first programming operation, detecting the threshold voltages of the flash memory cells and obtaining the highest threshold voltage;
setting a target threshold voltage, and generating a second programming voltage according to the target threshold voltage, the initial programming voltage and the highest threshold voltage;
performing a second programming operation on the flash memory cells according to the second programming voltage;
after the second programming operation, based on the second programming voltage, performing increment operation according to the programming step value to generate at least one third programming voltage; and
performing at least one third programming operation on the flash memory cells according to the at least one third programming voltage,
wherein after the first programming operation, detecting the threshold voltages of the flash memory cells and obtaining the highest threshold voltage comprises:
setting an initial reading voltage and a reading step value, and generating a plurality of reading voltages according to the initial reading voltage and the integral multiple of the reading step value; and
the reading operations are sequentially performed on the flash memory cells according to the reading voltages, and the highest threshold voltage is obtained.
2. The programming method of a flash memory as claimed in claim 1, further comprising:
the voltage values of the highest threshold voltage and the second programming voltage are written into the flash memory or an external electronic device.
3. The method of programming a flash memory of claim 1, wherein the step of setting the initial programming voltage comprises:
the initial programming voltage is set according to the process parameters of the flash memory.
4. The method for programming a flash memory of claim 1, wherein the step of setting the target threshold voltage, generating the second programming voltage according to the target threshold voltage, the initial programming voltage and the highest threshold voltage comprises:
after obtaining the highest threshold voltage, the second programming voltage is made equal to the initial programming voltage plus the target threshold voltage and minus the highest threshold voltage.
5. The method for programming a flash memory of claim 1, wherein the step of setting the target threshold voltage, generating the second programming voltage according to the target threshold voltage, the initial programming voltage and the highest threshold voltage comprises:
when the verification operation is performed on the flash memory cells according to the verification voltage in sequence, the second programming voltage is synchronously made to be equal to the initial programming voltage plus the target threshold voltage minus the initial reading voltage and minus an integral multiple of the reading step value.
6. The method for programming a flash memory as claimed in claim 1, further comprising after the second programming operation:
verify operations are performed on the memory cells at a verify voltage.
7. The method for programming a flash memory as claimed in claim 1, further comprising after the at least one third programming operation:
at least one verification operation is performed on the memory cells.
8. A flash memory device, comprising:
a flash memory having a plurality of flash memory cells;
a controller coupled to the flash memory and configured to:
setting an initial programming voltage, and performing a first programming operation on a plurality of flash memory cells according to the initial programming voltage;
after the first programming operation, detecting the threshold voltages of the flash memory cells and obtaining the highest threshold voltage;
setting a target threshold voltage, and generating a second programming voltage according to the target threshold voltage, the initial programming voltage and the highest threshold voltage;
performing a second programming operation on the flash memory cells according to the second programming voltage;
after the second programming operation, based on the second programming voltage, performing increment operation according to the programming step value to generate at least one third programming voltage; and
performing at least one third programming operation on the flash memory cells according to the at least one third programming voltage,
wherein after the first programming operation, the threshold voltages of the flash memory cells are detected and the highest threshold voltage is obtained,
the controller sets an initial reading voltage and a reading step value, and generates a plurality of reading voltages according to the initial reading voltage and the integral multiple of the reading step value; and
the controller sequentially verifies the flash memory cells according to the read voltages to obtain the highest threshold voltage.
9. The flash memory device of claim 8, wherein the controller comprises a memory, wherein the voltage values of the highest threshold voltage and the second programming voltage are stored in the memory or the flash memory.
10. The flash memory device of claim 8, wherein in the operation of setting the initial programming voltage,
the controller sets the initial programming voltage according to the process parameters of the flash memory.
11. The flash memory device of claim 8, wherein in operation of setting the target threshold voltage, generating the second programming voltage based on the target threshold voltage, the initial programming voltage, and the highest threshold voltage,
after the controller obtains the highest threshold voltage, the controller makes the second programming voltage equal to the initial programming voltage plus the target threshold voltage minus the highest threshold voltage.
12. The flash memory device of claim 8, wherein in operation of setting the target threshold voltage, generating the second programming voltage based on the target threshold voltage, the initial programming voltage, and the highest threshold voltage,
when the controller sequentially reads the flash memory cells according to the verification voltage, the controller synchronously makes the second programming voltage equal to the initial programming voltage plus the target threshold voltage minus the initial reading voltage plus an integral multiple of the reading step value.
13. The flash memory device of claim 8, wherein after the second programming action,
the controller performs verify operations on the memory cells with verify voltages.
14. The flash memory device of claim 8, wherein after the at least one third programming operation,
the controller performs at least one verify operation on the memory cells with a verify voltage.
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| TWI713860B (en) | 2020-12-21 |
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