TWI713860B - Flash memory apparatus and method for programming thereof - Google Patents

Flash memory apparatus and method for programming thereof Download PDF

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TWI713860B
TWI713860B TW107122372A TW107122372A TWI713860B TW I713860 B TWI713860 B TW I713860B TW 107122372 A TW107122372 A TW 107122372A TW 107122372 A TW107122372 A TW 107122372A TW I713860 B TWI713860 B TW I713860B
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voltage
programming
flash memory
threshold voltage
memory cells
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TW202001910A (en
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鄧才科
李進弘
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力晶積成電子製造股份有限公司
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/10Programming or data input circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention

Abstract

A flash memory device and a programming method thereof are provided. The programming method includes: setting an initial program voltage, and performing a first programming operation on a plurality of flash memory cells according to an initial program voltage; after the first programming operation, detecting a threshold voltages of the flash memory cells and obtaining a highest threshold voltage; setting a target threshold voltage to generate a second program voltage according to the target threshold voltage, the initial voltage, and the highest threshold voltage; performing a second programming operation on the plurality of flash memory cells according to the second program voltage; after the second programming operation, verifying the plurality of flash memory cells by same or different verify voltage, and based on the second program voltage, performing an increment operation according to a programming step value to generate at least one third program voltage; performing at least one third programming operation on the plurality of flash memory cells according to the at least one third program voltage; and enabling the plurality of flash memory cells pass the verify voltage according to a final program voltage.

Description

快閃記憶體裝置及其程式化方法Flash memory device and its programming method

本發明是有關於一種快閃記憶體裝置及其程式化方法。The invention relates to a flash memory device and its programming method.

隨著電子產品的普及化,為因應使用者大量的資訊需求,提供高品質的資料儲存媒介成為電子產品重要的規格之一。在現今的技術領域中,可提供資料寫入以及讀取能力的快閃記憶體成為電子產品必備的資料儲存媒介。With the popularization of electronic products, providing high-quality data storage media has become one of the important specifications of electronic products in response to the large amount of information needs of users. In the current technical field, flash memory, which can provide data writing and reading capabilities, has become an essential data storage medium for electronic products.

當針對快閃記憶體進行程式化動作時,第一次的程式化電壓的設定較為困難,當第一次的程式化電壓的設定過大時,容易產生較差的記憶胞的臨界電壓分佈狀態,當第一次的程式化電壓的設定過小時,造成長的程式化時間。另外基於記憶胞分佈在積體電路中的多個位置上,程式化動作所產生的結果,容易與記憶胞的配置位置相關聯,無法較佳化程式化記憶胞的臨界電壓分佈。另外基於記憶胞在多次抹除與程式化後產生特性變化,程式化的結果,容易與記憶胞抹除與程式化次數相關。When programming the flash memory, it is more difficult to set the programming voltage for the first time. When the programming voltage for the first time is set too large, it is easy to produce poor threshold voltage distribution of the memory cell. The first programming voltage setting is too small, resulting in long programming time. In addition, based on the distribution of memory cells at multiple positions in the integrated circuit, the results generated by the programming action are easily related to the placement positions of the memory cells, and the critical voltage distribution of the programming memory cells cannot be optimized. In addition, based on the characteristic changes of memory cells after multiple erasing and programming, the result of programming is easily related to the number of erasing and programming of memory cells.

本發明提供一種快閃記憶體裝置及其程式化方法,可控制程式化後的記憶胞的臨界電壓分佈狀態及較佳化快閃記憶胞程式化時間。The invention provides a flash memory device and a programming method thereof, which can control the critical voltage distribution state of the programmed memory cell and optimize the programming time of the flash memory cell.

本發明提供一種快閃記憶體的程式化方法,包括:設定初始程式化電壓,並依據初始程式化電壓對多個快閃記憶胞進行第一次程式化動作;在第一次程式化動作後,偵測快閃記憶胞的臨界電壓並獲得最高臨界電壓;設定目標臨界電壓,依據目標臨界電壓、初始程式化電壓以及最高臨界電壓以產生第二程式化電壓;依據第二程式化電壓對快閃記憶胞進行第二次程式化動作;在第二次程式化動作後,基於第二程式化電壓,依據程式化步階值進行遞增動作以產生至少一第三程式化電壓;以及依據至少一第三程式化電壓對快閃記憶胞進行至少一第三次程式化動作。The present invention provides a programming method of a flash memory, which includes: setting an initial programming voltage, and performing a first programming action on a plurality of flash memory cells according to the initial programming voltage; after the first programming action , Detect the threshold voltage of the flash memory cell and obtain the highest threshold voltage; set the target threshold voltage, and generate the second programmed voltage according to the target threshold voltage, the initial programmed voltage, and the highest threshold voltage; The flash memory cell performs a second programming action; after the second programming action, based on the second programming voltage, an incremental action is performed according to the programming step value to generate at least one third programming voltage; and according to at least one The third programming voltage performs at least one third programming action on the flash memory cell.

在本發明提供一種快閃記憶體裝置,包括快閃記憶體以及控制器。快閃記憶體具有多個快閃記憶胞。控制器耦接於快閃記憶體,並用以:設定初始程式化電壓,並依據初始程式化電壓對多個快閃記憶胞進行第一次程式化動作;在第一次程式化動作後,偵測快閃記憶胞的臨界電壓並獲得最高臨界電壓;設定目標臨界電壓,依據目標臨界電壓、初始程式化電壓以及最高臨界電壓以產生第二程式化電壓;依據第二程式化電壓對快閃記憶胞進行第二次程式化動作;在第二次程式化動作後,基於第二程式化電壓,依據程式化步階值進行遞增動作以產生至少一第三程式化電壓;以及依據至少一第三程式化電壓對快閃記憶胞進行至少一第三次程式化動作。The present invention provides a flash memory device, which includes a flash memory and a controller. The flash memory has multiple flash memory cells. The controller is coupled to the flash memory and used to: set the initial programming voltage, and perform the first programming action on the multiple flash memory cells according to the initial programming voltage; after the first programming action, detect Measure the threshold voltage of the flash memory cell and obtain the highest threshold voltage; set the target threshold voltage, and generate the second programmed voltage according to the target threshold voltage, the initial programmed voltage and the highest threshold voltage; compare the flash memory according to the second programmed voltage The cell performs a second programming action; after the second programming action, based on the second programming voltage, an incremental action is performed according to the programming step value to generate at least one third programming voltage; and according to at least one third programming voltage; The programming voltage performs at least one third programming action on the flash memory cell.

基於上述,本發明提供的快閃記憶體裝置透過針對快閃記憶胞的多次程式化動作,來控制程式化快閃記憶胞的臨界電壓的分佈範圍。如此一來,可設定較低的初始程式化,並藉由逐漸調整初始程式化電壓以程式化快閃記憶胞,進而較佳化程式化記憶胞的臨界電壓分佈。Based on the above, the flash memory device provided by the present invention controls the distribution range of the threshold voltage of the programmed flash memory cell through multiple programming actions on the flash memory cell. In this way, a lower initial programming can be set, and the flash memory cell can be programmed by gradually adjusting the initial programming voltage, thereby optimizing the threshold voltage distribution of the programming memory cell.

為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。In order to make the above-mentioned features and advantages of the present invention more comprehensible, the following specific embodiments are described in detail in conjunction with the accompanying drawings.

圖1說明根據本發明的示範性實施例的快閃記憶體的程式化方法的流程圖。請參看圖1,步驟S101設定初始程式化電壓,並依據初始程式化電壓對快閃記憶體中的多個快閃記憶胞進行第一次程式化動作。在此請同時參看圖1以及圖2A,其中圖2A說明根據本發明的示範性實施例的快閃記憶體的各程式化步驟的臨界電壓分佈狀態示意圖。具體而言,在第一次程式化動作未進行前,快閃記憶胞的臨界電壓分佈在被抹除的狀態Z0,而透過步驟S101的進行,快閃記憶胞的臨界電壓分佈可能變更為程式化的狀態Z1(即,此時被程式化的快閃記憶胞的臨界電壓均小於目標臨界電壓)。FIG. 1 illustrates a flowchart of a programming method of a flash memory according to an exemplary embodiment of the present invention. Please refer to FIG. 1, in step S101, an initial programming voltage is set, and a plurality of flash memory cells in the flash memory are programmed for the first time according to the initial programming voltage. Please refer to FIG. 1 and FIG. 2A at the same time. FIG. 2A illustrates a schematic diagram of the threshold voltage distribution state of each programming step of the flash memory according to an exemplary embodiment of the present invention. Specifically, before the first programming action is performed, the threshold voltage distribution of the flash memory cell is in the erased state Z0, and through the execution of step S101, the threshold voltage distribution of the flash memory cell may be changed to the program State Z1 (that is, the threshold voltage of the programmed flash memory cell at this time is less than the target threshold voltage).

值得注意的是,初始程式化電壓的設定方式與記憶體的製程參數相關聯,工程人員可依據記憶體的製程參數設定一個相對低的初始程式化電壓,以針對處於抹除狀態的快閃記憶胞進行程式化動作。 接著,步驟S103在第一次程式化動作後,偵測快閃記憶胞的臨界電壓並獲得快閃記憶胞中的臨界電壓中的最高臨界電壓。具體而言,由於在進行第一次程式化動作後,快閃記憶胞的臨界電壓可能分佈在程式化的狀態Z1,而透過步驟S103的進行,可獲得快閃記憶胞的最高臨界電壓RV。具體而言,可初始化索引值n,並設定初始讀取電壓RV0以及讀取步階值Vstep,以及設定讀取電壓RV1等於

Figure 02_image002
。藉此,依據讀取電壓RV1對快閃記憶胞進行讀取的驗證動作,以判斷快閃記憶胞的臨界電壓是否皆小於讀取電壓RV1。若驗證出所有的快閃記憶胞的臨界電壓皆小於讀取電壓RV1,便將讀取電壓RV1設定為最大臨界電壓值RV。若驗證出所有的快閃記憶胞的臨界電壓未皆小於讀取電壓RV1,使索引值n遞增1,並在索引值n不大於臨界值N的條件下,重新進行上述讀取的驗證動作。步驟S105設定目標臨界電壓,依據目標臨界電壓、初始程式化電壓以及最高臨界電壓以產第二程式化電壓,其中目標臨界電壓為預設的臨界電壓的最大值。具體而言,可預先設定目標臨界電壓VTh,並計算出第二程式化電壓V1等於
Figure 02_image004
。其中,V0為步驟S101中設定的初始程式化電壓,Voffest為預設的偏移電壓值。It is worth noting that the setting method of the initial programming voltage is related to the process parameters of the memory. The engineer can set a relatively low initial programming voltage according to the process parameters of the memory to target the flash memory in the erased state. Cells perform programmed actions. Then, in step S103, after the first programming action, the threshold voltage of the flash memory cell is detected and the highest threshold voltage among the threshold voltages in the flash memory cell is obtained. Specifically, since the threshold voltage of the flash memory cell may be distributed in the programmed state Z1 after the first programming action is performed, the highest threshold voltage RV of the flash memory cell can be obtained by performing step S103. Specifically, the index value n can be initialized, the initial read voltage RV0 and the read step value Vstep can be set, and the read voltage RV1 can be set equal to
Figure 02_image002
. In this way, a verification operation of reading the flash memory cell is performed according to the reading voltage RV1 to determine whether the threshold voltage of the flash memory cell is less than the reading voltage RV1. If it is verified that the threshold voltages of all flash memory cells are less than the read voltage RV1, the read voltage RV1 is set to the maximum threshold voltage RV. If it is verified that the threshold voltages of all the flash memory cells are not less than the read voltage RV1, the index value n is incremented by 1, and under the condition that the index value n is not greater than the threshold value N, the above-mentioned read verification operation is performed again. Step S105 sets a target threshold voltage, and generates a second programming voltage according to the target threshold voltage, the initial programming voltage and the highest threshold voltage, where the target threshold voltage is the maximum value of the preset threshold voltage. Specifically, the target threshold voltage VTh can be preset, and the second programmed voltage V1 can be calculated to be equal to
Figure 02_image004
. Among them, V0 is the initial programming voltage set in step S101, and Voffest is the preset offset voltage value.

值得注意的是,預設的偏移電壓值Voffest可以由工程人員依據需求及快閃記憶體的實際狀態來加以設定,其中預設的偏移電壓值Voffest可以大於、小於或也可以等於0伏特。It is worth noting that the preset offset voltage value Voffest can be set by engineers according to requirements and the actual state of the flash memory. The preset offset voltage value Voffest can be greater than, less than, or equal to 0 volts. .

接著,步驟S107依據步驟S105所獲得的第二程式化電壓V1對快閃記憶胞進行第二次程式化動作。請同時參看圖1以及圖2B,其中圖2B說明根據本發明的示範性實施例的快閃記憶體的各程式化動作的臨界電壓分佈狀態示意圖。具體而言,在第二次程式化動作未進行前,快閃記憶胞的臨界電壓分佈在程式化的狀態Z1,而透過步驟S107的進行,快閃記憶胞的臨界電壓分佈則變更為程式化的狀態Z2(即,快閃記憶胞的臨界電壓未皆大於第二驗證電壓PV1)。步驟S109在第二次程式化動作後,依據程式化步階值以遞增第二程式化電壓並產生至少一第三程式化電壓。具體而言,可預設程式化步階值Vstep1,以計算出第三程式化電壓V2等於

Figure 02_image006
1。其中,V1為第二程式化電壓,m為程式化次數。最後,步驟S111依據至少一第三程式化電壓V2對快閃記憶胞進行一次或多次的第三次程式化動作。請同時參看圖2C,其中圖2C說明根據本發明的示範性實施例的快閃記憶體的各程式化動作的臨界電壓分佈狀態示意圖。具體而言,透過步驟S318~S331或步驟 S416~S429的進行,可將快閃記憶胞的臨界電壓分佈控制在程式化的狀態Z3,其中狀態Z3被控制在第一驗證電壓PV以及目標臨界電壓VTh間,而第一驗證電壓PV以及第二驗證電壓PV1之間具有一個偏移電壓值OT。其中,步驟S318~S331以及步驟S416~S429將在下述的實施例中有進一步的描述。Then, step S107 performs a second programming action on the flash memory cell according to the second programming voltage V1 obtained in step S105. Please refer to FIG. 1 and FIG. 2B at the same time, where FIG. 2B illustrates a schematic diagram of the threshold voltage distribution state of each programming action of the flash memory according to an exemplary embodiment of the present invention. Specifically, before the second programming action is performed, the threshold voltage distribution of the flash memory cell is in the programmed state Z1, and through the execution of step S107, the threshold voltage distribution of the flash memory cell is changed to the programmed state State Z2 (ie, the threshold voltage of the flash memory cell is not all greater than the second verification voltage PV1). In step S109, after the second programming operation, the second programming voltage is incremented according to the programming step value and at least one third programming voltage is generated. Specifically, the programmed step value Vstep1 can be preset to calculate that the third programmed voltage V2 is equal to
Figure 02_image006
1. Among them, V1 is the second programming voltage, and m is the number of programming. Finally, step S111 performs one or more third programming actions on the flash memory cell according to at least one third programming voltage V2. Please refer to FIG. 2C at the same time, in which FIG. 2C illustrates a schematic diagram of the threshold voltage distribution state of each programming action of the flash memory according to an exemplary embodiment of the present invention. Specifically, by performing steps S318~S331 or steps S416~S429, the threshold voltage distribution of the flash memory cell can be controlled in a programmed state Z3, wherein the state Z3 is controlled at the first verification voltage PV and the target threshold voltage There is an offset voltage value OT between the first verification voltage PV and the second verification voltage PV1. Among them, steps S318 to S331 and steps S416 to S429 will be further described in the following embodiments.

藉由上述步驟,本發明可藉由逐步調整程式化電壓對快閃記憶體進行程式化動作,以將快閃記憶體的臨界電壓控制在預設的範圍內(即,第一驗證電壓PV與目標臨界電壓VTh之間),進而最佳化快閃記憶體的臨界電壓分佈。Through the above steps, the present invention can program the flash memory by gradually adjusting the programming voltage to control the threshold voltage of the flash memory within a preset range (ie, the first verification voltage PV and The target threshold voltage VTh), and then optimize the threshold voltage distribution of the flash memory.

圖3說明根據本發明的另一示範性實施例的快閃記憶體的程式化方法的流程圖。請參看圖3,步驟S301初始化索引值n等於0。步驟S303設定初始程式化電壓V0,並依據初始程式化電壓V0對快閃記憶胞進行程式化動作。步驟S305依據第一驗證電壓PV對快閃記憶胞進行對應的驗證動作,並用以驗證快閃記憶胞的程式化動作是否皆已完成。當所有的快閃記憶胞都可以通過驗證時,表示的程式化動作已完成。相對的,當非所有的快閃記憶胞都可以通過驗證(驗證失敗)時,則執行步驟S307(即,快閃記憶胞的臨界電壓未皆大於第一驗證電壓PV)。FIG. 3 illustrates a flowchart of a programming method of a flash memory according to another exemplary embodiment of the present invention. Please refer to FIG. 3, step S301 initializes the index value n to be equal to zero. In step S303, the initial programming voltage V0 is set, and the flash memory cell is programmed according to the initial programming voltage V0. Step S305 performs a corresponding verification action on the flash memory cell according to the first verification voltage PV, and is used to verify whether the programming actions of the flash memory cell have been completed. When all flash memory cells can pass the verification, the stylized action has been completed. In contrast, when not all flash memory cells can pass the verification (verification fails), step S307 is executed (that is, the threshold voltage of the flash memory cells is not all greater than the first verification voltage PV).

步驟S307設定初始讀取電壓RV0以及讀取步階值Vstep,並設定讀取電壓RV1等於

Figure 02_image008
。步驟S309依據讀取電壓RV1對快閃記憶胞進行讀取的驗證動作,以判斷快閃記憶胞的臨界電壓是否皆小於讀取電壓RV1,若步驟S309驗證出所有的快閃記憶胞的臨界電壓皆小於讀取電壓RV1,則執行步驟S315,相對的,若步驟S309驗證出所有的快閃記憶胞的臨界電壓未皆小於讀取電壓RV1,使索引值n遞增1(步驟S311),並在索引值n不大於臨界值N的條件下(步驟S313),重新執行步驟S307以及S309。Step S307 sets the initial read voltage RV0 and the read step value Vstep, and sets the read voltage RV1 equal to
Figure 02_image008
. Step S309 performs a verification operation of reading the flash memory cell according to the read voltage RV1 to determine whether the threshold voltage of the flash memory cell is less than the read voltage RV1. If step S309 verifies the threshold voltage of all the flash memory cells If both are less than the read voltage RV1, then perform step S315. On the other hand, if step S309 verifies that the threshold voltage of all flash memory cells is not less than the read voltage RV1, the index value n is incremented by 1 (step S311), Under the condition that the index value n is not greater than the critical value N (step S313), steps S307 and S309 are executed again.

透過步驟S307至S313,藉由遞增讀取電壓RV1來對快閃記憶胞的臨界電壓進行讀取驗證動作,可追蹤出快閃記憶胞中的最大臨界電壓值RV。在此,透過設定步階值Vstep的大小,可以調整追蹤出最大臨界電壓值RV的精準度以及追蹤速度。其中,當設定相對大的步階值Vstep時,可較快計算出最大臨界電壓值RV,相對的,當設定相對小的步階值Vstep時,可計算出較精準的最大臨界電壓值RV。Through steps S307 to S313, the threshold voltage of the flash memory cell is read and verified by increasing the read voltage RV1, and the maximum threshold voltage RV in the flash memory cell can be tracked. Here, by setting the size of the step value Vstep, the accuracy of tracking the maximum threshold voltage value RV and the tracking speed can be adjusted. Among them, when a relatively large step value Vstep is set, the maximum threshold voltage value RV can be calculated faster, and relatively, when a relatively small step value Vstep is set, a more accurate maximum threshold voltage value RV can be calculated.

在另一方面,在步驟S313中,當判斷出索引值n大於臨界值N時,則停止最大臨界電壓值RV的追蹤動作,並執行步驟S315。On the other hand, in step S313, when it is determined that the index value n is greater than the threshold value N, the tracking operation of the maximum threshold voltage value RV is stopped, and step S315 is executed.

承續上述的說明,步驟S315開始進行進一步的程式化動作。透過在步驟S317中設定目標臨界電壓VTh,並計算出第二程式化電壓V1等於

Figure 02_image010
1。其中,Voffset1為預設的偏壓值。步驟S318依據第二程式化電壓V1對快閃記憶胞進行進一步的程式化動作。步驟S319依據第二驗證電壓PV1對快閃記憶胞進行對應的驗證動作。具體而言,在進一步的程式化動作後,依據第二驗證電壓PV1對快閃記憶胞進行對應的驗證動作,並用以驗證快閃記憶胞的程式化動作是否皆已完成。當所有的快閃記憶胞都可以通過驗證時,表示的程式化動作已完成。相對的,當非所有的快閃記憶胞都可以通過驗證(驗證失敗)時,則執行步驟S321(即,快閃記憶胞的臨界電壓未皆大於第二驗證電壓PV1)。Continuing the above description, step S315 starts to perform further stylized actions. By setting the target threshold voltage VTh in step S317, and calculating the second programmed voltage V1 equal to
Figure 02_image010
1. Among them, Voffset1 is the preset bias value. Step S318 performs a further programming action on the flash memory cell according to the second programming voltage V1. Step S319 performs a corresponding verification action on the flash memory cell according to the second verification voltage PV1. Specifically, after further programming actions, corresponding verification actions are performed on the flash memory cells according to the second verification voltage PV1, and used to verify whether the programming actions of the flash memory cells have been completed. When all flash memory cells can pass the verification, the stylized action has been completed. In contrast, when not all the flash memory cells can pass the verification (verification fails), step S321 is executed (that is, the threshold voltage of the flash memory cells is not all greater than the second verification voltage PV1).

接著,步驟S321初始化索引值m等於1。步驟S323預設程式化步階值Vstep1以設定第三程式化電壓V2,並計算出第三程式化電壓V2等於

Figure 02_image012
。步驟S325依據第三程式化電壓V2對快閃記憶胞進行更進一步的程式化動作。步驟S327依據第一驗證電壓PV對快閃記憶胞進行對應的驗證動作。具體而言,在更進一步的程式化動作後,依據第一驗證電壓PV對快閃記憶胞進行對應的驗證動作,並用以驗證快閃記憶胞的程式化動作是否皆已完成。當所有的快閃記憶胞都可以通過驗證時,表示的程式化動作已完成。相對的,當非所有的快閃記憶胞都可以通過驗證(驗證失敗)時(即,快閃記憶胞的臨界電壓未皆大於第一驗證電壓PV),使索引值m遞增1(步驟S329),並在索引值m不大於臨界值M的條件下(步驟S331),重新執行步驟S323、S325以及S327。Next, step S321 initializes the index value m to be equal to 1. Step S323 presets the programming step value Vstep1 to set the third programming voltage V2, and calculates that the third programming voltage V2 is equal to
Figure 02_image012
. Step S325 performs a further programming action on the flash memory cell according to the third programming voltage V2. Step S327 performs a corresponding verification action on the flash memory cell according to the first verification voltage PV. Specifically, after a further programming action, a corresponding verification action is performed on the flash memory cell according to the first verification voltage PV, and used to verify whether the programming action of the flash memory cell has been completed. When all flash memory cells can pass the verification, the stylized action has been completed. In contrast, when not all flash memory cells can pass the verification (verification fails) (that is, the threshold voltage of the flash memory cells is not all greater than the first verification voltage PV), the index value m is incremented by 1 (step S329) , And under the condition that the index value m is not greater than the critical value M (step S331), steps S323, S325, and S327 are executed again.

透過步驟S323至步驟S331的進行,藉由遞增第三程式化電壓V2來對快閃記憶胞程式化與驗證動作,可將快閃記憶胞的最終臨界電壓分佈控制於驗證電壓以及目標臨界電壓VTh之間。Through the process of step S323 to step S331, by increasing the third programming voltage V2 to program and verify the flash memory cell, the final threshold voltage distribution of the flash memory cell can be controlled to the verification voltage and the target threshold voltage VTh between.

圖4說明根據本發明的另一示範性實施例的快閃記憶體的程式化方法的流程圖。請參看圖4,步驟S401初始化索引值n等於0。步驟S403設定初始程式化電壓V0,並依據初始程式化電壓V0對快閃記憶胞進行程式化動作。步驟S405依據第一驗證電壓PV對快閃記憶胞進行對應的驗證動作,並用以驗證快閃記憶胞的程式化動作是否皆已完成。當所有的快閃記憶胞都可以通過驗證時,表示的程式化動作已完成。相對的,當非所有的快閃記憶胞都可以通過驗證(驗證失敗)時,則執行步驟S407(即,快閃記憶胞的臨界電壓未皆大於第一驗證電壓PV)。FIG. 4 illustrates a flowchart of a programming method of a flash memory according to another exemplary embodiment of the present invention. Please refer to FIG. 4, step S401 initializes the index value n to be equal to zero. In step S403, the initial programming voltage V0 is set, and the flash memory cell is programmed according to the initial programming voltage V0. Step S405 performs a corresponding verification action on the flash memory cell according to the first verification voltage PV, and is used to verify whether the programming actions of the flash memory cell have been completed. When all flash memory cells can pass the verification, the stylized action has been completed. In contrast, when not all flash memory cells can pass the verification (verification fails), step S407 is executed (that is, the threshold voltage of the flash memory cells is not all greater than the first verification voltage PV).

步驟S407設定初始讀取電壓RV0以及步階值Vstep,並設定讀取電壓RV1等於

Figure 02_image013
。值得注意的,在步驟S407中,另同步進行第二程式化電壓V1的計算動作。其中,隨著讀取電壓RV1的遞增動作,第二程式化電壓V1可隨著索引值n的增加而進行追蹤的動作,並使第二程式化電壓V1=V0+(VTh – RV0) – Vstep × n + Voffset2,其中,RV0為初始驗證電壓,Voffset2為預設的偏壓值。Step S407 sets the initial read voltage RV0 and the step value Vstep, and sets the read voltage RV1 equal to
Figure 02_image013
. It is worth noting that in step S407, the calculation of the second programmed voltage V1 is also performed simultaneously. Wherein, as the reading voltage RV1 increases, the second programmed voltage V1 can be tracked as the index value n increases, and the second programmed voltage V1=V0+(VTh – RV0) – Vstep × n + Voffset2, where RV0 is the initial verification voltage, and Voffset2 is the preset bias value.

步驟S409依據讀取電壓RV1對快閃記憶胞進行讀取的驗證動作,以判斷快閃記憶胞的臨界電壓是否皆小於讀取電壓RV1,若步驟S409驗證出所有的快閃記憶胞的臨界電壓皆小於讀取電壓RV1,則執行步驟S415,相對的,若步驟S409驗證出所有的快閃記憶胞的臨界電壓未皆小於讀取電壓RV1,使索引值n遞增1(步驟S411),並在索引值n不大於臨界值N的條件下(步驟S413),重新執行步驟S407以及S409。Step S409 performs a verification operation of reading the flash memory cell according to the read voltage RV1 to determine whether the threshold voltage of the flash memory cell is less than the read voltage RV1. If step S409 verifies the threshold voltage of all the flash memory cells If both are less than the read voltage RV1, step S415 is executed. On the other hand, if step S409 verifies that the threshold voltage of all flash memory cells is not less than the read voltage RV1, the index value n is incremented by 1 (step S411), and Under the condition that the index value n is not greater than the critical value N (step S413), steps S407 and S409 are executed again.

由上述說明可以得知,當步驟S409的驗證動作完成時,第二程式化電壓V1也可同步被產生。It can be known from the above description that when the verification operation in step S409 is completed, the second programmed voltage V1 can also be generated synchronously.

接著,步驟S415開始依據第二程式化電壓V1進行進一步的程式化動作。步驟S416依據第二程式化電壓V1對快閃記憶胞進行進一步的程式化動作。步驟S417依據第二驗證電壓PV1對快閃記憶胞進行對應的驗證動作。具體而言,在進一步的程式化動作後,依據第二驗證電壓PV1對快閃記憶胞進行對應的驗證動作,並用以驗證快閃記憶胞的程式化動作是否皆已完成。當所有的快閃記憶胞都可以通過驗證時,表示的程式化動作已完成。相對的,當非所有的快閃記憶胞都可以通過驗證(驗證失敗)時,則執行步驟S419(即,快閃記憶胞的臨界電壓未皆大於第二驗證電壓PV1)。Then, step S415 starts to perform further programming actions according to the second programming voltage V1. Step S416 performs a further programming action on the flash memory cell according to the second programming voltage V1. Step S417 performs a corresponding verification action on the flash memory cell according to the second verification voltage PV1. Specifically, after further programming actions, corresponding verification actions are performed on the flash memory cells according to the second verification voltage PV1, and used to verify whether the programming actions of the flash memory cells have been completed. When all flash memory cells can pass the verification, the stylized action has been completed. In contrast, when not all flash memory cells can pass the verification (verification fails), step S419 is executed (that is, the threshold voltage of the flash memory cells is not all greater than the second verification voltage PV1).

接著,步驟S419初始化索引值m等於1。步驟S421預設程式化步階值Vstep1以設定第三程式化電壓V2,並計算出第三程式化電壓V2等於

Figure 02_image012
。步驟S423依據第三程式化電壓V2對快閃記憶胞進行更進一步的程式化動作。步驟S425依據第一驗證電壓PV對快閃記憶胞進行對應的驗證動作。具體而言,在更進一步的程式化動作後,依據第一驗證電壓PV對快閃記憶胞進行對應的驗證動作,並用以驗證快閃記憶胞的程式化動作是否皆已完成。當所有的快閃記憶胞都可以通過驗證時,表示的程式化動作已完成。相對的,當非所有的快閃記憶胞都可以通過驗證(驗證失敗)時(即,快閃記憶胞的臨界電壓未皆大於第一驗證電壓PV),使索引值m遞增1(步驟S427),並在索引值m不大於臨界值M的條件下(步驟S429),重新執行步驟S421、S423以及S425。Next, step S419 initializes the index value m to be equal to 1. Step S421 presets the programming step value Vstep1 to set the third programming voltage V2, and calculates that the third programming voltage V2 is equal to
Figure 02_image012
. Step S423 performs a further programming action on the flash memory cell according to the third programming voltage V2. Step S425 performs a corresponding verification action on the flash memory cell according to the first verification voltage PV. Specifically, after a further programming action, a corresponding verification action is performed on the flash memory cell according to the first verification voltage PV, and used to verify whether the programming action of the flash memory cell has been completed. When all flash memory cells can pass the verification, the stylized action has been completed. In contrast, when not all flash memory cells can pass the verification (verification fails) (that is, the threshold voltage of the flash memory cells is not all greater than the first verification voltage PV), the index value m is incremented by 1 (step S427) , And under the condition that the index value m is not greater than the critical value M (step S429), steps S421, S423, and S425 are executed again.

圖5說明根據本發明的示範性實施例的快閃記憶體儲存裝置的方塊圖。請參看圖5,本實施例的快閃記憶體裝置500包括快閃記憶體510以及控制器520。其中,快閃記憶體510具有多個快閃記憶胞,而控制器包括記憶體521,並耦接於快閃記憶體510。當進行如上述的圖3以及圖4實施例的動作流程時,在計算出最高臨界電壓RV以及第二程式化電壓V1後,可將最高臨界電壓RV以及第二程式化電壓V1儲存於記憶體521或快閃記憶體510中。控制器520還可包括算術運算器,例如是加法器。當進行如上述的圖3實施例的動作流程時,可透過算術運算器進行步驟S317的動作以直接計算出第二程式化電壓V1。此外,對應本發明圖4實施例的動作流程,第二程式化電壓V1是依據讀取步階值逐步追蹤而產生,可不需要應用算術運算器來產生。FIG. 5 illustrates a block diagram of a flash memory storage device according to an exemplary embodiment of the invention. Please refer to FIG. 5, the flash memory device 500 of this embodiment includes a flash memory 510 and a controller 520. The flash memory 510 has a plurality of flash memory cells, and the controller includes a memory 521 and is coupled to the flash memory 510. When performing the operation flow of the above-mentioned embodiment in FIG. 3 and FIG. 4, after the highest threshold voltage RV and the second programmed voltage V1 are calculated, the highest threshold voltage RV and the second programmed voltage V1 can be stored in the memory 521 or flash memory 510. The controller 520 may also include an arithmetic operator, such as an adder. When the operation flow of the embodiment in FIG. 3 is performed as described above, the operation of step S317 may be performed through an arithmetic operator to directly calculate the second programmed voltage V1. In addition, corresponding to the operation flow of the embodiment of FIG. 4 of the present invention, the second programming voltage V1 is generated by gradual tracking based on the read step value, and it does not need to be generated by an arithmetic operator.

此外,快閃記憶體510可以是NOR型快閃記憶體,也可以是NAND型快閃記憶體。並且,快閃記憶體儲存裝置500可以是記憶卡或固態硬碟(Solid State Drive, SSD)等,且快閃記憶體裝置500可設定於數位相機、手機、音樂撥放器、平板電腦或個人電腦等任意電子裝置中。而控制器520可以為具運算能力的處理器。或者,控制器520可以是透過硬體描述語言(Hardware Description Language, HDL)或是其他任意本領域具通常知識者所熟知的數位電路的設計方式來進行設計,並透過現場可程式邏輯門陣列(Field Programmable Gate Array, FPGA)、複雜可程式邏輯裝置(Complex Programmable Logic Device, CPLD)或是特殊應用積體電路(Application-specific Integrated Circuit, ASIC)的方式來實現的硬體電路如測試機台、快閃記憶體控制器。快閃記憶體510可以含有運算處理器。In addition, the flash memory 510 may be a NOR-type flash memory or a NAND-type flash memory. Moreover, the flash memory storage device 500 can be a memory card or a solid state drive (SSD), etc., and the flash memory device 500 can be set in a digital camera, a mobile phone, a music player, a tablet computer or a personal computer. In any electronic device such as a computer. The controller 520 may be a processor with computing capability. Alternatively, the controller 520 can be designed through a hardware description language (Hardware Description Language, HDL) or any other digital circuit design method known to those with ordinary knowledge in the art, and through a field programmable logic gate array ( Field Programmable Gate Array, FPGA), complex programmable logic device (Complex Programmable Logic Device, CPLD), or special application integrated circuit (Application-specific Integrated Circuit, ASIC) to implement hardware circuits such as test machines, Flash memory controller. The flash memory 510 may contain an arithmetic processor.

關於快閃記憶體裝置的程式化動作的實施細節在前述的實施例中已有詳細的說明,以下恕不多贅述。The implementation details of the programming actions of the flash memory device have been described in detail in the foregoing embodiments, and will not be repeated here.

綜上所述,本發明提供的快閃記憶體裝置透過針對快閃記憶胞的多次程式化動作,來控制程式化快閃記憶胞的臨界電壓的分布範圍。如此一來,可設定較低的初始程式化,並藉由逐漸調整初始程式化電壓以程式化快閃記憶胞,進而較佳化程式化記憶胞的臨界電壓分佈。此外,本發明更能藉由設定一個較低的初始程式化動作對快閃記憶胞程式化,以將快閃記憶胞的臨界電壓可分佈於預設的電壓範圍中。如此,快閃記憶胞的電氣特性的均勻度可以得到控制,可提升快閃記憶體的表現度。In summary, the flash memory device provided by the present invention controls the distribution range of the threshold voltage of the programmed flash memory cell through multiple programming actions on the flash memory cell. In this way, a lower initial programming can be set, and the flash memory cell can be programmed by gradually adjusting the initial programming voltage, thereby optimizing the threshold voltage distribution of the programming memory cell. In addition, the present invention can program the flash memory cell by setting a lower initial programming action, so that the threshold voltage of the flash memory cell can be distributed in a preset voltage range. In this way, the uniformity of the electrical characteristics of the flash memory cell can be controlled, and the performance of the flash memory can be improved.

雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許的更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. The scope of protection of the present invention shall be determined by the scope of the attached patent application.

Z0~Z3‧‧‧程式化的狀態RV0‧‧‧初始讀取電壓Vstep‧‧‧讀取步階值RV1‧‧‧讀取電壓RV‧‧‧最高臨界電壓PV‧‧‧第一驗證電壓PV1‧‧‧第二驗證電壓VTh‧‧‧目標臨界電壓OT‧‧‧偏移電壓值V0‧‧‧初始程式化電壓V1‧‧‧第二次程式化電壓V‧‧‧第三次後程式化電壓Vstep1‧‧‧程式化步階值S101~S111、S301~S331、S401~S429‧‧‧程式化的步驟500‧‧‧快閃記憶體裝置510‧‧‧快閃記憶體520‧‧‧控制器Z0~Z3‧‧‧Programmed state RV0‧‧‧Initial read voltage Vstep‧‧‧Read step value RV1‧‧‧Read voltage RV‧‧‧Highest threshold voltage PV‧‧‧First verification voltage PV1 ‧‧‧Second verification voltage VTh‧‧‧Target threshold voltage OT‧‧‧Offset voltage value V0‧‧‧Initial programming voltage V1‧‧‧Second programming voltage V‧‧‧After third programming Voltage Vstep1‧‧‧Programmed step value S101~S111, S301~S331, S401~S429‧‧‧Programmed step 500‧‧‧Flash memory device 510‧‧‧Flash memory 520‧‧‧Control Device

圖1說明根據本發明的示範性實施例的快閃記憶體的程式化方法的流程圖。 圖2A至2C說明根據本發明的示範性實施例的快閃記憶體的各程式化動作的臨界電壓分佈狀態示意圖。 圖3說明根據本發明的另一示範性實施例的快閃記憶體的程式化方法的流程圖。 圖4說明根據本發明的另一示範性實施例的快閃記憶體的程式化方法的流程圖。 圖5說明根據本發明的示範性實施例的快閃記憶體儲存裝置的方塊圖。FIG. 1 illustrates a flowchart of a programming method of a flash memory according to an exemplary embodiment of the present invention. 2A to 2C illustrate schematic diagrams of the threshold voltage distribution state of each programming action of the flash memory according to an exemplary embodiment of the present invention. FIG. 3 illustrates a flowchart of a programming method of a flash memory according to another exemplary embodiment of the present invention. FIG. 4 illustrates a flowchart of a programming method of a flash memory according to another exemplary embodiment of the present invention. FIG. 5 illustrates a block diagram of a flash memory storage device according to an exemplary embodiment of the invention.

S101~S111‧‧‧程式化的步驟 S101~S111‧‧‧Programmed steps

Claims (6)

一種快閃記憶體的程式化方法,包括:依據多個快閃記憶體的製程參數以設定初始程式化電壓,並依據該初始程式化電壓對多個快閃記憶胞進行一第一次程式化動作;在該第一次程式化動作後,偵測該些快閃記憶胞的臨界電壓並獲得一最高臨界電壓;設定一目標臨界電壓,依據該目標臨界電壓、該初始程式化電壓以及該最高臨界電壓以產生一第二程式化電壓;依據該第二程式化電壓對該些快閃記憶胞進行一第二次程式化動作;在該第二次程式化動作後,設定一第一驗證電壓,依序依據該第一驗證電壓對該些快閃記憶胞進行驗證動作,並基於該第二程式化電壓,依據一程式化步階值進行遞增動作以產生至少一第三程式化電壓;以及依據該至少一第三程式化電壓對該些快閃記憶胞進行至少一第三次程式化動作,並設定一第二驗證電壓,在各該至少一第三次程式化動作後,依序依據該第二驗證電壓對該些快閃記憶胞進行驗證動作,其中在該第一次程式化動作後,偵測該些快閃記憶胞的臨界電壓並獲得該最高臨界電壓的步驟包括:設定一初始讀取電壓以及讀取步階值,依據該初始讀取 電壓以及該讀取步階值的整數倍以產生多個讀取電壓;以及依序依據該些讀取電壓對該些快閃記憶胞進行讀取動作,並藉以獲得該最高臨界電壓,其中設定該目標臨界電壓,依據該目標臨界電壓、該初始程式化電壓以及該最高臨界電壓以產生該第二程式化電壓的步驟包括:在獲得該最高臨界電壓之後,使該第二程式化電壓等於該初始程式化電壓加上該目標臨界電壓並減去該最高臨界電壓;或者在依序依據該些讀取電壓對該些快閃記憶胞進行讀取動作時,同步使該第二程式化電壓等於該初始程式化電壓加上該目標臨界電壓減去該初始讀取電壓並減去該讀取步階值的整數倍。 A programming method for flash memory includes: setting an initial programming voltage according to the process parameters of a plurality of flash memories, and performing a first programming on a plurality of flash memory cells according to the initial programming voltage Action; after the first programming action, detect the threshold voltage of the flash memory cells and obtain a maximum threshold voltage; set a target threshold voltage, based on the target threshold voltage, the initial programming voltage and the maximum Threshold voltage to generate a second programming voltage; performing a second programming action on the flash memory cells according to the second programming voltage; setting a first verification voltage after the second programming action , Performing a verification operation on the flash memory cells sequentially according to the first verification voltage, and performing an incremental operation according to a programming step value based on the second programming voltage to generate at least a third programming voltage; and Perform at least one third programming action on the flash memory cells according to the at least one third programming voltage, and set a second verification voltage. After each at least one third programming action, follow The second verification voltage performs a verification action on the flash memory cells, wherein after the first programming action, the step of detecting the threshold voltage of the flash memory cells and obtaining the highest threshold voltage includes: setting a The initial reading voltage and reading step value are based on the initial reading Voltage and integer multiples of the read step value to generate a plurality of read voltages; and sequentially perform read operations on the flash memory cells according to the read voltages to obtain the highest threshold voltage, wherein The target threshold voltage, the step of generating the second programmed voltage according to the target threshold voltage, the initial programmed voltage and the highest threshold voltage includes: after obtaining the highest threshold voltage, making the second programmed voltage equal to the The initial programmed voltage is added to the target threshold voltage and the highest threshold voltage is subtracted; or when the flash memory cells are read sequentially according to the read voltages, the second programmed voltage is synchronously made equal to The initial programming voltage plus the target threshold voltage minus the initial reading voltage and subtracting an integer multiple of the reading step value. 如申請專利範圍第1項所述的快閃記憶體的程式化方法,更包括:使該最高臨界電壓以及該第二程式化電壓的電壓值被寫入至該快閃記憶體或一外部電子裝置中。 The programming method of flash memory as described in item 1 of the scope of the patent application further includes: enabling the voltage values of the highest threshold voltage and the second programming voltage to be written to the flash memory or an external electron In the installation. 如申請專利範圍第1項所述的快閃記憶體的程式化方法,其中在該第二次程式化動作後更包括:該第一驗證電壓可大於、小於或等於該第二驗證電壓。 According to the programming method of the flash memory described in claim 1, wherein after the second programming action, the method further includes: the first verification voltage can be greater than, less than or equal to the second verification voltage. 一種快閃記憶體裝置,包括:一快閃記憶體,具有多個快閃記憶胞;一控制器,耦接於該快閃記憶體,並用以:依據該些快閃記憶體的製程參數以設定初始程式化電壓,並依據該初始程式化電壓對該些快閃記憶胞進行一第一次程式化動作;在該第一次程式化動作後,偵測該些快閃記憶胞的臨界電壓並獲得一最高臨界電壓;設定一目標臨界電壓,依據該目標臨界電壓、該初始程式化電壓以及該最高臨界電壓以產生一第二程式化電壓;依據該第二程式化電壓對該些快閃記憶胞進行一第二次程式化動作;在該第二次程式化動作後,設定一第一驗證電壓,依序依據該第一驗證電壓對該些快閃記憶胞進行驗證動作,並基於該第二程式化電壓,依據一程式化步階值進行遞增動作以產生至少一第三程式化電壓;以及依據該至少一第三程式化電壓對該些快閃記憶胞進行至少一第三次程式化動作,並設定一第二驗證電壓,在各該至少一第三次程式化動作後,依序依據該第二驗證電壓對該些快閃記憶胞進行驗證動作,其中在該第一次程式化動作後,偵測該些快閃記憶胞的 臨界電壓並獲得該最高臨界電壓的運作中,該控制器設定一初始讀取電壓以及一讀取步階值,該控制器依據該初始讀取電壓以及該讀取步階值的整數倍以產生多個讀取電壓;以及該控制器依序依據該些讀取電壓對該些快閃記憶胞進行驗證動作,並藉以獲得該最高臨界電壓,其中在設定該目標臨界電壓,依據該目標臨界電壓、該初始程式化電壓以及該最高臨界電壓以產生該第二程式化電壓的運作中:在該控制器獲得該最高臨界電壓之後,該控制器使該第二程式化電壓等於該初始程式化電壓加上該目標臨界電壓並減去該最高臨界電壓,或者,在該控制器依序依據該些讀取電壓對該些快閃記憶胞進行讀取動作時,該控制器同步使該第二程式化電壓等於該初始程式化電壓加上該目標臨界電壓減去該初始讀取電壓並減去該讀取步階值的整數倍。 A flash memory device includes: a flash memory having a plurality of flash memory cells; a controller, coupled to the flash memory, and used for: according to the process parameters of the flash memory Set the initial programming voltage, and perform a first programming action on the flash memory cells according to the initial programming voltage; after the first programming action, detect the threshold voltage of the flash memory cells And obtain a highest threshold voltage; set a target threshold voltage, generate a second programmed voltage according to the target threshold voltage, the initial programmed voltage, and the highest threshold voltage; flash the flashes according to the second programmed voltage The memory cell performs a second programming action; after the second programming action, a first verification voltage is set, the flash memory cells are verified sequentially according to the first verification voltage, and based on the The second programming voltage performs an incremental action based on a programming step value to generate at least one third programming voltage; and performing at least one third programming on the flash memory cells based on the at least one third programming voltage After each of the at least one third programming action, the flash memory cells are sequentially verified according to the second verification voltage, and a second verification voltage is set, wherein in the first programming After the operation, detect the flash memory cells In the operation of obtaining the highest threshold voltage, the controller sets an initial read voltage and a read step value, and the controller generates an initial read voltage and an integer multiple of the read step value A plurality of read voltages; and the controller sequentially performs a verification operation on the flash memory cells according to the read voltages to obtain the highest threshold voltage, wherein the target threshold voltage is set according to the target threshold voltage , The initial programming voltage and the highest threshold voltage to generate the second programming voltage: after the controller obtains the highest threshold voltage, the controller makes the second programming voltage equal to the initial programming voltage The target threshold voltage is added and the highest threshold voltage is subtracted, or, when the controller reads the flash memory cells sequentially according to the read voltages, the controller synchronizes the second program The conversion voltage is equal to the initial programming voltage plus the target threshold voltage minus the initial reading voltage and minus an integer multiple of the reading step value. 如申請專利範圍第4項所述的快閃記憶體裝置,其中該控制器包括一記憶體,其中該最高臨界電壓以及該第二程式化電壓的電壓值儲存於該記憶體或該快閃記憶體中。 The flash memory device described in claim 4, wherein the controller includes a memory, wherein the voltage values of the highest threshold voltage and the second programmed voltage are stored in the memory or the flash memory Body. 如申請專利範圍第4項所述的快閃記憶體裝置,其中在該第二次程式化動作後,該第一驗證電壓可大於、小於或等於該第二驗證電壓。 According to the flash memory device described in claim 4, after the second programming operation, the first verification voltage can be greater than, less than or equal to the second verification voltage.
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