CN110658902A - Memory power supply circuit and electronic device - Google Patents
Memory power supply circuit and electronic device Download PDFInfo
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- CN110658902A CN110658902A CN201911213096.9A CN201911213096A CN110658902A CN 110658902 A CN110658902 A CN 110658902A CN 201911213096 A CN201911213096 A CN 201911213096A CN 110658902 A CN110658902 A CN 110658902A
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Abstract
The invention provides a memory power supply circuit and an electronic device. The memory power supply circuit comprises a main control chip and first to third power supply ends, wherein the main control chip comprises first to third input ends and first to third output ends. The first input end is used for receiving input signals, the first output end is used for outputting first output signals obtained by converting the input signals through the main control chip, the second input end is further connected with the first power supply end to receive the first output signals, the second output end is used for outputting second output signals obtained by converting the first output signals through the second input end through the main control chip, the third input end is also used for receiving the working voltage, the third output end is used for outputting third output signals obtained by converting the working voltage input through the third input end through the main control chip, and the first, second and third output ends are respectively connected to the first, second and third power supply ends to output voltages of 1.2V, 0.6V and 2.5V.
Description
Technical Field
The present disclosure relates to power supply technologies, and particularly to a memory power supply circuit and an electronic device.
Background
The computer is one of the most advanced scientific and technical inventions in the 20 th century, has extremely important influence on the production activities and social activities of human beings, and develops rapidly with strong vitality. The application field of the computer system is expanded from the initial military scientific research application to various fields of society, a large-scale computer industry is formed, the technology progress in the global range is driven, the deep social revolution is caused, and the computer is spread throughout general schools, enterprises and public institutions, enters common people and becomes an essential tool in the information society. The computer mainboard is the core pivot that the computer constitutes, is computer core system operation module, also is the essential module of computer constitution, whether computer system can stable work, and the stability of work is directly influenced to the good or bad of its performance.
The main board memory is one of the important components in various electronic devices such as computers, and is a bridge for communicating with the CPU. All programs in the electronic devices such as computers are operated in the memory, so the performance of the memory has a great influence on the electronic devices such as computers. However, in order to effectively and fully exert the working performance of the memory, the performance of the power supply module plays a very critical role. Therefore, it is a direction of research of designers to realize a memory power supply circuit that has at least one of the advantages of simpler wiring, fewer parts, and less occupied PCB space.
Disclosure of Invention
In order to solve the above technical problems, the present invention provides a memory power supply circuit with simple wiring and fewer parts, and an electronic device using the memory power supply circuit.
An embodiment of the present invention provides a memory power supply circuit, where the memory power supply circuit includes a main control chip, a first power supply terminal, a second power supply terminal, and a third power supply terminal, the main control chip includes a first input terminal, a second input terminal, a third input terminal, an enable terminal, a driving terminal, a first output terminal, a second output terminal, and a third output terminal, the enable terminal is configured to receive an enable signal to control normal operation of the main control chip, the driving terminal is configured to receive a 3.3V working voltage, the first input terminal is configured to receive a 12V input signal, the first output terminal is configured to output a 1.2V first output signal obtained by converting the input signal by the main control chip, the first output terminal is further connected to the first power supply terminal, the second input terminal is further connected to the first power supply terminal to receive the first output signal, and the second output terminal is configured to output a first output signal obtained by converting the second input terminal by the main control chip The second output signal of 0.6V, the second output is still connected to the second supply end, the third input is also used for receiving operating voltage, the third output is used for outputting the third output signal that the operating voltage conversion that main control chip will the third input was obtained, the third output still is connected to the third supply end, main control chip still includes second reference voltage output, first supply end is 1.2V's VDDQ voltage output, the second supply end is 0.6V's VTT voltage output, the third supply end is 2.5V's VPP voltage output, the second reference voltage output is VTT reference voltage output.
In an embodiment, the memory power supply circuit further includes a feedback output line and an auxiliary line, the main control chip further includes a self-boosting end and a feedback end, the self-boosting end is connected to the first output end through the auxiliary line, the auxiliary line includes an auxiliary resistor and an auxiliary capacitor connected in series, and the feedback end is connected to the first power supply end through the feedback output line.
In an embodiment, the memory power supply circuit further includes an output current stabilizing line, the first output terminal is connected to the first power supply terminal via the output current stabilizing line, and the output current stabilizing line includes an output inductor.
In one embodiment, the feedback output circuit includes a first voltage-dividing resistor, a second voltage-dividing resistor, a third voltage-dividing resistor, and a capacitor, the first power supply terminal is grounded via the first voltage-dividing resistor, the second voltage-dividing resistor, and the third voltage-dividing resistor in sequence, the feedback terminal is connected to a node between the second voltage-dividing resistor and the third voltage-dividing resistor, and the capacitor is connected between the first power supply terminal and a node between the second voltage-dividing resistor and the third voltage-dividing resistor.
In one embodiment, the memory power supply circuit further includes a first input voltage stabilizing line, a second input voltage stabilizing line, and a third input voltage stabilizing line, the first input terminal is further grounded via the first input voltage stabilizing line, the driving terminal is further grounded via the second input voltage stabilizing line, the third input terminal is further grounded via the third input voltage stabilizing line, the first input voltage stabilizing line and the input voltage stabilizing line include a chip multilayer ceramic capacitor and a solid capacitor, and the second input voltage stabilizing line and the third input voltage stabilizing line include at least one capacitor.
In one embodiment, the memory power supply circuit further includes a first output voltage stabilization line, a second output voltage stabilization line, and a third output voltage stabilization line, the first output terminal is grounded via the first output voltage stabilization line, the second output terminal is grounded via the second output voltage stabilization line, the third output terminal is grounded via the third output voltage stabilization line, the first output voltage stabilization line includes a chip type multilayer ceramic capacitor and a solid state capacitor, the second output voltage stabilization line includes a chip type multilayer ceramic capacitor, and the third output voltage stabilization line includes at least one capacitor.
In one embodiment, the main control chip further includes a frequency setting terminal, and the frequency setting terminal is grounded via a setting resistor.
In one embodiment, the enable terminal includes a first enable terminal and a second enable terminal, the first enable terminal receives the first enable control signal through a first access resistor, the second enable terminal receives the second enable control signal through a second access resistor, and the second enable terminal is further grounded through a ground resistor.
An electronic device includes the memory power supply circuit according to any of the above embodiments.
In the memory power supply circuit, only one master control chip with higher integration level is used, and compared with the memory power supply circuit adopting two control chips, the whole wiring of the memory power supply circuit can be simplified, so that the Layout difficulty and the cost can be reduced, the time spent by an engineer during debug is reduced, and the research and development period is shortened; in addition, the whole wiring of the memory power supply circuit is simplified, the number of parts is reduced, the occupied space of a PCB is correspondingly small, and the cost can be controlled well; in addition, the wiring of the memory power supply circuit is concentrated, so that the working performance can be effectively exerted; in addition, the number and the types of the integral parts of the memory power supply circuit are reduced, so that the production in a factory is facilitated, the BOM material and the research and development cost can be saved, and the market competitive advantage is enhanced.
Furthermore, the memory power supply circuit has strong compatibility and universality, can be used as a standard reference line for mainboard DDR power supply, can be suitable for memories such as DDR3/DD3L and the like which do not need a VPP power supply module, and can be completed by only disconnecting the VPP power supply of a second input end in the circuit and removing related parts of VPP input and output.
Furthermore, the memory power supply circuit is widely applied and can be applied to various electronic devices, the memory power supply circuit is directly designed into various electronic device products, the circuit has universality and universality, and related devices in the circuit are common materials in the industry, so that the purchase is convenient.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic diagram of a first partial structure of a memory power supply circuit of an electronic device according to an embodiment of the invention.
Fig. 2 is a second partial structural schematic diagram of the memory power supply circuit of the electronic device shown in fig. 1.
Fig. 3 is a schematic structural diagram of a memory power supply circuit of an electronic device according to another embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below.
In order to make the technical solutions of the present invention better understood, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terms "first," "second," and "third," etc. in the description and claims of the present invention and the above-described drawings are used for distinguishing between different objects and not for describing a particular order. Furthermore, the terms "comprises" and any variations thereof, are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.
The electronic device according to the present invention may be a tablet Computer, a mobile phone, an electronic reader, a remote controller, a Personal Computer (PC), a notebook Computer, a vehicle-mounted device, a flat panel display, a flat panel television, a wearable device, or the like, and is not limited thereto.
With the continuous upgrade of DDR memories, the current stage of the memory design matched with DDR4 has become the mainstream of the design of the motherboard product, and the DDR4 memory power supply circuit generally outputs three groups of basic operating voltages, namely VDDQ (1.2V), VTT (0.6V) and VPP (2.5V), as shown in fig. 1 and fig. 2, please refer to fig. 1, and fig. 1 is a schematic diagram of a first part of a structure of a memory power supply circuit 10 of an electronic device according to an embodiment of the present invention. Fig. 2 is a second partial structural schematic diagram of the memory power supply circuit 10 of the electronic device shown in fig. 1. The memory power supply circuit 10 includes a first control chip 11 and a second control chip 12.
The first control chip 11 includes a power source terminal VIN, a driving terminal 3V3, an enable terminal EN2, a first output terminal SW, a second input terminal VDDQ, a second output terminal VTT, and the like. The power source terminal VIN is configured to receive a 12V input signal, the driving terminal 3V3 is configured to receive a 3.3V working voltage, the enable terminal EN2 is configured to receive an enable control signal, the first output terminal SW is configured to output a first output voltage VDDQ of 1.2V obtained by converting the input signal by the first control chip 11, the second input terminal VDDQ is configured to receive the first output voltage VDDQ, and the second output terminal VTT is configured to output a second output voltage VTT of 0.6V obtained by converting the first output voltage VDDQ by the first control chip 11.
The second control chip 12 comprises a voltage input terminal PVIN1, a PVIN2, an enable terminal EN, and third output terminals LX1-LX 3. The voltage input terminals PVIN1 and PVIN2 are configured to receive an input voltage of 5V, and the third output terminals LX1 to LX3 are configured to output a third output signal VPP of 2.5V obtained by converting the input voltage of 5V by the second control chip 12.
It is understood that the memory power supply circuit 10 further has peripheral wiring of chips such as an input voltage stabilizing circuit, an output current stabilizing circuit, an output voltage stabilizing circuit, a feedback output circuit, and an auxiliary circuit at a self-boosting end, and is used for cooperating with the first control chip 11 and the second control chip 12, and will not be described in detail herein.
In the memory power supply circuit 10, the first output signal VDDQ (1.2V) and the second output signal VTT (0.6V) are both controlled and output by the first control chip 11, and the third output signal VPP (2.5V) is separately controlled and output by the second control chip 12, so that the first, second, and third output signals VDDQ (1.2V), VTT (0.6V) VPP (2.5V) require two control chips 11, 12 and related peripheral wiring line control, so that the memory power supply circuit 10 has dispersed and complex wiring, which may affect the performance of the DDR memory, and the memory power supply circuit 10 uses many components, which also results in large PCB space occupation, high BOM material consumption and research and development cost, no market competition, and needs to be further improved.
Referring to fig. 3, fig. 3 is a schematic structural diagram of a memory power supply circuit 30 of an electronic device according to another embodiment of the invention. The memory power supply circuit 30 includes a main control chip 31, a first power supply terminal 301, a second power supply terminal 302, a third power supply terminal 303, a feedback output line 32, an auxiliary line 33, an output voltage stabilizing line 34, a first input voltage stabilizing line 35, a second input voltage stabilizing line 36, a third input voltage stabilizing line 37, a first output voltage stabilizing line 38, a second output voltage stabilizing line 39, and a third output voltage stabilizing line 40.
The main control chip 31 includes a first input terminal VIN, a second input terminal VDDQ, a third input terminal VPPIN, an enable terminal EN1, EN2, a driving terminal 3V3, a self-boosting terminal BST, a feedback terminal FB, a frequency setting terminal MODE, a reference voltage output terminal VTTREF, a first output terminal SW, a second output terminal VTT, and a third output terminal VPP.
The enable terminals EN1 and EN2 are used for receiving enable signals to control the main control chip 11 to work normally. Specifically, the enable terminal EN1 receives a first enable control signal via a first access resistor 311, the enable terminal EN2 receives a second enable control signal via a second access resistor 312, and the enable terminal EN2 is also grounded via a ground resistor 313.
The driving end 3V3 is connected to the working voltage output end 304 through a third access resistor 313 for receiving a working voltage, which may be 3.3V. The drive terminal 3V3 is also grounded via the second input stabilizing circuit 36. The second input stabilizing circuit 36 may include at least one capacitor. The frequency setting terminal MODE is grounded via a setting resistor 314.
The first input terminal VIN is configured to receive an input signal, in this embodiment, the input signal is a dc voltage, such as 12V. Specifically, the first input terminal VIN may be connected to the supply voltage output terminal 305 to receive the input signal, and the first input terminal VIN may also be grounded via the first input voltage stabilizing circuit 35. The first input voltage regulation circuit 35 includes a chip multilayer ceramic capacitor 351 and a solid state capacitor 352.
The first output terminal SW is configured to output a first output signal obtained by converting the input signal by the main control chip 31, and the first output terminal SW is further connected to the first power supply terminal 301, so that the first power supply terminal 301 can output the first output signal, where the first output signal may be VDDQ voltage of 1.2V. The main control chip 31 is integrated with a MOSFET circuit therein, and cooperates with the self-boosting terminal BST, the auxiliary circuit 33, and the like to enable the first output terminal SW to output the first output signal.
Specifically, the first output terminal SW may be connected to the first power supply terminal 301 via the output current stabilization line 34. The output ballast line 34 includes an output inductor. The first power supply terminal 301 may also be grounded via the first output voltage stabilizing circuit 38. The first output voltage stabilizing circuit 38 includes a chip multilayer ceramic capacitor 381 and a solid capacitor 382.
The second input terminal VDDQ is also connected to the first supply terminal 301 to receive the first output signal. The second output terminal VTT is configured to output a second output signal obtained by converting the first output signal of the second input terminal VDDQ by the main control chip 31, where the second output signal may be a VTT voltage of 0.6V. The second output terminal VTT is further connected to the second power supply terminal 302, so that the second power supply terminal 302 can output the VTT voltage of 0.6V. The second output terminal VTT may also be grounded via the second output stabilizing circuit 39. The second output stabilizing circuit 39 includes at least one capacitor.
The third input terminal VPP may also be connected to a working voltage output terminal 304, and is configured to receive the working voltage, the third output terminal VPP is configured to output a third output signal obtained by converting the working voltage input by the third input terminal VPP by the main control chip 31, where the third output signal may be a VPP voltage of 2.5V, and the third output terminal VPP is further connected to the third power supply terminal 303, so that the third power supply terminal 303 may output the VPP voltage of 2.5V. The third input terminal VPPIN may also be grounded via the third input stabilizing circuit 37, and the third input stabilizing circuit 37 includes at least one capacitor. The third output port VPP may also be grounded via the third output voltage stabilizing circuit 40, and the third output voltage stabilizing circuit 40 includes at least one capacitor.
The self-boosting terminal BST is connected to the first output terminal SW through the auxiliary line 33, the auxiliary line 33 includes an auxiliary resistor 331 and an auxiliary capacitor 332 connected in series, and the feedback terminal FB is connected to the first power supply terminal 301 through the feedback output line 32.
The feedback output circuit 32 includes a first voltage dividing resistor 321, a second voltage dividing resistor 322, a third voltage dividing resistor 323, and a capacitor 324, the first power supply terminal 301 is sequentially grounded via the first voltage dividing resistor 321, the second voltage dividing resistor 322, and the third voltage dividing resistor 323, the feedback terminal FB is connected to a node between the second voltage dividing resistor 322 and the third voltage dividing resistor 323, and the capacitor 324 is connected to a node between the first power supply terminal 301 and the second voltage dividing resistor 322 and the third voltage dividing resistor 323.
When the memory power supply circuit 30 works, the main control chip 31 receives a 12V dc voltage input signal output by the power supply voltage output terminal 305 and a 3.3V working voltage output by the working voltage input terminal 304, the enable terminals EN1 and EN2 also receive enable signals to control the main control chip 11 to work normally, and the first output terminal SW outputs the 1.2V first output signal through a MOSFET circuit integrated in the main control chip 31 and by matching with the self-boosting terminal BST, the auxiliary circuit 33, and the like; the main control chip 11 further converts the first output signal of 1.2V received by the second input terminal VDDQ into a second output signal of 0.6V and outputs the second output signal through the second output terminal VTT; the main control chip 11 further converts the 3.3V working voltage received by the third voltage input end VPPIN into a 2.5V third output signal and outputs the third output signal through the third output end VPP, so that the first power supply end 301, the second power supply end 302, and the third power supply end 303 respectively output a 1.2V first output signal, a 0.6V second output signal, and a 2.5V third output signal.
The feedback output line 32 further detects a signal of the first power supply terminal 301 and feeds the signal back to the main control chip 31, so that the main control chip 31 adjusts the signal of the first output terminal SW to adjust the signal of the first power supply terminal 301. In addition, it can be understood that the signal voltage of the first power supply terminal 301 can be set by setting the resistance values of the first voltage-dividing resistor 321, the second voltage-dividing resistor 322 and the third voltage-dividing resistor 323 of the feedback output line 325; the first to third input voltage stabilization lines 35, 36, 37 and the first to third output voltage stabilization lines 38, 39, 40 are used for voltage stabilization; the output ballast circuit 34 is for ballast.
As can be seen from the above, in the memory power supply circuit 30, only one master control chip 31 with a higher integration level is used, compared with the memory power supply circuit 10 using two control chips, the overall wiring of the memory power supply circuit 30 can be simplified, so that the Layout difficulty and the cost can be reduced, the time spent by an engineer during debug is reduced, and the development cycle is shortened; in addition, as the whole wiring of the memory power supply circuit 30 is simplified and the number of parts is reduced, the occupied space of the PCB is correspondingly reduced, and the cost can be better controlled; in addition, the memory power supply circuit 30 is more centralized in wiring, so that the working performance can be effectively exerted; moreover, the number and types of the whole parts of the memory power supply circuit 30 are reduced, so that the factory production is facilitated, the BOM material and the research and development cost can be saved, and the market competitive advantage is enhanced.
Further, the memory power supply circuit 30 has strong compatibility and universality, can be used as a standard reference line for motherboard DDR power supply, can be applied to memories such as DDR3/DD3L which do not need a VPP power supply module, and can be completed by only disconnecting the VPP power supply of the second input terminal in the line and removing related parts of VPP input and output.
Furthermore, the memory power supply circuit 30 is widely applied and can be applied to various electronic devices, and the memory power supply circuit 30 is directly designed into various electronic device products, the circuit thereof has universality and universality, and related devices in the circuit are common materials in the industry, so that the purchase is convenient.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (9)
1. A memory power supply circuit, characterized by: the memory power supply circuit comprises a main control chip, a first power supply end, a second power supply end and a third power supply end, wherein the main control chip comprises a first input end, a second input end, a third input end, an enable end, a drive end, a first output end, a second output end and a third output end, the enable end is used for receiving an enable signal to control the main control chip to normally work, the drive end is used for receiving a 3.3V working voltage, the first input end is used for receiving a 12V input signal, the first output end is used for outputting a 1.2V first output signal obtained by converting the input signal by the main control chip, the first output end is further connected to the first power supply end, the second input end is further connected to the first power supply end to receive the first output signal, the second output end is used for outputting a 0.6V second output signal obtained by converting the first output signal of the second input end by the main control chip, the second output end is further connected to the second power supply end, the third input end is also used for receiving the working voltage, the third output end is used for outputting a 2.5V third output signal which is obtained by converting the working voltage and is input by the third input end through the main control chip, the third output end is further connected to the third power supply end, the main control chip further comprises a second reference voltage output end, the first power supply end is a 1.2V VDDQ voltage output end, the second power supply end is a 0.6V VTT voltage output end, the third power supply end is a 2.5V VPP voltage output end, and the second reference voltage output end is a VTT reference voltage output end.
2. The memory power supply circuit of claim 1, wherein: the main control chip further comprises a self-boosting end and a feedback end, the self-boosting end is connected to the first output end through the auxiliary line, the auxiliary line comprises an auxiliary resistor and an auxiliary capacitor which are connected in series, and the feedback end is connected to the first power supply end through the feedback output line.
3. The memory power supply circuit of claim 2, wherein: the memory power supply circuit further comprises an output current stabilizing circuit, the first output end is connected with the first power supply end through the output current stabilizing circuit, and the output current stabilizing circuit comprises an output inductor.
4. A memory power supply circuit as claimed in claim 3, wherein: the feedback output circuit comprises a first voltage-dividing resistor, a second voltage-dividing resistor, a third voltage-dividing resistor and a capacitor, the first power supply end is grounded through the first voltage-dividing resistor, the second voltage-dividing resistor and the third voltage-dividing resistor in sequence, the feedback end is connected with a node between the second voltage-dividing resistor and the third voltage-dividing resistor, and the capacitor is connected between the first power supply end and a node between the second voltage-dividing resistor and the third voltage-dividing resistor.
5. The memory power supply circuit of claim 1, wherein: the memory power supply circuit further comprises a first input voltage stabilizing circuit, a second input voltage stabilizing circuit and a third input voltage stabilizing circuit, the first input end is grounded through the first input voltage stabilizing circuit, the driving end is grounded through the second input voltage stabilizing circuit, the third input end is grounded through the third input voltage stabilizing circuit, the first input voltage stabilizing circuit and the third input voltage stabilizing circuit comprise a chip type multilayer ceramic capacitor and a solid capacitor, and the second input voltage stabilizing circuit and the third input voltage stabilizing circuit comprise at least one capacitor.
6. The memory power supply circuit of claim 1, wherein: the memory power supply circuit further comprises a first output voltage stabilizing circuit, a second output voltage stabilizing circuit and a third output voltage stabilizing circuit, wherein the first output end is grounded through the first output voltage stabilizing circuit, the second output end is grounded through the second output voltage stabilizing circuit, the third output end is grounded through the third output voltage stabilizing circuit, the first output voltage stabilizing circuit comprises a chip type multilayer ceramic capacitor and a solid-state capacitor, the second output voltage stabilizing circuit comprises a chip type multilayer ceramic capacitor, and the third output voltage stabilizing circuit comprises at least one capacitor.
7. The memory power supply circuit of claim 1, wherein: the main control chip further comprises a frequency setting end, and the frequency setting end is grounded through a setting resistor.
8. The memory power supply circuit of claim 1, wherein: the enabling end comprises a first enabling end and a second enabling end, the first enabling end receives a first enabling control signal through a first access resistor, the second enabling end receives a second enabling control signal through a second access resistor, and the second enabling end is grounded through a grounding resistor.
9. An electronic device, characterized in that: the electronic device comprising a memory power supply circuit as claimed in any one of claims 1 to 8.
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| CN201911213096.9A CN110658902A (en) | 2019-12-02 | 2019-12-02 | Memory power supply circuit and electronic device |
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| CN201911213096.9A CN110658902A (en) | 2019-12-02 | 2019-12-02 | Memory power supply circuit and electronic device |
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Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106406483A (en) * | 2016-08-24 | 2017-02-15 | 柳州鹏达科技有限责任公司 | Power supply circuit of DDR memory |
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Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106406483A (en) * | 2016-08-24 | 2017-02-15 | 柳州鹏达科技有限责任公司 | Power supply circuit of DDR memory |
Non-Patent Citations (1)
| Title |
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| TEXAS INSTRUMENTS INCORPORATED: "《TPS65295 complete DDR4 memory power solution datasheet》", 22 February 2019, HTTP://WWW.TI.COM/LIT/GPN/TPS65295 * |
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Application publication date: 20200107 |