CN110649916A - Drive circuit of controlled NMOS tube - Google Patents
Drive circuit of controlled NMOS tube Download PDFInfo
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- CN110649916A CN110649916A CN201910966088.5A CN201910966088A CN110649916A CN 110649916 A CN110649916 A CN 110649916A CN 201910966088 A CN201910966088 A CN 201910966088A CN 110649916 A CN110649916 A CN 110649916A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
- H03K17/08104—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit in field-effect transistor switches
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/081—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit
- H03K17/08112—Modifications for protecting switching circuit against overcurrent or overvoltage without feedback from the output circuit to the control circuit in bipolar transistor switches
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/60—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being bipolar transistors
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
Abstract
The present invention relates to the field of drive circuits. The invention discloses a drive circuit of a controlled NMOS (N-channel metal oxide semiconductor) transistor, which comprises an upper pull tube M3, a lower pull tube M0, a lower pull resistor, a control logic circuit and a first switch circuit, wherein the output end SRG of the drive circuit is connected with a power VIN (neutral ground) through the upper pull tube M3, and is grounded through the lower pull tube M0 and the lower pull resistor which are connected in parallel, the control ends of the upper pull tube M3 and the lower pull tube M0 are connected with the control output end of the control logic circuit, the first switch circuit is connected between the output end SRG of the drive circuit and the control end of the lower pull tube M0, and the first switch circuit is configured to be switched on when the voltage of the power VIN is less than the working voltage of the drive circuit, and the voltage of the output end SRG of the drive circuit is greater than the switching-on voltage of the first switch; when the voltage of the power source VIN is greater than or equal to the operating voltage of the driving circuit, the first switching circuit is turned off. The invention can avoid the error conduction of the controlled NMOS tube when the power supply voltage of the driving circuit is very low, thereby improving the safety and the reliability.
Description
Technical Field
The invention belongs to the field of drive circuits, and particularly relates to a drive circuit of a controlled NMOS (N-channel metal oxide semiconductor) tube.
Background
The flyback converter is a commonly used ac-to-dc converter, and a typical circuit structure thereof is shown in fig. 1, and includes a primary control circuit and a secondary synchronous rectification circuit, where the synchronous rectification circuit includes a synchronous rectifier SR and a synchronous rectification controller for driving the synchronous rectifier SR. The conventional synchronous rectification controller mainly includes an internal linear regulator and a required external voltage-stabilizing capacitor C0, a pull-up PMOS transistor M3, a pull-down NMOS transistor M0, and a passive pull-down resistor R0, as shown in fig. 2.
The circuit design of the traditional synchronous rectification controller has the following defects of 2:
the first disadvantage is that: in the starting stage of the flyback converter, because the power supply VIN of the synchronous rectification controller is very low, the whole synchronous rectification controller cannot work normally, and the output end SRG of the synchronous rectification controller is only pulled down to the ground by the internal pull-down resistor R0. Because the flyback converter is in the working process, the SEC is a signal of a violent switch, the voltage of the output end SRG can be raised through the parasitic capacitance coupling of the synchronous rectifier SR (NMOS transistor), although the internal pull-down resistor R0 pulls down the voltage of the output end SRG in the starting process, the resistance value of the pull-down resistor R0 is not too low in consideration of the influence of power consumption and area in the practical design, so that the pull-down capability of the pull-down resistor R0 is not enough in the starting stage of the flyback converter, and the coupling voltage still exceeds the starting voltage of the synchronous rectifier SR, so that the primary switch and the secondary synchronous rectifier SR are simultaneously opened to cause transformer inductance saturation, thereby burning the transformer and the primary switch tube.
The second disadvantage is that: because the VGS voltage of the normal switching-on of the external synchronous rectifier SR is about 0 to 12V, and the output voltage of the flyback converter can be greater than 12V, for ensuring that the voltage of the switch does not exceed the withstand voltage of the synchronous rectifier SR, a linear voltage stabilizer internally integrated is required to limit the highest voltage output by the output end SRG, the linear voltage stabilizer not only has a larger circuit occupation area, but also needs the cooperation of an external voltage stabilizing capacitor C0 to normally work, therefore, a chip pin is required to be added and an external capacitor C0 is added, thereby leading to the large circuit occupation area and high cost.
Disclosure of Invention
It is an object of the present invention to provide a driving circuit for a controlled NMOS transistor to solve the above-mentioned first drawback.
It is another object of the present invention to provide a driving circuit for a controlled NMOS transistor to solve the above-mentioned second drawback.
In order to achieve the purpose, the invention adopts the technical scheme that: a drive circuit of a controlled NMOS transistor comprises a pull-up transistor M3, a pull-down transistor M0, a control logic circuit and a first switch circuit, wherein an output end SRG of the drive circuit is connected with a power supply VIN through a pull-up transistor M3, and is grounded through a pull-down transistor M0, control ends of the pull-up transistor M3 and the pull-down transistor M0 are connected with the control output end of the control logic circuit, the first switch circuit is connected between the output end SRG of the drive circuit and the control end of the pull-down transistor M0, and the first switch circuit is configured to be switched on when the voltage of the power supply VIN is smaller than the working voltage of the drive circuit and the voltage of the output end SRG of the drive circuit is larger than the switching-on voltage of the first switch circuit; when the voltage of the power supply VIN is greater than or equal to the working voltage of the driving circuit, the first switching circuit is turned off.
Further, the first switch circuit includes a PMOS transistor M5, a PMOS transistor M6, a diode D0, and a resistor R1, a drain of the PMOS transistor M5 is connected to the output SRG of the driving circuit, a source of the PMOS transistor M5 is connected to a source of the PMOS transistor M6, a drain of the PMOS transistor M6 is connected to the control terminal of the pull-down transistor M0, the resistor R1 is connected in parallel to the PMOS transistor M5, a positive terminal of the diode D0 is connected to the gate of the PMOS transistor M5, a negative terminal of the diode D0 is connected to the source of the PMOS transistor M5, gates of the PMOS transistor M5 and the PMOS transistor M6 are connected to a first control voltage, and the first control voltage is configured to be zero when the voltage of the power supply VIN is smaller than the operating voltage of the driving circuit; when the voltage of the power source VIN is greater than or equal to the operating voltage of the driving circuit, the first control voltage VPRE is greater than or equal to the voltage of the output terminal SRG.
Further, the driving circuit further comprises a second switch circuit, the second switch circuit is connected between the control terminal of the pull-down tube M0 and the control output terminal of the control logic circuit, and the second switch circuit is configured to be turned off when the voltage of the power supply VIN is less than the operating voltage of the driving circuit; when the voltage of the power source VIN is greater than or equal to the operating voltage of the driving circuit, the second switch circuit is turned on.
Furthermore, the second switch circuit is implemented by using an NMOS transistor M4, a drain of the NMOS transistor M4 is connected to the control output terminal of the control logic circuit, a source of the NMOS transistor M4 is connected to the control terminal of the pull-down transistor M0, a gate of the NMOS transistor M4 is connected to a first logic level SREN, and the first logic level SREN is configured to be 0 when the voltage of the power supply VIN is less than the operating voltage of the driving circuit; when the voltage of the power source VIN is greater than or equal to the operating voltage of the driving circuit, the first logic level SREN is 1.
Further, the pull-up transistor M8 and the third switch circuit are included, the N-type transistor M8 is connected in parallel with the pull-up transistor M3, a control electrode of the pull-up transistor M3 is connected to a first control output end of the control logic circuit through a first level shift circuit, a power supply input end of the first level shift circuit is connected to the power supply VIN, a control electrode of the N-type transistor M8 is connected to a first control output end of the control logic circuit through a second level shift circuit, a power supply input end of the second level shift circuit is connected to a voltage VPRE, the voltage VPRE is configured to be equal to the withstand voltage of the controlled NMOS transistor when the voltage VIN of the power supply VIN is greater than or equal to the withstand voltage of the controlled NMOS transistor, and the third switch circuit is configured to control the pull-up transistor M3 to be turned off when the voltage of the power supply VIN is greater than the withstand voltage of the controlled NMOS transistor.
Furthermore, the N-type transistor M8 is an NMOS transistor.
The voltage stabilizing circuit is characterized by further comprising a voltage stabilizing circuit, wherein the input end of the voltage stabilizing circuit is connected with a power supply VIN, the output end of the voltage stabilizing circuit outputs a voltage VPRE, and the voltage stabilizing value of the voltage stabilizing circuit is the withstand voltage of the controlled NMOS tube.
Furthermore, the voltage stabilizing circuit comprises a PMOS tube M10, a PMOS tube M11, an NMOS tube M9, a voltage regulator tube zener1, a voltage regulator tube zener2, a voltage regulator tube zener3, a resistor R2 and a resistor R3, wherein the source electrode of the PMOS tube M11 is connected with a power supply VIN, the drain electrode of the PMOS tube M11 is sequentially connected with the voltage regulator tube zener1, the voltage regulator tube zener2 and the voltage regulator tube zener3 in series and is grounded, the resistor R3 is connected with the voltage regulator tube zener1, the voltage regulator tube zener2 and the voltage regulator tube zener3 in series and is connected with the power supply VIN in series, the drain electrode of the PMOS tube M10 is respectively connected with the gate electrode of the PMOS tube M10, the gate electrode of the PMOS tube M10 and the drain electrode of the NMOS tube M10, the source electrode of the NMOS tube M10 is connected with the resistor R10 in series, the gate electrode of the NMOS tube M10 is connected with a first logic level SREN, and serves as an output end of the voltage stabilizing circuit.
Further, the third switch circuit comprises a PMOS transistor M7, the source of the PMOS transistor M7 is connected to the power supply VIN, the drain of the PMOS transistor M7 is connected to the control electrode of the pull-up transistor M3, the gate of the PMOS transistor M7 is connected to a second control voltage VIN _ OV, and the second control voltage VIN _ OV is configured to make the PMOS transistor M7 conductive when the voltage of the power supply VIN is greater than the withstand voltage of the controlled NMOS transistor; when the voltage of the power supply VIN is less than or equal to the withstand voltage of the controlled NMOS transistor, the second control voltage VIN _ OV turns off the PMOS transistor M7.
Further, the pull-down circuit also comprises a pull-down resistor R0, and the pull-down resistor R0 is connected with the pull-down tube M0 in parallel.
The invention has the beneficial technical effects that:
the invention can avoid the error conduction of the controlled NMOS tube when the power supply voltage of the driving circuit is very low, thereby improving the safety and the reliability.
The invention can avoid the burning of the controlled NMOS tube caused by the output voltage of the driving circuit exceeding the withstand voltage of the controlled NMOS tube, and does not need to use a linear voltage stabilizer, thereby not needing to increase a chip pin and an external capacitor C0, greatly reducing the occupied area of the circuit and reducing the driving cost of the chip.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic diagram of a typical circuit structure of a flyback converter;
FIG. 2 is a circuit diagram of a conventional synchronous rectification controller;
FIG. 3 is a circuit diagram of a first embodiment of the present invention;
FIG. 4 is a circuit diagram of a voltage regulator circuit according to a first embodiment of the present invention;
fig. 5 is a circuit diagram of a second embodiment of the invention.
Detailed Description
To further illustrate the various embodiments, the invention provides the accompanying drawings. The accompanying drawings, which are incorporated in and constitute a part of this disclosure, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the embodiments. Those skilled in the art will appreciate still other possible embodiments and advantages of the present invention with reference to these figures. Elements in the figures are not drawn to scale and like reference numerals are generally used to indicate like elements.
The invention will now be further described with reference to the accompanying drawings and detailed description.
Example one
As shown in fig. 3, a driving circuit of a controlled NMOS transistor includes a pull-up transistor M3, a pull-down transistor M0, a pull-down resistor R0, a control logic circuit 1, and a first switch circuit, where an output terminal SRG of the driving circuit is used for being connected to a gate of the controlled NMOS transistor SR to drive the controlled NMOS transistor SR.
The output end SRG of the driving circuit is connected with a power supply VIN through an upper pull tube M3, and is grounded through a lower pull tube M0 and a lower pull resistor R0 which are connected in parallel, the control end of the upper pull tube M3 is connected with a first control output end of a control logic circuit 1 through a first level switching circuit 2, the power supply input end of the first level switching circuit 2 is connected with the power supply VIN, the control end of the lower pull tube M0 is connected with a second control output end of the control logic circuit 1, the partial circuits are the same as the circuits of a traditional synchronous rectification controller, the specific structure and the driving principle can refer to the prior art, and the detailed description is omitted.
In this embodiment, the pull-up transistor M3 is preferably a PMOS transistor, and the pull-down transistor M0 is preferably an NMOS transistor, but not limited thereto, and in other embodiments, the pull-up transistor M3 may be implemented by another P-type transistor, and the pull-down transistor M0 may be implemented by another N-type transistor.
The first switch circuit is connected between the output terminal SRG of the driving circuit and the gate (control terminal) of the NMOS transistor M0, and is configured to be turned on when the voltage of the power supply VIN is less than the operating voltage UVLO of the driving circuit (i.e., the control logic circuit 1 cannot operate normally at this time), and the voltage of the output terminal SRG of the driving circuit is greater than the turn-on voltage of the first switch circuit; therefore, the voltage of the output end SRG is transmitted to the grid electrode of the NMOS tube M0, so that the NMOS tube M0 is opened, once the NMOS tube M0 is opened, the voltage of the output end SRG is rapidly pulled down due to the fact that the on-resistance of the NMOS tube M0 is small, the voltage of the output end SRG is limited, the external controlled NMOS tube SR cannot be opened before the voltage of the output end SRG reaches the working voltage UVLO, the controlled NMOS tube SR is prevented from being conducted mistakenly, and safety and reliability are improved.
When the voltage of the power supply VIN is greater than or equal to the operating voltage UVLO of the driving circuit, the first switching circuit is turned off, so that the normal operation of the NMOS transistor M0 is not affected.
In this embodiment, the first switch circuit includes a PMOS transistor M5, a PMOS transistor M6, a diode D0, and a resistor R1, a drain of the PMOS transistor M5 is connected to the output terminal SRG of the driving circuit, a source of the PMOS transistor M5 is connected to a source of the PMOS transistor M6, a drain of the PMOS transistor M6 is connected to a gate of the NMOS transistor M0, the resistor R1 is connected in parallel to the PMOS transistor M5, a positive terminal of the diode D0 is connected to the gate of the PMOS transistor M5, a negative terminal of the diode D0 is connected to the source of the PMOS transistor M5, gates of the PMOS transistor M5 and the PMOS transistor M6 are connected to a first control voltage, and the first control voltage is configured to be zero when a voltage of the power supply VIN is less than an operating voltage UVLO of the driving circuit; when the voltage of the power supply VIN is greater than or equal to the operating voltage UVLO of the driving circuit, the first control voltage is greater than or equal to the voltage of the output terminal SRG, and with the circuit structure, when the voltage of the output terminal SRG is very small, the NMOS transistor M0 may be turned on, so as to further improve the safety and reliability.
In this specific embodiment, the driving circuit further includes a second switch circuit, the second switch circuit is connected between the gate of the NMOS transistor M0 and the second control output terminal of the control logic circuit 1, and the second switch circuit is configured to turn off when the voltage of the power supply VIN is less than the operating voltage UVLO of the driving circuit; when the voltage of the power source VIN is greater than or equal to the operating voltage UVLO of the driving circuit, the second switch circuit is turned on. By arranging the second switch circuit, when the voltage of the power supply VIN is lower than the operating voltage UVLO of the driving circuit, the first switch circuit and the second control output end of the control logic circuit 1 are prevented from being influenced by each other, and reliability is improved.
In this embodiment, the second switch circuit is preferably implemented by using an NMOS transistor M4, a drain of the NMOS transistor M4 is connected to the second control output terminal of the control logic circuit 1, a source of the NMOS transistor M4 is connected to a gate of the NMOS transistor M0, a gate of the NMOS transistor M4 is connected to a first logic level SREN, and the first logic level SREN is configured to be 0 when a voltage of the power supply VIN is less than an operating voltage UVLO of the driver circuit; when the voltage of the power source VIN is greater than or equal to the operating voltage UVLO of the driving circuit, the first logic level SREN is 1. The first logic level SREN may be provided by a third control output terminal of the control logic circuit 1, when the voltage of the power supply VIN is less than the operating voltage UVLO of the driving circuit, the control logic circuit 1 cannot operate normally, and the output of the third control output terminal is 0; when the voltage of the source VIN is greater than or equal to the operating voltage UVLO of the driving circuit, the control logic circuit 1 operates normally, and the output of the third control output terminal is 1.
In this embodiment, the first control voltage is provided by a voltage regulator circuit, an input terminal of the voltage regulator circuit is connected to the power supply VIN, an output terminal of the voltage regulator circuit outputs a voltage VPRE as the first control voltage, and a regulated value of the voltage regulator circuit is a withstand voltage of the controlled NMOS transistor SR, which is set to 15V in this embodiment, but is not limited thereto.
Specifically, as shown in fig. 4, in this embodiment, the voltage regulator circuit includes a PMOS transistor M10, a PMOS transistor M11, an NMOS transistor M9, a regulator tube zener1, a regulator tube zener2, a regulator tube zener3, a resistor R2, and a resistor R3, the source electrode of the PMOS tube M11 is connected with a power supply VIN, the drain electrode of the PMOS tube M11 is connected with a voltage regulator tube zener1, a voltage regulator tube zener2 and a voltage regulator tube zener3 in series in sequence and is grounded, the resistor R3 is connected with a voltage regulator tube zener1, a voltage regulator tube zener2 and a voltage regulator tube zener3 which are connected in series in parallel, the source electrode of the PMOS tube M10 is connected with a power supply VIN, the drain electrode of the PMOS tube M10 is respectively connected with the grid electrode of the PMOS tube M11, the grid electrode of the PMOS tube M10 and the drain electrode of the NMOS tube M9, the source electrode series resistor R2 of the NMOS transistor M9 is grounded, the gate electrode of the NMOS transistor M9 is connected with a first logic level SREN, the node between the PMOS tube M11 and the Zener tube 1 is used as the output end of the voltage stabilizing circuit to output the voltage VPRE, the first control voltage is provided for the gates of the PMOS transistor M5 and the PMOS transistor M6. Of course, in other embodiments, other existing voltage stabilizing circuits may be used.
In this embodiment, the NMOS transistor M8 and the third switch circuit are further included, the NMOS transistor M8 is connected in parallel to the PMOS transistor M3, a gate of the PMOS transistor M3 is connected to the first control output terminal of the control logic circuit 1 through the first level shifter circuit 2, a power input terminal of the first level shifter circuit 2 is connected to the power supply VIN, a control electrode of the NMOS transistor M8 is connected to the first control output terminal of the control logic circuit 1 through the second level shifter circuit 3, a power input terminal of the second level shifter circuit 3 is connected to the voltage VPRE, that is, to the output terminal of the voltage regulator circuit, and the third switch circuit is configured to control the PMOS transistor M3 to turn off when the voltage of the power supply VIN is greater than the withstand voltage of the controlled NMOS transistor SR. The controlled NMOS tube SR burning caused by the fact that the output voltage of the driving circuit exceeds the withstand voltage of the controlled NMOS tube SR can be avoided, a simple voltage stabilizing circuit is adopted, a linear voltage stabilizer is not needed, a chip pin and an external capacitor C0 are not needed to be added, the occupied area of the circuit is greatly reduced, and the driving cost of the chip is reduced.
In this embodiment, the N-type transistor M8 is preferably an NMOS transistor with a small on-resistance, but is not limited thereto, and in other embodiments, other N-type transistors, such as an NPN transistor, may also be used.
In this embodiment, the third switch circuit includes a PMOS transistor M7, the source of the PMOS transistor M7 is connected to the power supply VIN, the drain of the PMOS transistor M7 is connected to the gate of the PMOS transistor M3, the gate of the PMOS transistor M7 is connected to the second control voltage VIN _ OV, the second control voltage VIN _ OV is configured to be 15V in this embodiment when the voltage of the power supply VIN is greater than the withstand voltage of the controlled NMOS transistor SR, and the second control voltage VIN _ OV turns on the PMOS transistor M7; when the voltage of the power source VIN is less than or equal to the withstand voltage of the controlled NMOS transistor SR, the second control voltage VIN _ OV turns off the PMOS transistor M7. Of course, in other embodiments, the third switch circuit may be implemented by using other existing circuit structures.
When the voltage of the power supply VIN reaches the operating voltage UVLO of the driving circuit, the first logic level SREN is 1, the NMOS transistor M4 is turned on, the PMOS transistor M10, the PMOS transistor M11, and the NMOS transistor M9 are turned on, the voltage regulator circuit outputs a voltage VPRE, the voltage VPRE is min (VIN, 15V), the PMOS transistor M5 and the PMOS transistor M6 are turned off, and the NMOS transistor M0 is controlled by the control logic circuit 1 and can normally operate; when the voltage of the power supply VIN is less than the operating voltage UVLO of the driving circuit, the first logic level SREN is 0, the NMOS transistor M4 is turned off, the PMOS transistor M10, the PMOS transistor M11, and the NMOS transistor M9 are turned off, the output of the voltage stabilizing circuit is 0, when the voltage of the output SRG is greater than the on-state voltage of the PMOS transistor M6, the PMOS transistor M5 and the PMOS transistor M6 are turned on, so that the voltage of the output SRG is transmitted to the gate of the NMOS transistor M0 to turn on the NMOS transistor M0, once the NMOS transistor M0 is turned on, since the on-resistance of the NMOS transistor M0 is small, the voltage of the output SRG is rapidly pulled down to limit the voltage of the output SRG from not turning on the external synchronous rectifier SR before the voltage of the power supply VIN reaches the UVLO, thereby preventing the transformer inductance saturation caused by the simultaneous turning on of the switch on of the primary side of the flyback converter and the synchronous rectifier SR of the secondary side to burn the.
When the power supply voltage VIN exceeds 15V (the withstand voltage of the synchronous rectifier SR), the PMOS transistor M7 turns off the PMOS transistor M3, the NMOS transistor M8 is turned on as a pull-up transistor, and at this time, the voltage of the output terminal SRG is the voltage VPRE-VGS, where VGS is VGS of the NMOS transistor M8 and does not exceed the withstand voltage of the synchronous rectifier SR; when the supply voltage VIN is greater than the operating voltage UVLO of the driving circuit and less than 15V, the PMOS transistor M3 and the NMOS transistor M8 are both turned on and collectively serve as pull-up transistors, and at this time, the voltage of the output terminal SRG is the voltage of the supply voltage VIN and does not exceed the withstand voltage of the synchronous rectifier SR. Therefore, the VGS withstand voltage requirement of the synchronous rectifier SR is met, a linear voltage regulator is not needed, a chip pin and an external capacitor C0 are not needed to be added, the occupied area of a circuit is greatly reduced, and the driving cost of the chip is reduced.
Example two
As shown in fig. 5, the present embodiment is different from the first embodiment in that: in this embodiment, the first switch circuit is implemented by using a PNP transistor M5, an emitter of the PNP transistor M5 is connected to the output terminal SRG of the driving circuit, a collector of the PNP transistor M5 is connected to a gate of the NMOS transistor M0, and a base of the PNP transistor M5 is connected to the first control voltage VPRE.
In this embodiment, the second switch circuit is implemented by using an NPN transistor M4, a collector of the NPN transistor M4 is connected to the second control output terminal of the control logic circuit 1, an emitter of the NPN transistor M4 is connected to the gate of the NMOS transistor M0, and a base of the NPN transistor M4 is connected to the first logic level SREN.
The circuit can also be used for other types of driving circuits, is not limited to synchronous rectification driving circuits, and can be used in the scene that external MOS is required to be prevented from being turned on when not required.
While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A drive circuit of a controlled NMOS transistor comprises a pull-up transistor M3, a pull-down transistor M0 and a control logic circuit, and is characterized in that: the output end SRG of the driving circuit is connected with a power supply VIN through an upper pull tube M3 and is grounded through a lower pull tube M0, the control ends of the upper pull tube M3 and the lower pull tube M0 are connected with the control output end of the control logic circuit, the first switch circuit is connected between the output end SRG of the driving circuit and the control end of the lower pull tube M0, and the first switch circuit is configured to be switched on when the voltage of the power supply VIN is smaller than the working voltage of the driving circuit and the voltage of the output end SRG of the driving circuit is larger than the switching-on voltage of the first switch circuit; when the voltage of the power supply VIN is greater than or equal to the working voltage of the driving circuit, the first switching circuit is turned off.
2. The driving circuit of the controlled NMOS transistor of claim 1, wherein: the first switch circuit comprises a PMOS tube M5, a PMOS tube M6, a diode D0 and a resistor R1, wherein the drain of the PMOS tube M5 is connected with the output end SRG of the drive circuit, the source of the PMOS tube M5 is connected with the source of a PMOS tube M6, the drain of the PMOS tube M6 is connected with the control end of a pull-down tube M0, the resistor R1 is connected with the PMOS tube M5 in parallel, the positive end of the diode D0 is connected with the gate of the PMOS tube M5, the negative end of the diode D0 is connected with the source of the PMOS tube M5, the gates of the PMOS tube M5 and the PMOS tube M6 are connected with a first control voltage VIN, and the first control voltage is configured to be zero when the voltage of a power supply is smaller than the working voltage of the drive circuit; when the voltage of the power source VIN is greater than or equal to the operating voltage of the driving circuit, the first control voltage VPRE is greater than or equal to the voltage of the output terminal SRG.
3. The driving circuit of the controlled NMOS transistor according to claim 1 or 2, wherein: the control circuit further comprises a second switch circuit, wherein the second switch circuit is connected between the control end of the pull-down tube M0 and the control output end of the control logic circuit, and is configured to be turned off when the voltage of the power supply VIN is less than the working voltage of the driving circuit; when the voltage of the power source VIN is greater than or equal to the operating voltage of the driving circuit, the second switch circuit is turned on.
4. The driving circuit of the controlled NMOS transistor of claim 3, wherein: the second switch circuit is implemented by using an NMOS transistor M4, a drain of the NMOS transistor M4 is connected to a control output terminal of the control logic circuit, a source of the NMOS transistor M4 is connected to a control terminal of the pull-down transistor M0, a gate of the NMOS transistor M4 is connected to a first logic level SREN, and the first logic level SREN is configured to be 0 when the voltage of the power supply VIN is less than the working voltage of the driving circuit; when the voltage of the power source VIN is greater than or equal to the operating voltage of the driving circuit, the first logic level SREN is 1.
5. The driving circuit of the controlled NMOS transistor of claim 1, wherein: the transistor-resistor converter further comprises an N-type transistor M8 and a third switching circuit, wherein the N-type transistor M8 is connected in parallel with the pull-up transistor M3, the control electrode of the pull-up transistor M3 is connected with the first control output end of the control logic circuit through a first level conversion circuit, the power supply input end of the first level conversion circuit is connected with the power supply VIN, the control electrode of the N-type transistor M8 is connected with the first control output end of the control logic circuit through a second level conversion circuit, the power supply input end of the second level conversion circuit is connected with a voltage VPRE, the voltage VPRE is configured to be equal to the withstand voltage of the controlled NMOS transistor when the voltage of the power supply VIN is greater than or equal to the withstand voltage of the controlled NMOS transistor, and the third switching circuit is configured to control the pull-up transistor M3 to be turned off when the voltage of the power supply VIN is greater than the.
6. The driving circuit of the controlled NMOS transistor of claim 5, wherein: the N-type transistor M8 is an NMOS transistor.
7. The driving circuit of the controlled NMOS transistor of claim 5, wherein: the voltage stabilizing circuit is characterized by further comprising a voltage stabilizing circuit, wherein the input end of the voltage stabilizing circuit is connected with a power supply VIN, the output end of the voltage stabilizing circuit outputs a voltage VPRE, and the voltage stabilizing value of the voltage stabilizing circuit is the withstand voltage of the controlled NMOS tube.
8. The driving circuit of the controlled NMOS transistor of claim 7, wherein: the voltage stabilizing circuit comprises a PMOS tube M10, a PMOS tube M11, an NMOS tube M9, a voltage regulator tube zener1, a voltage regulator tube zener2, a voltage regulator tube zener3, a resistor R2 and a resistor R3, wherein the source electrode of the PMOS tube M11 is connected with a power supply VIN, the drain electrode of the PMOS tube M11 is sequentially connected with a voltage regulator tube zener1, a voltage regulator tube zener2 and a voltage regulator tube zener3 in series to be grounded, the resistor R3 is connected with a voltage regulator tube zener1, a voltage regulator tube zener2 and a voltage regulator tube zener3 which are connected in series to be grounded, the source electrode of the PMOS tube M10 is connected with the power supply VIN, the drain electrode of the PMOS tube M10 is respectively connected with the grid electrode of the PMOS tube M10, the grid electrode of the PMOS tube M10 and the drain electrode of the NMOS tube M10 are used as the output end of the voltage stabilizing circuit.
9. The driving circuit of the controlled NMOS transistor of claim 5, wherein: the third switching circuit comprises a PMOS tube M7, the source electrode of the PMOS tube M7 is connected with a power supply VIN, the drain electrode of the PMOS tube M7 is connected with the control electrode of the pull-up tube M3, the grid electrode of the PMOS tube M7 is connected with a second control voltage VIN _ OV, and the second control voltage VIN _ OV is configured to enable the PMOS tube M7 to be conducted when the voltage of the power supply VIN is greater than the withstand voltage of the controlled NMOS tube; when the voltage of the power supply VIN is less than or equal to the withstand voltage of the controlled NMOS transistor, the second control voltage VIN _ OV turns off the PMOS transistor M7.
10. The driving circuit of the controlled NMOS transistor of claim 1, wherein: the pull-down circuit further comprises a pull-down resistor R0, and the pull-down resistor R0 is connected with the pull-down tube M0 in parallel.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910966088.5A CN110649916A (en) | 2019-10-12 | 2019-10-12 | Drive circuit of controlled NMOS tube |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910966088.5A CN110649916A (en) | 2019-10-12 | 2019-10-12 | Drive circuit of controlled NMOS tube |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113346893A (en) * | 2020-12-24 | 2021-09-03 | 澜起电子科技(昆山)有限公司 | Drive output circuit, chip and drive output method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113346893A (en) * | 2020-12-24 | 2021-09-03 | 澜起电子科技(昆山)有限公司 | Drive output circuit, chip and drive output method |
| CN113346893B (en) * | 2020-12-24 | 2022-03-18 | 澜起电子科技(昆山)有限公司 | Drive output circuit, chip and drive output method |
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