CN110649027A - Method for forming semiconductor device - Google Patents
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- CN110649027A CN110649027A CN201910913688.5A CN201910913688A CN110649027A CN 110649027 A CN110649027 A CN 110649027A CN 201910913688 A CN201910913688 A CN 201910913688A CN 110649027 A CN110649027 A CN 110649027A
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
Abstract
The invention provides a method for forming a semiconductor device, which comprises the following steps: providing a substrate; sequentially forming a first dielectric layer, a floating gate layer, a second dielectric layer and a control gate layer on the substrate; sequentially etching the control gate layer, the second dielectric layer, the floating gate layer and the first dielectric layer to expose out of the surface of the substrate to form a plurality of square matrixes and a plurality of lead-out structures, wherein a plurality of lead-out structures are respectively arranged on two sides, which are not adjacent, of each square matrix; forming a plurality of rows of grid electrode structures on the square array to form a storage unit, wherein each grid electrode structure is provided with two ends, one end of each row of grid electrode structure is provided with a leading-out structure, and the leading-out structures of adjacent rows of grid electrode structures are positioned at different ends. After the memory cell is formed, the lead-out structures are positioned at different ends of adjacent columns, and the distance between the adjacent lead-out structures is increased, so that the requirement on the precision of a photoetching machine is reduced during etching, the etching can be finished by using the photoetching machine with lower precision, and the cost is reduced.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a forming method of a semiconductor device.
Background
The grid structure can be used as a storage unit, a plurality of storage units can form one storage unit, the storage unit is divided into a plurality of rows and columns of grid structures, the control grids of the storage units on the same column are connected to one line through the leading-out structure, and the storage units on the column can be controlled through the line. In the prior art, before a gate structure is formed, a plurality of lead-out structures are formed by etching, then the gate structure is formed by etching, a storage unit is formed by the plurality of gate structures, the storage unit is divided into a plurality of rows of gate structures, each row is provided with one lead-out structure, and the plurality of lead-out structures are positioned at the same end of each row. In the prior art, a method for forming a lead-out structure includes forming a plurality of independent lead-out structures by etching and separating a control gate layer through a photoresist mask and using a photoetching machine after the control gate layer is formed. However, as the size of the semiconductor device is gradually reduced, the distance between adjacent lead-out structures is also gradually reduced, so that the etching by using a high-precision photoetching machine is required, and the cost is required to be higher.
Disclosure of Invention
The invention aims to provide a method for forming a semiconductor device, which can form a lead-out structure by using a photoetching machine with lower precision and save cost.
In order to achieve the above object, the present invention provides a method of forming a semiconductor device, comprising:
providing a substrate;
sequentially forming a first dielectric layer, a floating gate layer, a second dielectric layer and a control gate layer on the substrate;
sequentially etching the control gate layer, the second dielectric layer, the floating gate layer and the first dielectric layer to expose out of the surface of the substrate to form a plurality of square matrixes and a plurality of lead-out structures, wherein a plurality of lead-out structures are respectively arranged on two sides, which are not adjacent, of each square matrix;
forming a plurality of rows of grid structures on the square array to form a storage unit, wherein each grid structure is provided with two ends, one end of each row of grid structure is provided with a leading-out structure, and the leading-out structures of adjacent rows of grid structures are positioned at different ends.
Optionally, in the method for forming a semiconductor device, the number of the square matrixes is two, the two square matrixes are a first square matrix and a second square matrix, and a certain distance is provided between the first square matrix and the second square matrix.
Optionally, in the method for forming a semiconductor device, the lead-out structure is square.
Optionally, in the method for forming a semiconductor device, the first square matrix and the second square matrix have a plurality of sides, respectively, and the plurality of lead-out structures are distributed on two opposite sides of the first square matrix and the second square matrix.
Optionally, in the method for forming a semiconductor device, the number of the lead-out structures is 8, and the lead-out structures are respectively a first lead-out structure, a second lead-out structure, a third lead-out structure, a fourth lead-out structure, a fifth lead-out structure, a sixth lead-out structure, a seventh lead-out structure and an eighth lead-out structure, where the first lead-out structure and the second lead-out structure are located on a first side of the first square matrix, the third lead-out structure and the fourth lead-out structure are located on a second side of the first square matrix, and the first side and the second side are opposite; the fifth leading-out structure and the sixth leading-out structure are located on a third edge of the second square matrix, the seventh leading-out structure and the eighth leading-out structure are located on a fourth edge of the second square matrix, the third edge is opposite to the fourth edge, and the second edge is opposite to the third edge.
Optionally, in the method for forming a semiconductor device, the lead-out structure of the second side and the lead-out structure of the third side are arranged in a crossing manner.
Optionally, in the method for forming the semiconductor device, a distance between the adjacent extraction structures is greater than or equal to 0.36 micrometers.
Optionally, in the forming method of the semiconductor device, the memory unit includes a first column of gate structures and a second column of gate structures, the first column of gate structures and the second column of gate structures are adjacent to each other, each of the first column of gate structures and the second column of gate structures has a first end and a second end, the first lead-out structure is located at the first end of the first column of gate structures, and the third lead-out structure is located at the second end of the second column of gate structures.
Optionally, in the method for forming a semiconductor device, the method for forming a gate structure by etching includes: and etching the control gate layer, the second dielectric layer, the floating gate layer and the first dielectric layer in sequence to expose the surface of the substrate to form a control gate, a second dielectric, a floating gate and a first dielectric of a gate structure, and then forming a word line between the control gate and the floating gate and a third dielectric between the word line and the control gate and the floating gate.
Optionally, in the method for forming the semiconductor device, the lead-out structure is connected to the control gate.
In the method for forming the semiconductor device, the lead-out structures are positioned at different ends of adjacent columns after the memory cells are formed, and the distance between the adjacent lead-out structures is increased, so that the requirement on the precision of a photoetching machine is reduced during etching, the etching can be finished by using the photoetching machine with lower precision, and the cost is reduced.
Drawings
Fig. 1 is a flow chart of a method of forming a semiconductor device of an embodiment of the present invention;
fig. 2 is a schematic cross-sectional view of a method of forming a semiconductor device according to an embodiment of the present invention;
fig. 3 and 4 are top views of a method of forming a semiconductor device according to an embodiment of the present invention;
in the figure: 110-substrate, 120-first dielectric layer, 130-floating gate layer, 140-second dielectric layer, 150-control gate layer, 161-first square matrix, 161A-first column gate structure, 161B-second column gate structure, 161C-third column gate structure, 161D-fourth column gate structure, 162-second square matrix, 171-first leading-out structure, 172-second leading-out structure, 173-third leading-out structure, 174-fourth leading-out structure, 175-fifth leading-out structure, 176-sixth leading-out structure, 177-seventh leading-out structure and 178-eighth leading-out structure.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. Advantages and features of the present invention will become apparent from the following description and claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Referring to fig. 1, the present invention provides a method of forming a semiconductor device, including:
s11: providing a substrate;
s12: sequentially forming a first dielectric layer, a floating gate layer, a second dielectric layer and a control gate layer on the substrate;
s13: sequentially etching the control gate layer, the second dielectric layer, the floating gate layer and the first dielectric layer to expose out of the surface of the substrate to form a plurality of square matrixes and a plurality of lead-out structures, wherein a plurality of lead-out structures are respectively arranged on two sides (two sides which are not adjacent on the cross section of each square matrix) which are not adjacent on each square matrix;
s14: and forming a plurality of rows of grid electrode structures on the square array to form a storage unit, wherein one end of each row of grid electrode structures is provided with a lead-out structure, and the lead-out structures of adjacent rows of grid electrode structures are positioned at different ends.
Referring to fig. 2, a substrate 110 is provided, a first dielectric layer 120 is formed on the substrate, a floating gate layer 130 is formed on the first dielectric layer 120, a second dielectric layer 140 is formed on the floating gate layer 130, and a control gate layer 150 is formed on the second dielectric layer 140. The control gate layer 150 is etched to form a control gate lead-out structure.
Next, referring to fig. 3, a method for forming a control gate lead-out structure by etching the control gate 150 includes sequentially etching the control gate 150, the second dielectric layer 140, the floating gate 130, and the first dielectric layer 120 to leak out of the surface of the substrate 110, and forming a plurality of control gate lead-out structures, in this embodiment, 8 lead-out structures are provided, where the 8 lead-out structures are divided into a first square matrix 161 and a second square matrix 162, the square matrices of this embodiment are all square with four sides, two lead-out structures are respectively provided on two sides of each square matrix that are not adjacent to each other, and the 8 lead-out structures are a first lead-out structure 171, a second lead-out structure 172, a third lead-out structure 173, a fourth lead-out structure 174, a fifth lead-out structure 175, a sixth lead-out structure 176, a seventh lead-out structure 177, and an eighth lead-out. The first lead-out structure 171 and the second lead-out structure 172 are disposed on a first side of the first matrix 161, the first lead-out structure 171 is spaced apart from the second lead-out structure 172 by a distance d1, and the third lead-out structure 173 and the fourth lead-out structure 174 are disposed on a second side of the first matrix 161, the first side and the second side being non-adjacent. The fifth lead-out structure 175 and the sixth lead-out structure 176 are disposed on the third side of the second square matrix 162, the seventh lead-out structure 177 and the eighth lead-out structure 178 are disposed on the fourth side of the second square matrix 162, and the third side and the fourth sideThe two sides are not adjacent, the third side is opposite to the second side, and the third lead-out structure 173 and the fourth lead-out structure 174 are arranged opposite to and across the fifth lead-out structure 175 and the sixth lead-out structure 176. In the present embodiment, the lead-out structures are square in shape, and each lead-out structure is spaced from an adjacent lead-out structure by a distance of 0.36 μm or more, for example, the distance d between the fifth lead-out structure 175 and the sixth lead-out structure 1761The distance between the fifth lead-out structure 115 and the third lead-out structure 113 is d2(the distance here means the shortest distance between the corner of the square of the fifth lead-out structure 115 and the corner of the square of the third lead-out structure 113), d1And d2Are all greater than or equal to 0.36 microns, and can be 0.36. In other embodiments of the present invention, d1And d2May also take other values, and d1And d2The value of (b) may also be different and is determined according to the parameters of the lithography machine or the process requirements. In the prior art, 4 leading-out structures of a square matrix are on the same side, so that the distance between two adjacent leading-out structures is relatively small, a high-precision photoetching machine is required to be used for photoetching, and the cost is relatively high. In the embodiment, the leading-out structures on one square matrix are divided into two opposite edges, the requirement on the precision of the photoetching machine is low, the photoetching machine with low precision can be used, and a lot of cost is saved.
With continued reference to fig. 1 and 4, a gate structure is formed in the remaining portion by etching the control gate layer 150, the second dielectric layer 140, the floating gate layer 130, and the first dielectric layer 120 in sequence to form a floating gate and a control gate, and then forming a third dielectric layer and a word line. The formation processes of the third dielectric layer and the word line are the same as those in the prior art, and are not described herein. After a plurality of rows of grid structures are formed on the square arrays, one end of each row of grid structure is provided with a lead-out structure, and the lead-out structures of adjacent rows of grid structures are positioned at different ends. For example, the first square matrix 161 includes a first column gate structure 161A, a second column gate structure 161B, a third column gate structure 161C, and a fourth column gate structure 161D in sequence, a first end of the first column gate structure 161A has a first lead-out structure 171, a second end of the second column gate structure 161B has a third lead-out structure 173, a first end of the third column gate structure 161C has a second lead-out structure 172, and a second end of the fourth column gate structure 161D has a fourth lead-out structure 174. Therefore, the lead-out structures in adjacent rows are not at the same end, and the distance between the adjacent lead-out structures can be increased, so that a photoetching machine with lower precision can be used for etching, and the cost is reduced.
In summary, in the method for forming a semiconductor device according to the embodiment of the present invention, after the memory cells are formed, the lead-out structures are located at different ends of adjacent columns, and the distance between adjacent lead-out structures is increased, so that the requirement on the precision of the lithography machine is reduced during etching, and the etching can be completed by using the lithography machine with lower precision, thereby reducing the cost.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (10)
1. A method of forming a semiconductor device, comprising:
providing a substrate;
sequentially forming a first dielectric layer, a floating gate layer, a second dielectric layer and a control gate layer on the substrate;
sequentially etching the control gate layer, the second dielectric layer, the floating gate layer and the first dielectric layer to expose out of the surface of the substrate to form a plurality of square matrixes and a plurality of lead-out structures, wherein a plurality of lead-out structures are respectively arranged on two sides, which are not adjacent, of each square matrix;
forming a plurality of rows of grid structures on the square array to form a storage unit, wherein each grid structure is provided with two ends, one end of each row of grid structure is provided with a leading-out structure, and the leading-out structures of adjacent rows of grid structures are positioned at different ends.
2. The method of forming a semiconductor device according to claim 1, wherein the number of the square matrix is two, and the first square matrix and the second square matrix are provided with a distance therebetween.
3. The method for forming a semiconductor device according to claim 2, wherein the lead-out structure is in a square shape.
4. The method for forming a semiconductor device according to claim 2, wherein the first square matrix and the second square matrix each have a plurality of sides, and wherein the plurality of lead-out structures are distributed on opposite sides of the first square matrix and the second square matrix.
5. The method according to claim 4, wherein the number of the lead-out structures is 8, and the lead-out structures are a first lead-out structure, a second lead-out structure, a third lead-out structure, a fourth lead-out structure, a fifth lead-out structure, a sixth lead-out structure, a seventh lead-out structure, and an eighth lead-out structure, the first lead-out structure and the second lead-out structure are located on a first side of the first matrix, the third lead-out structure and the fourth lead-out structure are located on a second side of the first matrix, and the first side and the second side are opposite; the fifth leading-out structure and the sixth leading-out structure are located on a third edge of the second square matrix, the seventh leading-out structure and the eighth leading-out structure are located on a fourth edge of the second square matrix, the third edge is opposite to the fourth edge, and the second edge is opposite to the third edge.
6. The method for forming a semiconductor device according to claim 5, wherein the lead-out structure of the second side and the lead-out structure of the third side are arranged to intersect.
7. The method of forming a semiconductor device according to claim 6, wherein a distance between the adjacent lead-out structures is greater than or equal to 0.36 μm.
8. The method of claim 7, wherein the memory cell comprises a first column of gate structures and a second column of gate structures, the first column of gate structures and the second column of gate structures being adjacent, the first column of gate structures and the second column of gate structures each having a first end and a second end, the first lead-out structure being located at the first end of the first column of gate structures, the third lead-out structure being located at the second end of the second column of gate structures.
9. The method for forming a semiconductor device according to claim 1, wherein the method for forming the gate structure by etching comprises: and etching the control gate layer, the second dielectric layer, the floating gate layer and the first dielectric layer in sequence to expose the surface of the substrate to form a control gate, a second dielectric, a floating gate and a first dielectric of a gate structure, and then forming a word line between the control gate and the floating gate and a third dielectric between the word line and the control gate and the floating gate.
10. The method for forming a semiconductor device according to claim 9, wherein the lead-out structure is connected to the control gate.
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Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1845337A (en) * | 2005-04-06 | 2006-10-11 | 国际商业机器公司 | FET design with long gate and dense pitch and manufacturing method thereof |
| CN102420193A (en) * | 2010-09-25 | 2012-04-18 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of memory device |
| CN103310066A (en) * | 2013-06-25 | 2013-09-18 | 中国科学院微电子研究所 | Generation method of standard unit layout |
| CN103325788A (en) * | 2013-06-18 | 2013-09-25 | 中国科学院上海微系统与信息技术研究所 | Eight-transistor static random access memory unit |
| US20150221371A1 (en) * | 2014-02-04 | 2015-08-06 | Stmicroelectronics S.R.I. | Embedded non-volatile memory with single polysilicon layer memory cells programmable through channel hot electrons and erasable through fowler-nordheim tunneling |
| CN107437548A (en) * | 2016-05-26 | 2017-12-05 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacture method, electronic installation |
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Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1845337A (en) * | 2005-04-06 | 2006-10-11 | 国际商业机器公司 | FET design with long gate and dense pitch and manufacturing method thereof |
| CN102420193A (en) * | 2010-09-25 | 2012-04-18 | 中芯国际集成电路制造(上海)有限公司 | Manufacturing method of memory device |
| CN103325788A (en) * | 2013-06-18 | 2013-09-25 | 中国科学院上海微系统与信息技术研究所 | Eight-transistor static random access memory unit |
| CN103310066A (en) * | 2013-06-25 | 2013-09-18 | 中国科学院微电子研究所 | Generation method of standard unit layout |
| US20150221371A1 (en) * | 2014-02-04 | 2015-08-06 | Stmicroelectronics S.R.I. | Embedded non-volatile memory with single polysilicon layer memory cells programmable through channel hot electrons and erasable through fowler-nordheim tunneling |
| CN107437548A (en) * | 2016-05-26 | 2017-12-05 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacture method, electronic installation |
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