CN110634879B - Method for forming semiconductor device - Google Patents
Method for forming semiconductor device Download PDFInfo
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- CN110634879B CN110634879B CN201910912440.7A CN201910912440A CN110634879B CN 110634879 B CN110634879 B CN 110634879B CN 201910912440 A CN201910912440 A CN 201910912440A CN 110634879 B CN110634879 B CN 110634879B
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- 238000000034 method Methods 0.000 title claims abstract description 35
- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 239000000758 substrate Substances 0.000 claims abstract description 33
- 238000005530 etching Methods 0.000 claims description 15
- 238000000605 extraction Methods 0.000 claims description 14
- 238000001312 dry etching Methods 0.000 claims description 2
- 230000004075 alteration Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
- H10B41/42—Simultaneous manufacture of periphery and memory cells
- H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
- H10B41/44—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a control gate layer also being used as part of the peripheral transistor
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/60—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates the control gate being a doped region, e.g. single-poly memory cell
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Abstract
The invention provides a method for forming a semiconductor device, which comprises the following steps: providing a substrate, wherein the substrate is divided into a first part and a second part; sequentially forming a first dielectric layer, a floating gate layer, a second dielectric layer and a control gate layer on a substrate; the control gate layer, the second dielectric layer, the floating gate layer and the first dielectric layer of the first portion are etched in sequence to form a plurality of groups of leading-out structures side by side, each group of leading-out structures comprises two leading-out strips, three control gate connecting electrodes are connected with the two outer sides of the leading-out strips and the two leading-out strips, the cross section size of one end, connected with the second portion, of each leading-out strip is larger than that of the other end, and the control gate connecting electrodes of the two adjacent leading-out structures are arranged in a staggered mode. In the method for forming a semiconductor device of the present invention, any one of the control gate connection electrodes formed is not short-circuited to its adjacent terminal connection.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a forming method of a semiconductor device.
Background
The grid structure can be used as a storage unit, a plurality of storage units can form a storage array, the storage array is divided into a plurality of rows and a plurality of columns, the control grids of the storage units on the same column are connected to one line through the leading-out structure, and the storage units on the column can be controlled through the line. In the prior art, before a gate structure is formed, a plurality of leading-out structures are formed by etching, then the gate structure is formed by etching, a storage array is formed by the plurality of gate structures, the storage array is divided into a plurality of columns, each column is provided with the leading-out structure of one control gate, and the plurality of leading-out structures are positioned on two sides of each column. The leading-out structure is away from the grid electrode of the grid electrode structure on the adjacent row, and the distance is too small, so that the leading-out structure is easy to be short-circuited with the floating grid electrode of the grid electrode structure on the adjacent row.
Disclosure of Invention
The invention aims to provide a method for forming a semiconductor device, which enables the distance between a lead-out structure of a control gate on each column of a storage unit and a gate on an adjacent column to be larger, so that the lead-out structure of the control gate and the gate are not short-circuited.
In order to achieve the above object, the present invention provides a method of forming a semiconductor device, comprising:
providing a substrate, and dividing the substrate into a first part and a second part;
sequentially forming a first dielectric layer, a floating gate layer, a second dielectric layer and a control gate layer on the substrate;
sequentially etching part of a control gate layer, part of a second dielectric layer, part of a floating gate layer and part of a first dielectric layer on the first part of the substrate to expose out of the surface of the substrate to form a plurality of groups of parallel leading-out structures, wherein each group of leading-out structure comprises two leading-out strips and three control gate connecting electrodes, the three control gate connecting electrodes are respectively connected between the outer sides of the two leading-out strips and the two leading-out strips, the cross section size of one end, connected with the second part, of each leading-out strip is larger than that of the other end, and the control gate connecting electrodes of the two adjacent groups of leading-out structures are arranged in a staggered manner;
and forming a plurality of columns of grid structures on the second part to form a storage unit, wherein each column of grid structures corresponds to one leading-out strip, and the cross section size of each column of grid structures is larger than that of the leading-out strip.
Optionally, in the method for forming the semiconductor device, the first lead-out structure includes a first lead-out strip and a second lead-out strip, and the first lead-out strip and the second lead-out strip are connected through a control gate connection electrode.
Optionally, in the method for forming a semiconductor device, two adjacent lead-out bars are symmetrical with a central line of the adjacent lead-out bar.
Optionally, in the method for forming a semiconductor device, the control gate connection electrode is rectangular.
Optionally, in the method for forming a semiconductor device, a distance from the control gate connection electrode of the first group of extraction structures to the second portion is different from a distance from the control gate connection electrode of the second group of extraction structures to the second portion.
Optionally, in the method for forming a semiconductor device, the extraction bar is divided into a first side, a second side, a third side and a fourth side, one end of the first side is connected to the second portion, the other end of the first side is connected to the second side, the first side and the second side are not in a straight line, that is, an angle formed by the first side and the second side is not 180 degrees, the third side is perpendicular to the second side and is connected to the second side, and the fourth side is perpendicular to the third side and is connected to the third side and the second portion.
Optionally, in the method for forming a semiconductor device, the method for forming a gate structure by etching includes: and etching part of the control gate layer, part of the second dielectric layer, part of the floating gate layer and part of the first dielectric layer of the second part in sequence to expose out of the surface of the substrate to form a control gate, a second dielectric, a floating gate and a first dielectric of a gate structure, and then forming a word line which is positioned on the first dielectric and between the control gate and a third dielectric between the word line and the control gate.
Optionally, in the method for forming a semiconductor device, each column of gate structures is located on an extension line of the lead-out bar, and the control gate is connected to the control gate connection electrode.
Optionally, in the method for forming a semiconductor device, every two adjacent columns of the gate structures are divided into a sector, the memory cell further includes a bit line located in the substrate, the same bit line is shared between two columns of the gate structures of the same sector, and the adjacent gate structures of the adjacent sectors share the bit line.
Optionally, in the method for forming the semiconductor device, the method for etching the control gate layer, the second dielectric layer, the floating gate layer and the first dielectric layer to expose the surface of the substrate is dry etching.
In the method for forming the semiconductor device, any control gate connecting electrode is formed to have enough distance with the adjacent leading-out strip, and the control gate connecting electrode is not connected with the adjacent leading-out strip to be short-circuited.
Drawings
Fig. 1 is a flow chart of a method of forming a semiconductor device of an embodiment of the present invention;
fig. 2 is a cross-sectional view of a method of forming a semiconductor device of an embodiment of the present invention;
fig. 3 to 5 are top views of a method of forming a semiconductor device of an embodiment of the present invention;
FIG. 6 is a cross-sectional view of a gate structure of an embodiment of the present invention;
in the figure: 10-substrate, 20-first dielectric layer, 21-first dielectric, 30-floating gate layer, 31-floating gate, 40-second dielectric layer, 41-second dielectric, 50-control gate layer, 51-control gate, 61-word line, 71-third dielectric, 81-bit line, 100-first part, 200-second part, 311-first extraction bar, 312-second extraction bar, 313-third extraction bar, 314-fourth extraction bar, 321-first group of control gate connection electrodes, 322-second group of control gate connection electrodes, 311A-first side, 311B-second side, 311C-third side, 311D-fourth side, 211-first column gate structure, 212-second column gate structure, 213-third column gate structure, 214-fourth column gate structure.
Detailed Description
The following describes in more detail embodiments of the present invention with reference to the schematic drawings. Advantages and features of the present invention will become apparent from the following description and claims. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Referring to fig. 1, the present invention provides a method of forming a semiconductor device, including:
s11: providing a substrate, and dividing the substrate into a first part and a second part;
s12: sequentially forming a first dielectric layer, a floating gate layer, a second dielectric layer and a control gate layer on the substrate;
s13: sequentially etching part of a control gate layer, part of a second dielectric layer, part of a floating gate layer and part of a first dielectric layer on the first part of the substrate to expose out of the surface of the substrate to form a plurality of groups of parallel leading-out structures, wherein each group of leading-out structure comprises two leading-out strips and three control gate connecting electrodes, the three control gate connecting electrodes are respectively connected between the outer sides of the two leading-out strips and the two leading-out strips, the cross section size of one end, connected with the second part, of each leading-out strip is larger than that of the other end, and the control gate connecting electrodes of the two adjacent groups of leading-out structures are arranged in a staggered manner;
s14: and forming a plurality of columns of grid structures on the second part to form a storage unit, wherein each column of grid structures corresponds to one leading-out strip, and the cross section size of each column of grid structures is larger than that of the leading-out strip.
Referring to fig. 2, a substrate 10 is provided, the substrate is divided into a first portion 100 and a second portion 200, a first dielectric layer 20 is formed on the substrate, a floating gate layer 30 is formed on the first dielectric layer 20, a second dielectric layer 40 is formed on the floating gate layer 30, and a control gate layer 50 is formed on the second dielectric layer 40. The first dielectric layer 20, the floating gate layer 30, the second dielectric layer 40 and the control gate layer 50 on the first portion 100 are used for forming a leading-out structure of a control gate through etching, and the first dielectric layer 20, the floating gate layer 30, the second dielectric layer 40 and the control gate layer 50 on the second portion 200 are used for forming a gate structure through etching.
With reference to fig. 2 to 5, in detail, the method for etching the first dielectric layer 20, the floating gate layer 30, the second dielectric layer 40 and the control gate layer 50 on the first portion 100 to form the extraction structure includes sequentially etching a portion of the control gate layer 50, a portion of the second dielectric layer 40, a portion of the floating gate layer 30 and a portion of the first dielectric layer 20 of the first portion 100 to expose the surface of the substrate 10, forming a plurality of extraction structures, specifically, covering a portion of the control gate layer 50 with photoresist, sequentially etching the control gate layer 50, the second dielectric layer 40, the floating gate layer 30 and the first dielectric layer 20 are exposed out of the surface of the substrate 10, the number of the lead-out structures after etching is multiple, each lead-out structure comprises a lead-out strip and a control gate connecting electrode, one end of each lead-out strip is connected with the first dielectric layer 20, the floating gate layer 30, the second dielectric layer 40 and the control gate layer 50 on the second part 200, and the plurality of lead-out strips and the second part 200 form an interdigital structure. Draw strip and control gate connection electrode's quantity to be a plurality of, in this embodiment, has four to draw strip and six control gate connection electrode, and is specific, and four draw the strip and include: a first lead tab 311, a second lead tab 312, a third lead tab 313 and a fourth lead tab 314; six control grid connecting electrodes divide into two sets ofly, and each group is including three control grid connecting electrode, and two sets of control grid connecting electrode do respectively: the first group of control gate connection electrodes 321 and the second group of control gate connection electrodes 322, the outer sides of the first lead-out strip 311 and the second lead-out strip 312 are both provided with a lead-out strip, meanwhile, a lead-out strip is arranged between the first lead-out strip 311 and the second lead-out strip 312, the three lead-out strips form the first group of control gate connection electrodes 321, and correspondingly, the other three control gate connection electrodes form the second group of control gate connection electrodes 322. The end of the lead-out bar connected with the second part 200 and connected with the second part 200 has a larger cross-sectional size than the other end, the control gate connection electrode has a rectangular shape, and the lead-out bar has a regular polygonal shape, for example, the first lead-out bar 311 is divided into a first side 311A, a second side 311B, a third side 311C and a fourth side 311D, one end of the first side 311A is connected with the second part 200, the other end of the first side 311A is connected with the second side 311B, and the first side 311A and the second side 311B are not on a straight line, that is, an angle formed by the first side 311A and the second side 311B is not 180 degrees. Third side 311C is perpendicular to second side 311B and connects to second side 311B, and fourth side 311D is perpendicular to third side 311C and connects to third side 311C. The first and second lead-out strips 311, 312, 313 and 314 are of the same shape but the first and second lead-out strips 311, 312 are symmetrical about the centre line of the first and second lead-out strips 311, 312 and the third and fourth lead-out strips 313, 314 are symmetrical about the centre line of the third and fourth lead-out strips 313, 314. The first lead-out strip 311, the second lead-out strip 312 and the first control gate connecting electrode 321 bridged above are used as a group of lead-out structures which are named as a first group of lead-out structures 301, and the third lead-out strip 313, the fourth lead-out strip 314 and the second control gate connecting electrode 322 bridged above are used as a group of lead-out structures which are named as a second group of lead-out structures 302. In other embodiments of the present invention, the control gate connection electrode may not be connected to the first lead-out strip and the second lead-out strip, and may be separately connected to the first lead-out strip or the second lead-out strip, that is, each lead-out strip has one control gate connection electrode, and meanwhile, in other embodiments of the present application, the shapes of the lead-out strips and the control gate connection electrodes may be other shapes.
The three control gate connection electrodes of each group of control gate connection electrodes are on the same straight line, the first control group control gate connection electrode 321 and the second control gate connection electrode 322 are not on the same straight line, namely the distances between the first control gate connection electrode 321 and the second control gate connection electrode 322 and the second part 200 are different, and the second leading-out strip 312 and the third leading-out strip 313 which are arranged in a staggered mode can be etched by a lower-precision photoetching machine, so that the second leading-out strip 312 or the third leading-out strip 313 cannot be short-circuited.
Referring to fig. 5 and 6, continuing to etch partially the control gate layer 50, partially the second dielectric layer 40, partially the floating gate layer 30 and partially the first dielectric layer 20 in the second portion 200 and leaking out of the substrate 10, the first dielectric 21 on the substrate 10, the floating gate 31 on the first dielectric 21, the second dielectric 41 on the floating gate 31 and the control gate 51 on the second dielectric 41 are formed, and then, the word line 61 between the control gate 51 and the third dielectric 71 between the control gate 51 and the word line 61 are formed on the first dielectric 21. Every two adjacent columns of the gate structures are divided into a sector, and a bit line 81 positioned between the control gates 51 of the gate structures of the same sector is also arranged in the substrate 10, and the gate structures of the same sector share the bit line 81. The method of forming the gate structure is prior art and will not be set forth herein. The formed multi-column grid structures form a storage unit, a control grid of the storage unit is connected with a leading-out strip, each column of grid structures corresponds to one leading-out strip, and a group of leading-out structures are used for two columns of grid structures sharing the bit line 81. For example, the multi-column gate structures sequentially include a first column of gate structures 211, a second column of gate structures 212, a third column of gate structures 213 and a fourth column of gate structures 214, one end of the first column of gate structures 212 is correspondingly connected with a first lead-out strip 311, one end of the second column of gate structures 212 is correspondingly connected with a second lead-out strip 312, one end of the third column of gate structures 213 is correspondingly connected with a third lead-out strip 313, and one end of the fourth column of gate structures 214 is correspondingly connected with a fourth lead-out strip 314. The cross section size of each column of grid structures is larger than that of the corresponding extraction strip, so that the control grid connection electrode on the extraction strip has enough distance with the adjacent extraction strip, and the control grid connection electrode cannot be connected with the adjacent extraction strip for short circuit.
In summary, in the method for forming a semiconductor device according to the embodiment of the invention, any control gate connection electrode is formed to have a sufficient distance from its adjacent bar, and will not be short-circuited with its adjacent bar.
The above description is only a preferred embodiment of the present invention, and does not limit the present invention in any way. It will be understood by those skilled in the art that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (8)
1. A method of forming a semiconductor device, comprising:
providing a substrate, and dividing the substrate into a first part and a second part;
sequentially forming a first dielectric layer, a floating gate layer, a second dielectric layer and a control gate layer on the substrate;
sequentially etching part of a control gate layer, part of a second dielectric layer, part of a floating gate layer and part of a first dielectric layer on the first part of the substrate to expose out of the surface of the substrate to form a plurality of groups of parallel leading-out structures, wherein each group of leading-out structure comprises two leading-out strips and three control gate connecting electrodes, the three control gate connecting electrodes are respectively connected between the outer sides of the two leading-out strips and the two leading-out strips, the cross section size of one end, connected with the second part, of each leading-out strip is larger than that of the other end, and the control gate connecting electrodes of two adjacent groups of leading-out structures are arranged in a staggered manner;
and forming a plurality of columns of grid structures on the second part to form a storage unit, wherein each column of grid structures corresponds to one leading-out strip, and the cross section size of each column of grid structures is larger than the size of the smaller end of the cross section of the leading-out strip.
2. The method of forming a semiconductor device of claim 1, wherein adjacent two of the tabs are symmetrical about a centerline of the adjacent tabs.
3. The method for forming a semiconductor device according to claim 1, wherein the control gate connection electrode has a rectangular shape.
4. A method of forming a semiconductor device according to claim 1, wherein the lead-out bar is divided into a first side, a second side, a third side, and a fourth side, the first side is connected to the second portion at one end, the first side is connected to the second portion at the other end, the first side and the second side are not on a straight line, i.e., an angle formed by the first side and the second side is not 180 degrees, the third side is perpendicular to the second side and is connected to the second side, and the fourth side is perpendicular to the third side and is connected to the third side and the second portion.
5. The method for forming a semiconductor device according to claim 1, wherein a portion of the control gate layer, a portion of the second dielectric layer, a portion of the floating gate layer, and a portion of the first dielectric layer of the second portion are sequentially etched to expose the surface of the substrate to form a control gate, a second dielectric, a floating gate, and a first dielectric of a gate structure, and then a word line located on the first dielectric and between the control gate and a third dielectric between the word line and the control gate are formed.
6. The method of claim 5, wherein each column of the gate structures is located on an extension of the extraction bar, and the control gate is connected to the control gate connection electrode.
7. The method of claim 6, wherein every two adjacent columns of said gate structures are divided into a sector, said memory cell further comprising a bit line located in said substrate, and two columns of said gate structures of a same said sector share a same bit line therebetween.
8. The method for forming the semiconductor device according to claim 6, wherein the method for exposing the etching control gate layer, the second dielectric layer, the floating gate layer and the first dielectric layer on the surface of the substrate is dry etching.
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| CN201910912440.7A CN110634879B (en) | 2019-09-25 | 2019-09-25 | Method for forming semiconductor device |
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| CN201910912440.7A CN110634879B (en) | 2019-09-25 | 2019-09-25 | Method for forming semiconductor device |
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| CN110634879B true CN110634879B (en) | 2021-12-10 |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000082650A (en) * | 1998-09-04 | 2000-03-21 | Nec Corp | Projection exposure method |
| CN1339824A (en) * | 2000-08-17 | 2002-03-13 | 株式会社东芝 | Semiconductor device and its producing method |
| CN1979814A (en) * | 2005-12-09 | 2007-06-13 | 三星电子株式会社 | Electrically erasable and programmable read only memories and methods of fabricating the same |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4278338B2 (en) * | 2002-04-01 | 2009-06-10 | 株式会社ルネサステクノロジ | Semiconductor memory device |
| US7655387B2 (en) * | 2004-09-02 | 2010-02-02 | Micron Technology, Inc. | Method to align mask patterns |
| JP4909733B2 (en) * | 2006-12-27 | 2012-04-04 | 株式会社東芝 | Semiconductor memory device |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000082650A (en) * | 1998-09-04 | 2000-03-21 | Nec Corp | Projection exposure method |
| CN1339824A (en) * | 2000-08-17 | 2002-03-13 | 株式会社东芝 | Semiconductor device and its producing method |
| CN1979814A (en) * | 2005-12-09 | 2007-06-13 | 三星电子株式会社 | Electrically erasable and programmable read only memories and methods of fabricating the same |
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