CN112133699B

CN112133699B - Active area structure and forming method thereof

Info

Publication number: CN112133699B
Application number: CN202010969107.2A
Authority: CN
Inventors: 林刚毅
Original assignee: Fujian Jinhua Integrated Circuit Co Ltd
Current assignee: Fujian Jinhua Integrated Circuit Co Ltd
Priority date: 2020-09-15
Filing date: 2020-09-15
Publication date: 2022-05-06
Anticipated expiration: 2040-09-15
Also published as: CN112133699A

Abstract

The invention discloses an active area structure and a forming method thereof, wherein the forming method of the active area structure comprises the following steps: forming a plurality of sacrificial patterns over a substrate, wherein at least some of the sacrificial patterns comprise a horizontal portion and a vertical portion, wherein the horizontal portion of at least some of the sacrificial patterns is aligned with the horizontal portion of another adjacent sacrificial pattern in a horizontal direction, and the vertical portion of at least some of the sacrificial patterns is aligned with the vertical portion of another adjacent sacrificial pattern in a vertical direction; a plurality of spacer patterns are formed, each of which surrounds a sacrificial pattern. The forming method of the active area structure can block the stress of the shallow trench insulating layer of the peripheral large area to the component area, and prevent the component unit of the peripheral edge area of the component area from being damaged due to the stress. The boundary structure can compensate for uneven stress between active lines at the ends and also avoid damage to the component cells.

Description

Active area structure and forming method thereof

Technical Field

The present invention relates to semiconductor technology. More particularly, the present invention relates to an active area structure and a method for forming the same.

Background

In recent years, electronic products are designed to have multifunction and fast processing capability. In order to increase processing power, for example, in computer systems or multi-function electronic products, large Dynamic Random Access Memories (DRAMs) are required. In order to increase the memory capacity, the size of the memory cell of the memory needs to be reduced, but the reduction of the size of the memory cell causes other problems, such that the operation of the memory cell is unstable or the memory cell is damaged.

Semiconductor devices are generally formed by forming a desired device structure on the basis of an active layer unit defined on a substrate. Therefore, the active layer unit on the substrate is the basis of the components, and the size, shape and position of the components are determined. The active layer unit is also referred to as a device unit hereinafter.

Taking the memory cell of the memory as an example, a plurality of component units are arrayed in a predetermined component area in a regular arrangement. A component unit will eventually form a memory cell. In addition, there are peripheral circuits around the memory cells to control the memory cells in order to operate the memory cells. These peripheral circuits are also formed on the basis of the peripheral active region.

Therefore, under the demand of reducing the size of the semiconductor device, how to design the device structure to maintain the normal operation of the device is also one of the issues to be considered.

The above information disclosed in this background section is only for enhancement of understanding of the background of the technology described herein and, therefore, certain information may be included in the background that does not form the prior art that is already known in this country to a person of ordinary skill in the art.

Disclosure of Invention

The present invention provides an active area structure and a method for forming the same, which can at least avoid the damage of a semiconductor component caused by the stress generated by a shallow trench insulation structure around the component when the size of the semiconductor component is reduced.

The invention provides a method for forming an active region structure, which comprises the following steps: forming a plurality of sacrificial patterns over a substrate, wherein at least a portion of the sacrificial patterns comprise a horizontal portion and a vertical portion, wherein the horizontal portion of at least a portion of the sacrificial patterns is aligned with the horizontal portion of another adjacent sacrificial pattern in a horizontal direction, and the vertical portion of at least a portion of the sacrificial patterns is aligned with the vertical portion of another adjacent sacrificial pattern in a vertical direction, and forming a plurality of spacer patterns, each of which surrounds one of the sacrificial patterns.

Optionally, each of the spacer patterns is a closed sub-pattern when viewed from a front view.

Optionally, a plurality of the spacer patterns are in contact with each other and constitute a closed pattern.

Optionally, the closed pattern comprises a closed edge portion, and a plurality of diagonal portions are located in an area within the closed edge portion.

Optionally, the plurality of diagonal portions are arranged along a first direction, wherein the first direction is different from the horizontal direction and the vertical direction.

Optionally, the closed edge portion comprises a plurality of borders, wherein at least one of the borders extends along the horizontal direction and at least one of the borders extends along the vertical direction.

Optionally, after forming the plurality of spacer patterns, a first etching step is performed to remove the plurality of sacrificial patterns.

Optionally, the method further comprises a step of forming a material layer, wherein the material layer is located between the substrate and the plurality of spacer patterns.

Optionally, the method further comprises performing a second etching step to transfer the spacer patterns into the material layer by using the spacer patterns as a mask.

The present invention also provides an active region structure comprising: the plurality of closed pattern active regions are positioned on a substrate, the plurality of closed pattern active regions are mutually contacted with each other and form a closed pattern, wherein a first boundary of the closed pattern extends along a horizontal direction, and a second boundary of the closed pattern extends along a vertical direction.

Optionally, the display device further comprises a plurality of oblique component units located in the closed pattern, wherein the plurality of oblique component units do not contact the closed pattern, and the plurality of oblique component units are arranged along a first direction, wherein the first direction is different from the horizontal direction and the vertical direction.

Optionally, the closed pattern includes the first boundary, the second boundary, and a third boundary extending along the first direction.

Optionally, at least one of the closed pattern active regions includes an irregular polygon of a hexagonal or more.

Optionally, the closed patterns have different widths, wherein a maximum width is greater than 1.3 times and not greater than 2 times a width of a short side of the diagonal module unit.

The present invention also provides an active region structure comprising: a closed pattern active region on a substrate, the closed pattern comprising: a closed edge portion, and a plurality of diagonal device elements in an area within the closed edge portion, the plurality of diagonal device elements arranged along a first direction, and at least one branch structure contacting the closed pattern active region edge portion and extending inward of the closed pattern active region; the branch structure includes a first portion and a second portion, the first portion is arranged along the first direction, and the second portion is arranged along a second direction different from the first direction.

Optionally, the closed edge portion further comprises at least one closed sub-pattern.

Optionally, a first boundary of the closed pattern extends along a horizontal direction, a second boundary of the closed pattern extends along a vertical direction, and a third boundary of the closed pattern extends along the first direction.

Optionally, the closed edge portions have different widths, with the largest width being at the intersection of the branch structure and the closed edge portion.

Optionally, the first portion and the second portion of the branching structure are not the same length.

Optionally, the length of the branch structures aligned along the first direction is 2 to 8 times the length of the branch structures aligned along the second direction.

Based on the above active region structure and the forming method thereof, the periphery of the device region further includes a boundary structure surrounding the device region, so that the stress generated by the shallow trench isolation layer in the large peripheral region on the device region can be blocked, and the device unit in the peripheral edge region of the device region can be prevented from being damaged due to the stress. In addition, the boundary structure comprises a branch structure extending towards the component region, and the branch structure extends towards at least two different directions, so that uneven stress at the end part between active lines can be compensated, and the damage of the component unit can be avoided.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this application, illustrate embodiments of the application and, together with the description, serve to explain the application and are not intended to limit the application. In the drawings:

fig. 1 is a schematic front view of an active region structure according to an embodiment of the invention.

Fig. 2 to 6 are schematic front views illustrating a process of fabricating the active region structure shown in fig. 1 according to the present invention.

Wherein the reference numerals are as follows:

11. a layer of material; 12. a first sacrificial pattern; 12H, horizontal portion; 12V, vertical section; 12S, a first oblique part; 14. a spacer pattern; 15. a closed pattern; 16. an edge portion; 17. a second angled portion; 20. a mask pattern; 90. a memory device; 100. an active region; 102. a component area; 104. an assembly unit; 106. a boundary structure; 107. a branched structure; 107a, a first portion; 107b, a second portion; 108. an insulating layer; 108a, a first component; 108b, a second component; 110. a peripheral active region; 112. a notch; 150. an active layer.

Detailed Description

It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.

It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of exemplary embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.

It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. Also, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element or "connected" to the other element through a third element.

Semiconductor devices, such as memory cells, require isolation to achieve isolation, and insulating structures are formed between the device cells and the peripheral active region, such as by using shallow trench isolation, to provide isolation between devices, under high device density requirements.

The present invention considers the insulation quality among the components and proposes a corresponding design.

The shallow trench isolation layer is made of a dielectric material, and the device unit and the peripheral active region are formed by patterning a portion of the substrate, such as a surface layer portion of a silicon substrate. Furthermore, the distance between the device units and the peripheral active region is larger than the gap between the device units, and the occupied area is larger, thereby generating larger stress. Therefore, the material of the sti layer may cause unbalanced stress to the device cells in the edge region, and may easily damage some of the device cells at the edge. The invention provides an effective design for forming the component unit, can reduce the stress effect of the shallow trench insulating layer on the component unit and avoid the damage of the component unit.

The invention is illustrated below by way of a number of examples, but is not limited to the examples.

Fig. 1 is a schematic front view of an active region structure according to an embodiment of the invention. Referring to fig. 1, a memory device 90, for example, may comprise an active area 100, a peripheral active area 110, and an insulating layer 108 for isolation therebetween, for a device's overall semiconductor structure. The active region 100 is a region for forming high density devices. Taking the memory device 90 as an example, the active region 100 is a region for forming a memory cell array. The active region 100 includes a device region 102. A plurality of device units 104 are expected to be formed in the device region 102 as the basis for the completed device structure to be fabricated. That is, the area of the array formed by the device units 104 is hereinafter referred to as the device area 102.

The active region 100 also includes a border structure 106 at the periphery of the device region 102. In one exemplary embodiment, the boundary structure 106, for example, continuously surrounds the component area 102.

The component unit 104 and the boundary structure 106 are formed by a patterned manufacturing process of a surface layer of a substrate, such as a silicon substrate. The component unit 104 and the boundary structure 106, which are hereinafter also referred to as an active layer 150, have a plurality of component units 104 within the component region 102 and the boundary structure 106 surrounds the component region 102.

The border structure 106 of the present invention has at least one branch structure 107 extending inwardly into the device region 102 and between a portion of the device cells 104. The number of branch structures 107 is typically plural.

The active region 100 further comprises a shallow trench isolation layer 108 for isolating the device cells 104 and isolating the device cells 104 from the peripheral active region 110. It is understood that the sti layer 108 included in the active region 100 is a part of the overall structure. The shallow trench isolation layer 108 actually extends to the peripheral active region 110, and also provides an isolation effect to the peripheral active region 110.

In a more specific structure of an embodiment, the sti 108 has a first portion 108a and a second portion 108 b. A first member 108a is formed within the boundary structure 106 to insulate between the component units 104. The second member 108b is around the outer perimeter of the boundary structure 106. That is, the second portion 108b of the shallow trench isolation layer 108 isolates the device cells 104 from the peripheral active region 110.

The peripheral active region 110 is a component for forming peripheral circuits, which are also formed by patterning a surface layer of the substrate. Taking the memory device 90 as an example, the peripheral active region 110 is used to form a peripheral circuit and control operations such as data storage, reading, and erasing to the memory cells. In addition, the position of the memory cell structure to be formed later corresponds to the component unit 104, and the component unit 104 is taken as the basis of the component structure.

It should be noted that there is a distance D between the boundary structure 106 and the peripheral active region 110. This distance D is typically greater than the spacing between the component units 104. Therefore, the second portion 108b of the sti 108 may have a greater stress between the boundary structure 106 and the peripheral active region 110 than the first portion 108 a. However, the boundary structure 106 of the present invention can block the stress generated by the second portion 108b of the sti layer 108.

A still further effect is that the at least one branch structure 107 of the boundary structure 106 may extend inwardly into the component areas 102 of the component units 104, such that the edges of the component areas 102 are stressed uniformly. To explain further, each of these assembly units 104 has a bar shape, that is, a bar structure. The assembly units are aligned with each other in the longitudinal direction to form a plurality of active lines. The direction of the active line is, for example, inclined with respect to one side of the device region 102. Each of the plurality of active lines contains a plurality of component units 104. However, the positions of the component units 104 on the two adjacent active lines are not coincident, but are arranged to be staggered left and right. The source lines 'end points will not all fall neatly (near) around the device region 102, depending on the location of the device cells 104, and thus some source lines' end points will be recessed into the device region 102. This phenomenon, for the active lines themselves, results in unbalanced stress at the ends of two adjacent active lines due to the recessed active lines. However, the branch structure 107 of the boundary structure 106 of the present invention is aligned with a corresponding one of the active lines and is located between two adjacent active lines. Therefore, the stress balance is achieved by a more uniform stress distribution around the device region 102 due to the branch structure 107, which reduces the damage of the device unit 104 in the peripheral region of the device region 102. In addition, in this embodiment, the component unit 104 does not contact the boundary structure 106.

Here, the line width of the branch structure 107 is, for example, consistent with the line width of the active line, so that a better stress balance can be obtained. In addition, the outer periphery of the boundary structure 106 may also form a notch 112, for example. The number, depth and width of the notches 112 can be determined according to actual requirements. Due to the mechanical effect of the gap 112, the strength of the boundary structure 106 can be enhanced to resist the stress generated by the sti layer 108 at the periphery.

Furthermore, the branch structures 107 may extend in different directions. For example, the branch structure 107 may include a first portion 107a arranged along the first direction D1 and a second portion 107b arranged toward the second direction (X direction or Y direction). Wherein the first direction D1 is the same as the arrangement direction of the component units 104. That is, the plurality of unit cells 104 are arranged along the oblique direction (the first direction D1), and the first portion 107a of the branch structure 107 is also arranged toward the first direction D1, but the second portion 107b of the branch structure 107 is arranged toward a second direction different from the first direction D1. In addition, the first direction D1 in this embodiment is different from a horizontal direction (e.g., X direction) or a vertical direction (e.g., Y direction).

In accordance with the mechanisms of the boundary structure 106 of the present invention, the boundary structure 106 is not limited to continuously surround the component area 102 in the manner set forth in the preceding embodiments. The boundary structure 106 may also partially surround the device region 102 only in response to the peripheral active region 110. Thus, the boundary structure 106 may only partially surround the component region 102. However, based on the actual circuit layout, there will be peripheral active areas 110 around the device region 102 for various circuits, and therefore, in one embodiment, the boundary structure 106 may be formed of multiple components rather than being directly connected to each other. Taking the quadrilateral component area 102 as an example, it may be discontinuously surrounded by four boundary structures 106.

Fig. 2 to 6 are schematic front views illustrating a process of fabricating the active region structure shown in fig. 1 according to the present invention. For purposes of simplicity, fig. 2-6 only show the structures within the device region 102, and omit other surrounding devices (e.g., the peripheral active region 110).

As shown in fig. 2, a material layer 11 is formed on a substrate (not shown), wherein the substrate may include a single-layer structure or a multi-layer structure, such as a silicon substrate or a multi-layer stack structure composed of multiple layers of materials, such as a silicon substrate, an oxide layer, an amorphous silicon layer, etc. The material layer 11 may be an insulating layer, such as a silicon nitride layer, on the substrate. Next, a plurality of first sacrificial patterns 12 are formed on the material layer 11, wherein at least a portion of the first sacrificial patterns 12 includes a horizontal portion 12H and a vertical portion 12V, and a plurality of first oblique portions 12S are located between the horizontal portion 12H and the vertical portion 12V, wherein the first oblique portions 12S are arranged along a first direction D1. In addition, the horizontal portion 12H of at least a part of the first sacrificial patterns 12 and the horizontal portion 12H of another adjacent first sacrificial pattern 12 are aligned with each other in a horizontal direction (e.g., X direction), and the vertical portion 12V of at least a part of the first sacrificial patterns 12 and the vertical portion 12V of another adjacent first sacrificial pattern 12 are aligned with each other in a vertical direction (e.g., Y direction). In the present embodiment, the material of the first sacrificial pattern 12 is, for example, an Organic Dielectric Layer (ODL), but is not limited thereto.

As shown in fig. 3, a plurality of spacer patterns 14 are formed around each of the first sacrificial patterns 12. The method for forming a plurality of spacer patterns may include a deposition step and an etch-back step for forming the spacer patterns 14 along the periphery of the first sacrificial patterns 12. The material of the spacer pattern 14 may be selected from materials different from those of the first sacrificial pattern 12 and the material layer 11, such as, but not limited to, silicon oxide or silicon oxynitride.

As shown in fig. 4, the first sacrificial patterns 12 are removed by etching or the like, thus leaving a plurality of spacer patterns 14 on the material layer 11. It should be noted that, since fig. 3 mentioned above has mentioned that the spacer patterns 14 are formed around the first sacrificial patterns 12, each of the spacer patterns 14 should be a closed pattern. That is, each side of each spacer pattern 14 facing outward is surrounded by the spacer pattern without a gap, as viewed from the center thereof.

In addition, in the present embodiment, the first sacrificial patterns 12 shown in fig. 2 are spaced apart from each other by a small distance, so that after the spacer patterns 14 are formed, the spacer patterns are connected to each other to form a closed pattern 15. As shown in fig. 4, the closed pattern 15 is formed by connecting a plurality of closed spacer patterns 14 to each other. Further, as shown in fig. 4, the closed pattern includes a closed edge portion 16 and a plurality of second oblique portions 17, the second oblique portions 17 are located in the edge portion 16, wherein at least one side of the edge portion 16 extends along a horizontal direction (e.g., X direction), another at least one side of the edge portion 16 extends along a vertical direction (e.g., Y direction), and the plurality of second oblique portions 17 extend along the first direction D1.

As shown in fig. 5, the closed pattern 15 (including the edge portion 16 and the second diagonal portion 17) is transferred into the underlying material layer 11 by means of an etching step or the like. A mask pattern 20 is formed in the raw material layer 11. The mask pattern 20 is located on the substrate, and when the substrate is a single layer, the mask pattern 20 is directly located on the substrate, that is, the substrate is exposed, or when the substrate is a multi-layer structure, the mask pattern 20 may be located on other material layers. Since the mask pattern 20 is formed by etching the material layer 11, the material is also the same (for example, the mask pattern 20 also includes silicon nitride).

As shown in fig. 6, a patterning step is performed to partially remove the mask pattern 20, and particularly to partially remove the second inclined portion 17, so as to divide the second inclined portion 17 into a plurality of spaced segment structures, wherein each segment structure corresponds to a component unit 104 of the active region 100 to be formed subsequently. That is, the remaining mask pattern 20 of FIG. 6 is used as another mask layer to transfer the pattern into the underlying substrate, and the resulting pattern will be the same as that shown in FIG. 1. Since the structure of the present invention has been described in fig. 1, the description will not be repeated here.

In addition, the pattern of the present invention has the following features (please refer to fig. 1 to fig. 6 together):

as shown in fig. 1, the closed pattern (active layer 150) has a first boundary S1 extending along the horizontal direction (X-axis direction), the closed pattern (active layer 150) has a second boundary S2 extending along the vertical direction (Y-axis direction), and the closed pattern (active layer 150) has a third boundary S3 extending along the first direction D1.

As shown in fig. 1, the edge portions of the closed pattern (active layer 150) have different widths, wherein the largest width is denoted as W, at the intersection of the branch structure 107 and the closed boundary structure 106.

As shown in fig. 1, the closed patterns (active layers 150) have different widths, wherein the maximum width W is greater than 1.3 times and not greater than 2 times the width W' of the short side of the diagonal member unit.

As shown in fig. 1, the length of the first portion 107a (designated as L1) of the branch structure 107 is different from the length of the second portion 107b (designated as L2). Wherein the above-mentioned length of the branch structure arranged along the first direction D1, i.e. the length of the first portion 107a, is 2-8 times larger than the length of the branch structure arranged along the second direction (e.g. the Y-axis direction), i.e. the length of the branch structure of the second portion 107b, the ratio of the length of the branch structure of the first portion 107a to the length of the branch structure of the second portion 107 b.

As shown in fig. 3, at least one of the closed pattern active regions (e.g., the portion of the spacer pattern 14 indicated in fig. 3 that is subsequently etched to become the active region) includes irregular polygons of more than a hexagonal shape.

The above description is only a preferred embodiment of the present application and is not intended to limit the present application, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for forming an active area structure, comprising:

forming a plurality of sacrificial patterns over a substrate, wherein at least some of the sacrificial patterns comprise a horizontal portion and a vertical portion, wherein the horizontal portion of at least some of the sacrificial patterns is aligned with the horizontal portion of another adjacent sacrificial pattern in a horizontal direction, and the vertical portion of at least some of the sacrificial patterns is aligned with the vertical portion of another adjacent sacrificial pattern in a vertical direction; and

forming a plurality of spacer patterns, each of the spacer patterns surrounding a periphery of one of the sacrificial patterns.

2. The method of claim 1, wherein each of the spacer patterns is a closed sub-pattern as viewed in a front view.

3. The method of claim 2, wherein a plurality of said spacer patterns are in contact with each other and form a closed pattern.

4. The method of claim 3, wherein the closed pattern comprises a closed edge portion, and wherein the plurality of diagonal portions are located in an area within the closed edge portion.

5. The method of claim 4, wherein the plurality of diagonal portions are aligned along a first direction, wherein the first direction is different from the horizontal direction and the vertical direction.

6. The method of claim 4, wherein the closed edge portion comprises a plurality of borders, wherein at least one of the borders extends along the horizontal direction and at least one of the borders extends along the vertical direction.

7. The method of claim 1, further comprising performing a first etching step to remove the sacrificial patterns after the spacer patterns are formed.

8. The method of claim 7, further comprising the step of forming a material layer between the substrate and the plurality of spacer patterns.

9. The method of claim 8, further comprising performing a second etching step using the spacer patterns as a mask to transfer the spacer patterns into the material layer.

10. An active area structure, comprising:

a device region and a peripheral active region, wherein the device region comprises: a plurality of closed pattern active regions on a substrate, the plurality of closed pattern active regions being in contact with each other and constituting a closed pattern, wherein a first boundary of the closed pattern extends along a horizontal direction, a second boundary of the closed pattern extends along a vertical direction, the device region further including a plurality of device units;

the active area structure further comprises a shallow trench insulation layer for insulating the element unit and isolating the element unit with respect to the peripheral active area.

11. The active area structure of claim 10, further comprising a plurality of diagonal component elements disposed within the closed pattern, wherein the plurality of diagonal component elements do not contact the closed pattern, wherein the plurality of diagonal component elements are arranged along a first direction, wherein the first direction is different from the horizontal direction and the vertical direction.

12. The active area structure of claim 11, wherein the closed pattern comprises the first boundary, the second boundary, and a third boundary extending along the first direction.

13. The active area structure of claim 10, wherein at least one of the closed pattern active areas comprises an irregular polygon having a hexagonal or more.

14. The active area structure of claim 11, wherein the closed patterns have different widths, wherein a maximum width is greater than 1.3 times and not greater than 2 times a width of a short side of the diagonal member unit.

15. An active area structure, comprising:

a device region and a peripheral active region, wherein the device region comprises: a closed pattern active region on a substrate and a plurality of component units, the closed pattern comprising:

a closed edge portion, and a plurality of diagonal module units located in an area within the closed edge portion, the plurality of diagonal module units being arranged along a first direction; and

at least one branch structure contacting an edge portion of the closed pattern active region and extending toward an inside of the closed pattern active region; the branch structure comprises a first part and a second part, wherein the first part is arranged along the first direction, and the second part is arranged along a second direction different from the first direction;

16. The active area structure of claim 15, further comprising at least one closed sub-pattern within the closed edge portion.

17. The active area structure of claim 15, wherein a first boundary of the closed pattern extends along a horizontal direction, a second boundary of the closed pattern extends along a vertical direction, and a third boundary of the closed pattern extends along the first direction.

18. The active area structure of claim 15, wherein the closed edge portions have different widths, with a maximum width being located at an intersection of the branch structure and the closed edge portion.

19. The active area structure of claim 15, wherein the first portion and the second portion of the branch structure are not the same length.

20. The active area structure of claim 19, wherein the length of the branch structures aligned along the first direction is 2 to 8 times the length of the branch structures aligned along the second direction.