CN110648964A - Method for repairing fuse circuit of chip - Google Patents
Method for repairing fuse circuit of chip Download PDFInfo
- Publication number
- CN110648964A CN110648964A CN201911058430.8A CN201911058430A CN110648964A CN 110648964 A CN110648964 A CN 110648964A CN 201911058430 A CN201911058430 A CN 201911058430A CN 110648964 A CN110648964 A CN 110648964A
- Authority
- CN
- China
- Prior art keywords
- chip
- fuse
- polished
- fuse circuit
- breakpoint
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76886—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances
- H01L21/76892—Modifying permanently or temporarily the pattern or the conductivity of conductive members, e.g. formation of alloys, reduction of contact resistances modifying the pattern
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/525—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
- H01L23/5256—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
Abstract
The application discloses a method for repairing fuse circuit of a chip, which relates to the field of semiconductor manufacturing and comprises the following steps: obtaining a fuse circuit position on the chip according to the layout design information corresponding to the chip; polishing the side surface of the chip corresponding to the fuse circuit position; determining two breakpoint positions of a fuse line on the polished side surface of the chip; selectively etching the positions of the two breakpoints; depositing metal Pt on the side surface of the polished chip, wherein the metal Pt is connected with two break points of the fuse wire; the problems that other circuit functions of a chip are easily damaged and the repair rate is low in the existing repair method of the fuses circuit are solved; the effects of reducing the windowing area, not damaging the circuit structure on the upper layer of the fuse wire and improving the repair rate are achieved.
Description
Technical Field
The application relates to the technical field of semiconductor manufacturing, in particular to a method for repairing a fuse circuit of a chip.
Background
Currently, integrated circuit chips, particularly smart card platform chips, are provided with fuse circuits. The fuse is generally a signal line related to function control inside the chip, and provides a back gate function of the chip in a debugging stage. The fuse line 12 of each die 11 extends into the scribe line 13 on the wafer, as shown in fig. 1, and can be cut off during the chip de-scribing process to close the back door function.
However, occasionally faults occur in the back-end application process, and in order to debug a faulty chip, fuse circuits of the chip need to be repaired. The fuse lines of most of the existing products use poly (polysilicon) layers, the line repair from the surface needs to destroy more hierarchical structures, the windowing area is large, the influence on other circuit functions of the chip is easy to cause, and the repair success rate is reduced.
Disclosure of Invention
The application provides a method for repairing a fuse circuit of a chip, which can solve the problem of low repairing success rate when repairing a fuse wire in the related technology.
In one aspect, an embodiment of the present application provides a method for repairing a fuse circuit of a chip, where the method includes:
obtaining a fuse circuit position on the chip according to the layout design information corresponding to the chip;
polishing the side surface of the chip corresponding to the fuse circuit position;
determining two breakpoint positions of a fuse line on the polished side surface of the chip;
selectively etching the positions of the two breakpoints;
and depositing metal Pt on the side surface of the polished chip, wherein the metal Pt is connected with two break points of the fuse wire.
Optionally, polishing the side surface of the chip corresponding to the fuse circuit position includes:
fixing the chip on the carrier;
and polishing the side surface of the chip corresponding to the fuse circuit position in a Chemical Mechanical Polishing (CMP) mode.
Optionally, determining two breakpoint positions of the fuse line on the polished side surface of the chip includes:
putting the polished chip into focused ion beam FIB equipment;
the two breakpoint positions of the fuse line on the polished side surface of the chip were determined by the FIB apparatus.
Optionally, the selective etching is performed on the two breakpoint positions, and includes:
and selectively etching the positions of the two breakpoints by using FIB equipment.
Optionally, before obtaining the fuse circuit position on the chip according to the layout design information corresponding to the chip, the method further includes:
and deblocking the packaged product to obtain the chip.
Optionally, depositing metal Pt on the polished side surface of the chip, including:
and depositing metal Pt on a predetermined area of the polished side surface of the chip by an FIB device, wherein the predetermined area comprises two break points of the fuse line, and the area of the predetermined area is smaller than that of the side surface of the chip.
Optionally, selectively etching the two breakpoint positions by using FIB equipment, including:
determining a scanning strategy, an ion beam type, ion energy and ion beam current according to the substrate material of the chip and the size characteristics of the two breakpoint positions;
and in the FIB equipment, selectively etching the positions of the two breakpoints by utilizing a gas selective etching mode.
Optionally, the fuse line is a poly hierarchical structure.
The technical scheme at least comprises the following advantages:
obtaining a fuse circuit position on a chip according to layout design information corresponding to the chip, polishing a side surface of the chip corresponding to the fuse circuit position, determining two breakpoint positions of a fuse line on the polished side surface of the chip, selectively etching the two breakpoint positions, depositing metal Pt on the polished side surface of the chip, wherein the metal Pt is connected with the two breakpoints of the fuse line; the problems that other circuit functions of a chip are easily damaged and the repair rate is low in the existing repair method of the fuses circuit are solved; the effects of reducing the windowing area, not damaging the circuit structure on the upper layer of the fuse wire and improving the repair rate are achieved.
Drawings
In order to more clearly illustrate the detailed description of the present application or the technical solutions in the prior art, the drawings needed to be used in the detailed description of the present application or the prior art description will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative efforts.
FIG. 1 is a partial schematic view of a wafer;
FIG. 2 is a flowchart of a method for repairing a fuse circuit of a chip according to an embodiment of the present disclosure;
FIG. 3 is a flow chart of another method for repairing a fuse circuit of a chip according to an embodiment of the present disclosure;
FIG. 4 is a schematic diagram of a chip to be repaired before polishing according to an embodiment of the present disclosure;
FIG. 5 is a schematic diagram of a chip to be repaired after polishing according to an embodiment of the present disclosure;
FIG. 6 is a schematic side view of a polished chip to be repaired according to an embodiment of the present application;
FIG. 7 is a schematic diagram of a side surface of a chip after fuse circuit repair in an embodiment of the present application;
fig. 8 is an enlarged schematic view at a in fig. 7.
Detailed Description
The technical solutions in the present application will be described clearly and completely with reference to the accompanying drawings, and it is obvious that the described embodiments are some, but not all embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of description and simplicity of description, and do not indicate or imply that the device or element being referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus, should not be construed as limiting the present application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present application, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; the connection can be mechanical connection or electrical connection; the two elements may be directly connected or indirectly connected through an intermediate medium, or may be communicated with each other inside the two elements, or may be wirelessly connected or wired connected. The specific meaning of the above terms in the present application can be understood in a specific case by those of ordinary skill in the art.
In addition, the technical features mentioned in the different embodiments of the present application described below may be combined with each other as long as they do not conflict with each other.
Referring to fig. 2, a flowchart of a method for repairing a fuse circuit of a chip according to an embodiment of the present disclosure is shown. As shown in fig. 2, the method for repairing the fuse circuit of the chip may include the steps of:
And determining layout design information corresponding to the chip according to the model of the chip, and acquiring the fuse circuit position on the chip according to the layout design information.
The fuse circuit location is the location of the fuse circuit in the chip. The fuse circuit position is used to determine the chip side surface where the break point of the fuse line is located.
And step 202, polishing the side surface of the chip corresponding to the fuse circuit position.
The stains on the side surface of the chip were removed by polishing.
In step 203, two breakpoint positions of the fuse line on the polished side surface of the chip are determined.
The breakpoint position is the position at which the breakpoint of the fuse line is located.
And step 204, selectively etching the positions of the two breakpoints.
And step 205, depositing metal Pt on the side surface of the polished chip, wherein the metal Pt is connected with two break points of the fuse wire.
And (3) depositing metal Pt on the side surface of the polished chip, and shorting two break points of the fuse wire to finish the repair of the fuse circuit.
In summary, in the embodiment of the present application, the fuse circuit position on the chip is obtained according to the layout design information corresponding to the chip, the side surface of the chip corresponding to the fuse circuit position is polished, two breakpoint positions of the fuse line on the polished side surface of the chip are determined, the two breakpoint positions are selectively etched, metal Pt is deposited on the polished side surface of the chip, and the metal Pt is connected with the two breakpoints of the fuse line; the problems that other circuit functions of a chip are easily damaged and the repair rate is low in the existing repair method of the fuses circuit are solved; the effects of reducing the windowing area, not damaging the circuit structure on the upper layer of the fuse wire and improving the repair rate are achieved.
Referring to fig. 3, a flowchart of another method for repairing a fuse circuit of a chip according to an embodiment of the present disclosure is shown. As shown in fig. 3, the method for repairing the fuse circuit of the chip may include the steps of:
and step 301, unsealing the packaged product to obtain the chip.
And deblocking the packaged product of the fault chip needing to be debugged again to obtain the chip to be repaired.
And 302, acquiring a fuse circuit position on the chip according to the layout design information corresponding to the chip.
And determining layout design information corresponding to the chip according to the model of the chip, and acquiring the fuse circuit position on the chip according to the layout design information.
The fuse circuit position is used to determine the chip side surface where the break point of the fuse line is located. The fuse line is a poly hierarchical structure.
And step 303, polishing the side surface of the chip corresponding to the fuse circuit position.
As shown in FIG. 4, since the surface of the chip 41 has the stains 42, the position of the break point of the fuse line on the side surface of the chip corresponding to the fuses circuit is not obvious, and the side surface of the chip needs to be polished.
Optionally, the chip is fixed on the carrier, and a side surface of the chip corresponding to the position of the fuse circuit is polished by a CMP (Chemical Mechanical Polishing).
The FIB (Focused Ion Beam) etching process uses high-energy Ion beams to bombard the surface of a material to remove the material, so as to directly process the micro-nano structure.
After polishing the side surface of the chip corresponding to the position of the fuse circuit, the chip was placed in the FIB apparatus.
At step 305, two breakpoint positions of the fuse line on the polished side surface of the chip are determined by the FIB device.
The polished chip was used to determine two break point positions 51, 52 of the fuse line on the side surface of the chip 41 by the FIB device as shown in fig. 5 and 6.
And step 306, selectively etching the two breakpoint positions by using FIB equipment.
Optionally, determining a scanning strategy of selective etching, an ion beam type, ion energy and ion beam current according to the substrate material of the chip and the size characteristics of the two breakpoint positions; in the FIB equipment, two breakpoint positions of a fuse line on the side surface of a chip are selectively etched by utilizing a gas selective etching mode.
In the etching process, reaction gas is sprayed to an etching area on the surface of a sample, the gas adsorbed on the side surface of the chip is induced by the high-energy ion beam to carry out chemical reaction with the materials at the two breakpoint positions, and generated volatile reactants are pumped away by a vacuum pump.
The predetermined region includes two break points of the fuse line, and the area of the predetermined region is smaller than the area of the chip side surface.
As shown in fig. 7 and 8, the metal Pt is deposited in the predetermined region 53 on the side surface of the chip, the metal Pt connects the break point 51 and the break point 52 of the fuse line, and the fuse circuit is directly repaired without destroying the upper circuit structure of the fuse line by depositing the metal Pt short break point 51 and the break point 52 on the side surface of the chip corresponding to the fuse circuit.
In the process of depositing the metal Pt, selecting corresponding inducing gas according to the metal Pt to be deposited, introducing the inducing gas into an FIB incident area, adsorbing the introduced inducing gas on the side surface of the chip in a monomolecular layer mode, decomposing adsorbed gas molecules by bombardment of incident ion beams, and leaving the metal Pt in a preset area on the side surface of the chip.
To sum up, in the embodiment of the present application, a chip to be repaired is obtained by performing decapsulation on a product to be repaired, a fuse circuit position on the chip is obtained according to layout design information corresponding to the chip, a chip side surface corresponding to the fuse circuit position is polished, two breakpoint positions of a fuse line on the chip side surface corresponding to the fuse circuit position are determined by FIB equipment, the two breakpoint positions of the fuse line on the chip side surface are selectively etched by FIB equipment, metal Pt is deposited in a predetermined area on the chip side surface, and the deposited metal Pt is short-circuited with the two breakpoints of the fuse line; the windowing area in the fuse circuit repairing process is reduced, other functional circuits on the upper layer of the fuse line are not damaged, the chip is prevented from being broken down again in the fuse circuit repairing process, and the repairing rate is improved.
It should be understood that the above examples are only for clarity of illustration and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art in light of the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications of this invention are intended to be covered by the scope of the invention as expressed herein.
Claims (8)
1. A method of repairing a fuse circuit of a chip, the method comprising:
obtaining a fuse circuit position on the chip according to the layout design information corresponding to the chip;
polishing the side surface of the chip corresponding to the fuse circuit position;
determining two breakpoint positions of a fuse line on the polished side surface of the chip;
selectively etching the positions of the two breakpoints;
and depositing metal Pt on the side surface of the polished chip, wherein the metal Pt is connected with two break points of the fuse wire.
2. The method of claim 1, wherein polishing the chip side surface corresponding to the fuse circuit location comprises:
fixing the chip to a carrier;
and polishing the side surface of the chip corresponding to the fuse circuit position in a Chemical Mechanical Polishing (CMP) mode.
3. The method of claim 1, wherein said determining two breakpoint locations for a fuse line on a polished side surface of the chip comprises:
putting the polished chip into focused ion beam FIB equipment;
determining two breakpoint positions of a fuse line on the polished side surface of the chip by the FIB apparatus.
4. The method of claim 1, wherein the selectively etching the two breakpoint locations comprises:
and selectively etching the two breakpoint positions by using FIB equipment.
5. The method according to claim 1, before obtaining the fuse circuit position on the chip according to the layout design information corresponding to the chip, further comprising:
and deblocking the packaged product to obtain the chip.
6. The method of claim 1, wherein said depositing metal Pt on said polished chip side surface comprises:
depositing metal Pt on a predetermined area of the polished chip side surface by an FIB device, wherein the predetermined area comprises two break points of the fuse line, and the area of the predetermined area is smaller than that of the chip side surface.
7. The method of claim 4, wherein the selectively etching the two breakpoint locations with the FIB device comprises:
determining a scanning strategy of selective etching, an ion beam type, ion energy and ion beam current according to the substrate material of the chip and the size characteristics of the two breakpoint positions;
and selectively etching the two breakpoint positions in the FIB equipment by utilizing a gas selective etching mode.
8. The method of any one of claims 1 to 7, wherein the fuse line is a poly hierarchy.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911058430.8A CN110648964A (en) | 2019-10-30 | 2019-10-30 | Method for repairing fuse circuit of chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911058430.8A CN110648964A (en) | 2019-10-30 | 2019-10-30 | Method for repairing fuse circuit of chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110648964A true CN110648964A (en) | 2020-01-03 |
Family
ID=68995402
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201911058430.8A Pending CN110648964A (en) | 2019-10-30 | 2019-10-30 | Method for repairing fuse circuit of chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110648964A (en) |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR0151383B1 (en) * | 1994-06-16 | 1998-10-01 | 문정환 | Programmable semiconductor device with anti-fuse and manufacturing method thereof |
| CN1393932A (en) * | 2001-06-26 | 2003-01-29 | 株式会社东芝 | Semiconductor chip with fuse element |
| KR20060066500A (en) * | 2004-12-13 | 2006-06-16 | 삼성전자주식회사 | Semiconductor device |
| CN103227167A (en) * | 2013-04-08 | 2013-07-31 | 北京昆腾微电子有限公司 | Chip and test mode protection circuit and method of chip |
| CN103426848A (en) * | 2012-05-25 | 2013-12-04 | 北大方正集团有限公司 | Chip and manufacturing method thereof |
| CN107093565A (en) * | 2017-04-07 | 2017-08-25 | 中国电子产品可靠性与环境试验研究所 | The amending method of the integrated circuit of Flip-Chip Using |
| CN107622991A (en) * | 2016-07-14 | 2018-01-23 | 联华电子股份有限公司 | Electric fuse structure and preparation method thereof |
| CN107861047A (en) * | 2017-11-01 | 2018-03-30 | 北京智芯微电子科技有限公司 | The detecting system and detection method of safety test pattern |
-
2019
- 2019-10-30 CN CN201911058430.8A patent/CN110648964A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR0151383B1 (en) * | 1994-06-16 | 1998-10-01 | 문정환 | Programmable semiconductor device with anti-fuse and manufacturing method thereof |
| CN1393932A (en) * | 2001-06-26 | 2003-01-29 | 株式会社东芝 | Semiconductor chip with fuse element |
| KR20060066500A (en) * | 2004-12-13 | 2006-06-16 | 삼성전자주식회사 | Semiconductor device |
| CN103426848A (en) * | 2012-05-25 | 2013-12-04 | 北大方正集团有限公司 | Chip and manufacturing method thereof |
| CN103227167A (en) * | 2013-04-08 | 2013-07-31 | 北京昆腾微电子有限公司 | Chip and test mode protection circuit and method of chip |
| CN107622991A (en) * | 2016-07-14 | 2018-01-23 | 联华电子股份有限公司 | Electric fuse structure and preparation method thereof |
| CN107093565A (en) * | 2017-04-07 | 2017-08-25 | 中国电子产品可靠性与环境试验研究所 | The amending method of the integrated circuit of Flip-Chip Using |
| CN107861047A (en) * | 2017-11-01 | 2018-03-30 | 北京智芯微电子科技有限公司 | The detecting system and detection method of safety test pattern |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11367652B2 (en) | Microelectronic assembly from processed substrate | |
| CN110648964A (en) | Method for repairing fuse circuit of chip | |
| US20120091557A1 (en) | Anti-fuse of semiconductor device and method for manufacturing the same | |
| JP2007036252A (en) | Semiconductor device with enhanced pad structure and pad forming method of semiconductor device | |
| KR20120103982A (en) | Fuse pattern and method for manufacturing the same | |
| US20120012943A1 (en) | Anti-fuse of semiconductor device and method of manufacturing the same | |
| US6319733B1 (en) | Method of manufacturing semiconductor device, semiconductor equipment and manufacturing system | |
| US7253093B2 (en) | Method for fabricating interconnection in an insulating layer on a wafer | |
| CN111883555B (en) | Integrated circuit repairing method | |
| JP4983006B2 (en) | Substrate inspection apparatus and method | |
| KR100778860B1 (en) | Method for analyzing defects of semiconductor device | |
| KR100752662B1 (en) | Semiconductor device including fuse and method of identifying the cutting of fuse | |
| US20070264874A1 (en) | Fuse structure of a semiconductor device and method of manufacturing the same | |
| KR101159677B1 (en) | Method for Manufacturing Anti-Fuse of Semiconductor Device | |
| KR100998947B1 (en) | Method for manufacturing semiconductor device with fuse and pad | |
| JPH06216255A (en) | Wafer inspection of semiconductor device with redundancy circuit | |
| CN113097084A (en) | Method for exposing metal layer and circuit repairing method | |
| KR100861305B1 (en) | Method of manufacturing semiconductor device | |
| KR101150554B1 (en) | Semiconductor Device and Method for Manufacturing the same | |
| KR101128896B1 (en) | Anti-fuse of semiconductor device and method for manufacturing the same | |
| KR101102048B1 (en) | The fuse of semicondutor device and method for fabricating the same | |
| KR20090076140A (en) | Method for forming a fuse of semiconductor device | |
| KR20040108223A (en) | Method of manufacturing semiconductor device including 2-step etching for forming fuse cutting hole | |
| KR20070079804A (en) | Method for manufacturing of semiconductor device | |
| KR20110076242A (en) | The semiconductor device and method for manufacturing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20200103 |
|
| RJ01 | Rejection of invention patent application after publication |