CN110647256A - Manufacturing method of In-cell touch panel - Google Patents
Manufacturing method of In-cell touch panel Download PDFInfo
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- CN110647256A CN110647256A CN201910938192.3A CN201910938192A CN110647256A CN 110647256 A CN110647256 A CN 110647256A CN 201910938192 A CN201910938192 A CN 201910938192A CN 110647256 A CN110647256 A CN 110647256A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/01—Input arrangements or combined input and output arrangements for interaction between user and computer
- G06F3/03—Arrangements for converting the position or the displacement of a member into a coded form
- G06F3/041—Digitisers, e.g. for touch screens or touch pads, characterised by the transducing means
- G06F3/0412—Digitisers structurally integrated in a display
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2203/00—Indexing scheme relating to G06F3/00 - G06F3/048
- G06F2203/041—Indexing scheme relating to G06F3/041 - G06F3/045
- G06F2203/04103—Manufacturing, i.e. details related to manufacturing processes specially suited for touch sensitive devices
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Abstract
The invention provides a method for manufacturing an In-cell touch panel, the In-cell touch panel comprises a pixel area and a terminal area, by adding a composite inorganic layer on the organic insulating layer, the problem of Undercut (underrout) of the organic insulating layer formed by etching the organic insulating layer in the process of the second halftone mask is solved, the product quality is improved, meanwhile, because the oxide semiconductor material layer is added on the third metal layer, the annealing process of the first transparent electrode layer can be performed immediately after the photoresist is stripped, and the annealing is carried out after the insulating layer is not required to be deposited, so that the time required by the annealing process of the pixel electrode is reduced, the transmittance of the pixel electrode is improved, and meanwhile, the oxide semiconductor material layer is convenient to remove after the annealing is finished, the invention has no other influence on the product structure, is beneficial to improving the production efficiency and the product quality and reduces the production cost.
Description
Technical Field
The invention relates to the technical field of display panels, In particular to a manufacturing method of an In-cell touch panel.
Background
Currently, the existing In-Cell touch screen detects the touch position of a finger by using the principle of mutual capacitance or self-capacitance. The touch position can be judged by detecting the capacitance value change of each capacitance electrode in the touch time period by the touch detection chip.
In order to sense the capacitance change of a self-capacitance electrode, a lead is required to connect a touch chip and the self-capacitance electrode, the lead is generally used as a touch line, for FFS (fringe field switching) liquid crystal display, the implementation modes of the touch line are mainly divided into two modes, the first mode is that the touch line is completed through a source and drain metal layer, namely a second metal layer is required to be a source and drain electrode and wiring thereof and is also required to be a touch line, and the touch line is parallel to a data line; the second is to add a third metal layer and its corresponding insulating protection layer, and to connect the touch sensing chip and the self-capacitance electrode by patterning the third metal layer, because an organic insulating layer (JAS) is generally disposed above the data line, and the thickness of the organic insulating layer generally exceeds 2 μm, the touch lines of the third metal layer can be crossed at will without worrying about parasitic capacitance between the touch lines and the data line, and thus the aperture ratio is higher than that of the touch lines and the data line disposed on the same layer.
In addition, In-cell (In-cell) needs to realize a display function In a display time besides a touch function, generally, a self-capacitance electrode is divided into blocks by a common electrode, the self-capacitance electrode is arranged on the same layer and is arranged In a time-sharing multiplexing mode, namely, In a display stage, a common electrode signal is loaded on the self-capacitance electrode, a touch line is connected with the self-capacitance electrode during touch, the common touch line and the self-capacitance electrode are arranged on different layers, a protective layer is arranged between the common touch line and the self-capacitance electrode, the common touch line and the self-capacitance electrode are connected through a contact hole, meanwhile, the touch line is connected with a touch detection chip, and the capacitance change of the.
Because the FFS lcd panel is manufactured by using two layers of Indium Tin Oxide (ITO), the manufacturing process of the FFS lcd panel is one to two mask processes more than that of the general lcd panel. In addition, M3(Sensor line) is required to connect the self-capacitance electrode and the touch chip, which results in a larger number of light masks and higher cost.
Disclosure of Invention
The invention aims to provide a method for manufacturing an In-cell touch panel, which is beneficial to improving the production efficiency and the product quality and reducing the production cost.
The invention provides a method for manufacturing an In-cell touch panel, wherein the In-cell touch panel comprises a pixel area and a terminal area, and the method comprises the following steps:
s1: depositing a first metal layer on a substrate, and forming a scanning line positioned in a terminal area and a grid positioned in a pixel area through exposure, development and etching;
s2: forming a gate insulating layer covering the first metal layer on the basis of the step S1;
s3: sequentially forming a semiconductor material layer and a second metal layer on the basis of the step S2, and performing multi-level exposure, development and etching on the semiconductor material layer and the second metal layer through a half-tone mask to form a data line positioned in the terminal area, and a source electrode, a drain electrode and a semiconductor layer positioned in the pixel area;
s4: sequentially forming a stacked structure of a first insulating layer and an organic insulating layer on the basis of step S3, and forming a first contact hole located in the pixel region and a second contact hole located in the terminal region by exposing, developing, and etching the organic insulating layer, respectively;
s5: depositing a composite inorganic insulating layer on the basis of the step S4, wherein the composite inorganic insulating layer comprises a bottom insulating layer and a top insulating layer, the bottom insulating layer is made of SiNx, and the top insulating layer is made of SiO 2;
s6: etching all the composite inorganic insulating layer and the first insulating layer in the first contact hole and etching part of the composite inorganic insulating layer, the first insulating layer and part of the gate insulating layer in the second contact hole by using a mask of the first insulating layer on the basis of the step S5;
s7: a stacked structure of the first transparent electrode layer, the third metal layer, and the oxide semiconductor material layer is sequentially formed on the basis of step S6, and then the oxide semiconductor material layer, the third metal layer, and the first transparent electrode layer are subjected to multi-step exposure and development through a semi-transparent mask to form a pixel electrode and a touch line.
Preferably, the step S7 specifically includes the following steps:
s71: sequentially forming a stacked structure of a first transparent electrode layer, a third metal layer and an oxide semiconductor material layer on the basis of the step S6;
s72: coating photoresist on the oxide semiconductor material layer on the basis of the step S71, and forming a photoresist-free reserved area, a photoresist partial reserved area and a photoresist complete reserved area after exposing and developing the photoresist by adopting a semi-transparent mask;
s73: performing first etching on the oxide semiconductor material layer, the third metal layer and the first transparent electrode layer by using etching liquid containing fluorine copper acid on the basis of the step S72, so that parts of the third metal layer positioned at two sides of the photoresist-free reserved area are etched inwards;
s74: ashing the photoresist on the basis of the step S73, and etching the photoresist in the photoresist partial retention area until the oxide semiconductor material layer is exposed;
s75: etching away the oxide semiconductor material layer in the photoresist partial retention region by using oxalic acid etching on the basis of the step S74 to expose the third metal layer in the photoresist partial retention region;
s76: etching for the first time by adopting fluorine-containing copper acid on the basis of the step S75, etching the third metal layer of the photoresist partial reserved area, and undercutting both sides of the third metal layer of the photoresist complete reserved area;
s77: stripping the photoresist on the basis of step S76;
s78: annealing the first transparent electrode layer and forming a pixel electrode in the pixel region on the basis of step S77;
s79: the oxide semiconductor material layer on the third metal layer is stripped based on step S78, and the remaining third metal layer becomes a touch line.
Preferably, the photoresist partial retention area is located in an area where the pixel electrode is located, the photoresist complete retention area corresponds to an area where the touch line and the first contact hole are located, and the non-photoresist retention area is the remaining other area.
Preferably, the size of the photoresist complete reserve area corresponding to the first contact hole is larger than the upper surface area of the first contact hole and smaller than the vertical projection area of the drain electrode.
Preferably, the first metal layer and the third metal layer are made of copper, aluminum single-layer metal or two-layer metal with copper as an upper layer and molybdenum as a lower layer.
Preferably, the second metal layer is formed of a double-layer metal having an upper layer of copper and a lower layer of titanium or an upper layer of copper and a lower layer of molybdenum.
Preferably, the gate insulating layer, the first insulating layer, and the second insulating layer are composed of silicon oxide, silicon nitride, or a mixture of silicon oxide and silicon nitride.
Preferably, the method further comprises the following steps:
s8: depositing a second insulating layer on the basis of the step S7, exposing the conductive lines above the touch lines of the pixel region and the data lines of the terminal region by exposure, development and etching;
s9: a second transparent electrode is formed on the basis of step S8, and an individual common electrode is formed by exposure, development, and etching.
Preferably, the specific steps of step S3 are: and sequentially forming a semiconductor material layer and a second metal layer on the basis of the step S2, and performing multi-level exposure, development and etching on the semiconductor material layer and the second metal layer through a half-tone mask to form a data line located in the terminal area, and a source electrode, a drain electrode and a semiconductor located in the pixel area.
The invention solves the problem of Undercut (underrout) of the organic insulating layer caused by etching the organic insulating layer in the process of the second half-tone mask, improves the product quality, simultaneously, because the oxide semiconductor material layer is newly added on the third metal layer, the first transparent electrode layer can be immediately carried out after the photoresistance is stripped in the annealing process without carrying out annealing after the insulating layer is deposited, reduces the time required by the annealing process of the pixel electrode and improves the transmittance of the pixel electrode, and simultaneously, the oxide semiconductor material layer is convenient to remove after the annealing is finished, and has no other influence on the product structure.
Drawings
Fig. 1 to 11 are schematic views illustrating manufacturing steps of the method for manufacturing an In-cell touch panel according to the present invention.
Detailed Description
The present invention is further illustrated by the following figures and specific examples, which are to be understood as illustrative only and not as limiting the scope of the invention, which is to be given the full breadth of the appended claims and any and all equivalent modifications thereof which may occur to those skilled in the art upon reading the present specification.
For the sake of simplicity, the drawings only schematically show the parts relevant to the present invention, and they do not represent the actual structure as a product. In addition, in order to make the drawings concise and understandable, components having the same structure or function in some of the drawings are only schematically illustrated or only labeled. In this document, "one" means not only "only one" but also a case of "more than one".
The invention discloses a method for manufacturing an In-cell touch panel, wherein the In-cell touch panel comprises a pixel area 100 and a terminal area 200, and the method comprises the following steps:
s1: as shown in fig. 1, fig. 1 is a schematic diagram, a first metal layer is deposited on a substrate 10, and a scan line 21 located in a terminal area and a gate 22 located in a pixel area 100 are formed by exposure, development and etching;
s2: as shown in fig. 1, a gate insulating layer 23 covering the first metal layer is formed on the basis of step S1;
s3: as shown in fig. 1, a semiconductor material layer and a second metal layer are sequentially formed on the basis of step S2, and the data line 31 located in the terminal area 200, and the source electrode 32, the drain electrode 33 and the semiconductor layer 34 located in the pixel area 100 are formed by performing multi-step exposure, development and etching on the semiconductor material layer and the second metal layer through a halftone mask (i.e., a first halftone mask);
the source electrode 32, the drain electrode 33 and the data line 31 are in an overlapped structure of a semiconductor layer and a second metal layer, and only the semiconductor layer is reserved in the channel region;
s4: sequentially forming a stacked structure of the first insulating layer 41(PAS1) and the organic insulating layer 42 (JAS) on the basis of step S3, forming the first contact hole 51 located at the pixel region and the second contact hole 52 located at the terminal region by exposing, developing, and etching the organic insulating layer 42, respectively, exposing the first insulating layer 41 in the first contact hole 41 and the second contact hole 42;
s5: as shown in fig. 2, a composite inorganic insulating layer 51(PAS3) is deposited on the basis of step S4;
the composite inorganic insulating layer 51 is a third insulating layer having a stacked structure and including a bottom insulating layer 511 and a top insulating layer 512, the bottom insulating layer 511 is made of SiNx, and the thickness of the bottom insulating layer 511 is not less than that of the bottom insulating layer 511The top insulating layer 512 is formed of SiO2, and the thickness of the top insulating layer 512 is also setNot less than
The SiNx can protect the organic insulating layer 42 from being corroded by N2O gas generated in SiO2 film forming process, the SiO2 can protect the etching liquid from etching the lower SiNx layer when the third metal layer and the first transparent electrode layer are etched to form patterns, and the bottom SiNx layer can prevent the top SiO2 from corroding the lower organic insulating layer 42 in the film forming process.
S6: etching away all the composite inorganic insulating layer 51 and the first insulating layer 41 in the first contact hole 51 and etching away part of the composite inorganic insulating layer 51, the first insulating layer 41 and part of the gate insulating layer 23 in the second contact hole 52 using a mask of the first insulating layer on the basis of the step S5; exposing the drain electrode 33 in the first contact hole 51 in the pixel region 100; the scan line 21 and the data line 31 are exposed in the second contact hole 52 in the terminal area 100;
s7: as shown in fig. 3, a stacked structure of the first transparent electrode layer 61, the third metal layer 62 and the oxide semiconductor material layer 63 is sequentially formed on the basis of step S6, as shown in fig. 11, and then the oxide semiconductor material layer 63, the third metal layer 62 and the first transparent electrode layer 61 are subjected to multi-step exposure and development through a semi-transparent mask (not shown), i.e., a second halftone mask, to form a pixel electrode 611, a connection electrode (not shown) of the pixel electrode 611 and the drain electrode 33 and a touch line 621 located in the pixel area 100, wherein the touch line 621 is used for connecting a touch detection chip (not shown) and a self-capacitance electrode (not shown);
wherein the oxide semiconductor material is IGZO, IZO, MgZnO, TiO2 or IGO.
S8: depositing a second insulating layer on the basis of step S7, exposing the conductive lines (not shown) above the touch lines 621 of the pixel region and the data lines of the terminal region by exposing, developing and etching;
s9: a second transparent electrode is formed on the basis of step S8, and an independent common electrode (not shown) is formed by exposure, development, and etching.
Wherein, step S7 specifically includes the following steps:
s71: as shown in fig. 3, a stacked structure of the first transparent electrode layer 61, the third metal layer 62, and the oxide semiconductor material layer 63 is formed in this order on the basis of step S6;
s72: as shown in fig. 4, a photoresist 70 is coated on the oxide semiconductor material layer 63 based on step S71, a semi-transparent mask (not shown) is used to expose and develop the photoresist 100, and then a photoresist-free reserved area 71, a photoresist-partially reserved area 71 and a photoresist-intact reserved area 73 are formed, wherein the photoresist-partially reserved area 71 is located in an area where the pixel electrode is located, the photoresist-intact reserved area 73 corresponds to an area where the touch line 621, the conductive line and the first contact hole 51 are located, and the photoresist-free reserved area 71 is the remaining other area; the size of the photoresist complete reserve region 73 corresponding to the first contact hole 51 is larger than the upper surface area of the first contact hole 51 and smaller than the vertical projection area of the drain electrode 32. The light transmittance of the photoresist portion-retaining region 71 is 10% to 50%.
S73: as shown in fig. 5, on the basis of step S72, the first etching is performed on the oxide semiconductor material layer 63, the third metal layer 62 and the first transparent electrode layer 61 by using an etching solution containing copper F acid, so that the third metal layer 62 on both sides of the photoresist-free retention region 71 is etched inward to remove a portion, as shown by the circle drawn in fig. 5;
wherein, the step S73 does not require etching using oxalic acid.
S74: as shown in fig. 6, the photoresist 70 is ashed on the basis of step S73, and the photoresist 70 in the photoresist partial-reserve region 71 is etched by passing oxygen until the oxide semiconductor material layer 63 is exposed;
the organic insulating layer 42 is not etched to form UnderCut due to the composite inorganic insulating layer 51 thereon.
S75: as shown in fig. 7, the oxide semiconductor material layer 63 of the photoresist portion-retaining region 71 is etched away by oxalic acid etching based on step S74 to expose the third metal layer 62 of the photoresist portion-retaining region 71;
s76: as shown in fig. 8, a first etching is performed by using copper acid containing F based on step S75, the third metal layer 62 of the photoresist partial-region 71 is etched away, and undercuts occur on both sides of the third metal layer 62 of the photoresist complete-region 73, as shown by the circled area in fig. 8;
the oxide semiconductor material layer 63 is disposed above the third metal layer 62 of the photoresist complete reserve region 73, so that the oxide semiconductor material layer 63 acts as the photoresist 70, and the size of the etching in the third metal layer 62 of the photoresist complete reserve region 73 can be controlled.
S77: as shown in fig. 9, the photoresist 70 is stripped on the basis of step S76;
s78: as shown in fig. 10, the first transparent electrode layer 61 is annealed on the basis of step S77 and a pixel electrode 611 is formed in the pixel region 100;
in the annealing process, the third metal layer 62 is protected from being oxidized by the oxide semiconductor material layer 63; the first transparent electrode layer 61 is directly on N2The same baking time as the existing ITO annealing process is adopted, and the same transmittance level can be achieved without increasing the Oven time.
S79: as shown in fig. 11, the oxide semiconductor material layer 63 on the third metal layer 62 is stripped based on step S78, and the remaining third metal layer 62 becomes the touch line 621.
The first metal layer, the second metal layer, the semiconductor material layer, the first transparent electrode layer and the second transparent electrode layer are formed by a physical sputtering deposition method; the gate insulating layer, the first insulating layer and the second insulating layer are formed by a chemical vapor deposition method, and the organic insulating layer is formed by a coating method.
The first metal layer and the third metal layer are made of single-layer metal of copper and aluminum or double-layer metal with the upper layer made of copper and the lower layer made of molybdenum; the second metal layer is composed of double-layer metal with copper as the upper layer and titanium as the lower layer or molybdenum as the upper layer and copper as the lower layer; the first transparent electrode and the second transparent electrode are made of indium tin oxide or nano silver wires; the grid insulating layer, the first insulating layer and the second insulating layer are made of silicon oxide and silicon nitride or a mixture of the silicon oxide and the silicon nitride, and the third insulating layer is made of a bottom silicon nitride and a top silicon oxide composite layer; the semiconductor material layer is made of an oxide semiconductor.
The thickness of the first metal layer is
The thickness of the gate insulating layer isThe thickness of the semiconductor layer material layer is
The thickness of the second metal layer and the third metal layer is
The first insulating layer and the second insulating layer have a thickness ofThe thickness of the third insulating layer is greater than
Thickness of organic insulating layer
The first transparent electrode layer and the second transparent electrode layer have a thickness of
The invention uses the first half-tone mask plate on the source electrode, the drain electrode and the semiconductor layer, uses the second half-tone mask plate on the first transparent electrode layer and the third metal layer, and after the organic insulating layer is patterned, deposits the third insulating layer, the third insulating layer adopts the composite inorganic insulating layer, reduces the total mask using amount in the manufacturing process of the array substrate, improves the aperture opening ratio of the display panel, improves the display effect, solves the problems of the first transparent electrode layer and the third metal layer, solves the problem of the organic insulating layer Undercut (Undercut) formed by etching the organic insulating layer in the second half-tone mask plate process, improves the product quality, and simultaneously, because the oxide semiconductor material layer is added on the third metal layer, the first transparent electrode layer can be immediately carried out after the light resistance stripping without annealing after the insulating layer is deposited, the time required by the annealing process of the pixel electrode is reduced, the transmittance of the pixel electrode is improved, the oxide semiconductor material layer is convenient to remove after the annealing is finished, and other influences on the product structure are not caused.
Although the preferred embodiments of the present invention have been described in detail, the present invention is not limited to the details of the foregoing embodiments, and various equivalent changes (such as number, shape, position, etc.) may be made to the technical solution of the present invention within the technical spirit of the present invention, and these equivalent changes are all within the protection scope of the present invention.
Claims (9)
1. A method for manufacturing an In-cell touch panel, the In-cell touch panel comprising a pixel region and a terminal region, the method comprising the steps of:
s1: depositing a first metal layer on a substrate, and forming a scanning line positioned in a terminal area and a grid positioned in a pixel area through exposure, development and etching;
s2: forming a gate insulating layer covering the first metal layer on the basis of the step S1;
s3: sequentially forming a semiconductor material layer and a second metal layer on the basis of the step S2, and performing multi-level exposure, development and etching on the semiconductor material layer and the second metal layer through a half-tone mask to form a data line positioned in the terminal area, and a source electrode, a drain electrode and a semiconductor layer positioned in the pixel area;
s4: sequentially forming a stacked structure of a first insulating layer and an organic insulating layer on the basis of step S3, and forming a first contact hole located in the pixel region and a second contact hole located in the terminal region by exposing, developing, and etching the organic insulating layer, respectively;
s5: depositing a composite inorganic insulating layer on the basis of the step S4, wherein the composite inorganic insulating layer comprises a bottom insulating layer and a top insulating layer, the bottom insulating layer is made of SiNx, and the top insulating layer is made of SiO 2;
s6: etching all the composite inorganic insulating layer and the first insulating layer in the first contact hole and etching part of the composite inorganic insulating layer, the first insulating layer and part of the gate insulating layer in the second contact hole by using a mask of the first insulating layer on the basis of the step S5;
s7: a stacked structure of the first transparent electrode layer, the third metal layer, and the oxide semiconductor material layer is sequentially formed on the basis of step S6, and then the oxide semiconductor material layer, the third metal layer, and the first transparent electrode layer are subjected to multi-step exposure and development through a semi-transparent mask to form a pixel electrode and a touch line.
2. The method for manufacturing an In-cell touch panel according to claim 1, wherein the step S7 specifically comprises the following steps:
s71: sequentially forming a stacked structure of a first transparent electrode layer, a third metal layer and an oxide semiconductor material layer on the basis of the step S6;
s72: coating photoresist on the oxide semiconductor material layer on the basis of the step S71, and forming a photoresist-free reserved area, a photoresist partial reserved area and a photoresist complete reserved area after exposing and developing the photoresist by adopting a semi-transparent mask;
s73: performing first etching on the oxide semiconductor material layer, the third metal layer and the first transparent electrode layer by using etching liquid containing fluorine copper acid on the basis of the step S72, so that parts of the third metal layer positioned at two sides of the photoresist-free reserved area are etched inwards;
s74: ashing the photoresist on the basis of the step S73, and etching the photoresist in the photoresist partial retention area until the oxide semiconductor material layer is exposed;
s75: etching away the oxide semiconductor material layer in the photoresist partial retention region by using oxalic acid etching on the basis of the step S74 to expose the third metal layer in the photoresist partial retention region;
s76: etching for the first time by adopting fluorine-containing copper acid on the basis of the step S75, etching the third metal layer of the photoresist partial reserved area, and undercutting both sides of the third metal layer of the photoresist complete reserved area;
s77: stripping the photoresist on the basis of step S76;
s78: annealing the first transparent electrode layer and forming a pixel electrode in the pixel region on the basis of step S77;
s79: the oxide semiconductor material layer on the third metal layer is stripped based on step S78, and the remaining third metal layer becomes a touch line.
3. The method of claim 2, wherein the photoresist partial retention region is located In a region where the pixel electrode is located, the photoresist complete retention region corresponds to a region where the touch line and the first contact hole are located, and the photoresist-free retention region is the remaining other region.
4. The method as claimed In claim 3, wherein the photoresist intact preservation region corresponding to the first contact hole has a size larger than the upper surface area of the first contact hole and smaller than the vertical projection area of the drain.
5. The method of claim 1, wherein the first metal layer and the third metal layer are made of a single layer metal of copper or aluminum or a double layer metal with an upper layer of copper and a lower layer of molybdenum.
6. The method of claim 1, wherein the second metal layer is made of a double-layer metal with an upper layer of copper and a lower layer of titanium or an upper layer of copper and a lower layer of molybdenum.
7. The method of claim 1, wherein the gate insulating layer, the first insulating layer, and the second insulating layer are made of silicon oxide, silicon nitride, or a mixture thereof.
8. The method of manufacturing an In-cell touch panel according to claim 1, further comprising the steps of:
s8: depositing a second insulating layer on the basis of the step S7, exposing the conductive lines above the touch lines of the pixel region and the data lines of the terminal region by exposure, development and etching;
s9: a second transparent electrode is formed on the basis of step S8, and an individual common electrode is formed by exposure, development, and etching.
9. The method of claim 1, wherein the step S3 comprises the following steps: and sequentially forming a semiconductor material layer and a second metal layer on the basis of the step S2, and performing multi-level exposure, development and etching on the semiconductor material layer and the second metal layer through a halftone mask to form a data line located in the terminal area, and a source electrode, a drain electrode and a semiconductor layer located in the pixel area.
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| CN201910938192.3A CN110647256A (en) | 2019-09-29 | 2019-09-29 | Manufacturing method of In-cell touch panel |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114721553A (en) * | 2022-06-06 | 2022-07-08 | 惠科股份有限公司 | Touch structure, OLED touch display panel and manufacturing method |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114721553A (en) * | 2022-06-06 | 2022-07-08 | 惠科股份有限公司 | Touch structure, OLED touch display panel and manufacturing method |
| CN114721553B (en) * | 2022-06-06 | 2022-12-13 | 惠科股份有限公司 | Touch structure, OLED touch display panel and manufacturing method |
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Effective date of registration: 20200827 Address after: No.7 Tianyou Road, Qixia District, Nanjing City, Jiangsu Province Applicant after: NANJING CEC PANDA LCD TECHNOLOGY Co.,Ltd. Address before: Nanjing Crystal Valley Road in Qixia District of Nanjing City Tianyou 210033 Jiangsu province No. 7 Applicant before: NANJING CEC PANDA LCD TECHNOLOGY Co.,Ltd. Applicant before: NANJING CEC PANDA FPD TECHNOLOGY Co.,Ltd. Applicant before: Nanjing East China Electronic Information Technology Co.,Ltd. |
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Application publication date: 20200103 |