CN110645851A - Wired frequency modulation communication method and circuit for electronic detonator initiator and electronic detonator - Google Patents
Wired frequency modulation communication method and circuit for electronic detonator initiator and electronic detonator Download PDFInfo
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- CN110645851A CN110645851A CN201910852841.8A CN201910852841A CN110645851A CN 110645851 A CN110645851 A CN 110645851A CN 201910852841 A CN201910852841 A CN 201910852841A CN 110645851 A CN110645851 A CN 110645851A
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- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F42—AMMUNITION; BLASTING
- F42C—AMMUNITION FUZES; ARMING OR SAFETY MEANS THEREFOR
- F42C19/00—Details of fuzes
- F42C19/08—Primers; Detonators
- F42C19/12—Primers; Detonators electric
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- F—MECHANICAL ENGINEERING; LIGHTING; HEATING; WEAPONS; BLASTING
- F42—AMMUNITION; BLASTING
- F42C—AMMUNITION FUZES; ARMING OR SAFETY MEANS THEREFOR
- F42C19/00—Details of fuzes
- F42C19/08—Primers; Detonators
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03C—MODULATION
- H03C7/00—Modulating electromagnetic waves
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Abstract
The invention belongs to the technical field of electronic detonators, and particularly relates to a wired frequency modulation communication method and circuit of an electronic detonator initiator and an electronic detonator, which comprises the steps of initializing a digital logic processing circuit in the electronic detonator initiator; the digital logic processing circuit modulates the signal; the digital logic circuit outputs a modulation signal to the driving circuit, and the driving circuit amplifies the modulation signal; the electronic detonator built-in chip demodulates the modulation signal, and designs a circuit according to the method, the digital logic processing circuit modulates the modulation signal to be transmitted to two carrier frequencies with higher frequencies of f0 and 2 xf 0, and the modulated signal is output through an I/O pin of the digital logic processing chip IC 1; the drive circuit amplifies the modulated signal output by the digital logic circuit to increase the transmission distance and the load capacity of the digital logic circuit. The electronic detonator demodulates the modulated signal through the built-in chip to realize the communication between the detonation controller and the electronic detonator.
Description
Technical Field
The invention belongs to the technical field of electronic detonators, and particularly relates to a wired frequency modulation communication method and circuit of an electronic detonator initiator and an electronic detonator.
Background
The continuous development and improvement of the electronic detonator technology, the technical superiority of the electronic detonator is more and more widely known in the global blasting world, particularly the production cost of the novel electronic detonator is continuously reduced, and the production application of the novel electronic detonator is expanded from the early rare and precious mineral exploitation field to the common mine and the quarry. The existing electronic detonator generally comprises a detonator tube plug, an electronic control module and a detonator tube shell, wherein a detonator leg wire penetrates through the detonator tube plug and is electrically connected with the electronic control module.
When the electronic detonators are used in a blasting field, the electronic detonators are firstly connected in parallel to form a network and then connected to the exploder, and the exploder communicates with the detonators of the network and sends blasting instructions. In the existing electronic detonator initiator, because the frequency of communication signals is low, the time consumption is long during blasting scanning of the electronic detonator, and the working efficiency is very easy to reduce. In addition, the existing electronic detonator initiator has low working voltage, complex topography and strong interference in a blasting field, a longer initiation bus is often needed, and the existing electronic detonator initiator cannot meet the field use requirements in transmission distance and anti-interference capability.
Disclosure of Invention
The purpose of the invention is: a wired frequency modulation communication method and circuit for an electronic detonator initiator and an electronic detonator can improve the communication efficiency of the electronic detonator initiator and the electronic detonator, and are strong in anti-jamming capability and long in transmission distance.
The method for wired frequency modulation communication between the electronic detonator initiator and the electronic detonator is realized by the following technical scheme, and comprises the following steps:
1) initializing a digital logic processing circuit in the electronic detonator initiator;
2) digital logic processing circuitry modulates signals representing commands or data;
3) the digital logic circuit outputs a modulation signal to the driving circuit, and the driving circuit amplifies the modulation signal; the digital logic circuit controls the drive circuit to work in a forward mode or a reverse mode, wherein the forward mode outputs a signal with positive polarity, and the reverse mode outputs a signal with negative polarity;
4) the electronic detonator built-in chip demodulates the modulation signal.
Further, the digital logic processing circuit described in step 2) modulates the signal onto two carrier pulses with frequency f1 and frequency f2, wherein a carrier pulse with three rising edges and frequency f1 represents a logic signal "0", and a carrier pulse with five rising edges and frequency f2 represents a logic signal "1"; wherein f 1-3 f 0; f2 is 5f0, f0 is 2000-3000 Hz.
Further, the digital logic processing chip outputs a low level, keeps the low level for a period of time t1, outputs a high level again, keeps the high level for a period of time t1, and circulates the steps for three times to represent that a modulation signal '0' is output; if the digital logic processing chip outputs a low level, the digital logic processing chip keeps outputting the low level for a period of time t2, and then outputs the high level, the digital logic processing chip delays outputting the high level for a period of time t2, and the cycle is repeated for five times, and the modulation signal "1" is output, wherein t1 is 3/5t 2; t1 is 1/f 1; t2 ═ 1/f 2.
In the invention, the high level of 2 times t0 is continuously output to represent the start bit signal, and the high level of 1.5 times t0 is continuously output to represent the end bit signal; wherein sequentially outputting 1 start bit signal, 8 permutation combination signals of logic signals "1" and "0" and 1 stop bit signal means outputting a complete data frame, the interval between data frames is 1-10mS, each frame data can be represented as command or data, and t0 is 1/f 0.
Further, the high level is 3.3-5V, and the low level is 0V.
Further, the specific scheme of the step 3) comprises the following steps: the digital logic processing chip of the digital logic circuit outputs a high level control signal and a low level control signal, and controls a driving chip in the driving circuit to work in a forward mode or a reverse mode; in all working modes, the driving chip is controlled by the digital logic processing chip, namely the digital logic processing chip outputs high level, the driving chip outputs high level, otherwise, the driving chip outputs low level, the signal amplitude is amplified to the driving power supply voltage, and the driving power supply voltage is 9-40V.
Further, the electronic detonator in the step 4) judges the bus through a built-in chip, and when the continuous high level which is 2 times t0 exists, the host starts to send an instruction; reading the rising edge times of the amplified modulation signal rectangular pulse output by the driving circuit, and when the rising edge times are three times in the time of 2 × t0, receiving a logic signal '0' by the electronic detonator; when the number of rising edges is five within the time of 2 × t0, the electronic detonator receives a logic signal "1", and when there is a continuous high level 1.5 times t0, the host stops sending the command, wherein t0 is 1/f 0.
Furthermore, the circuit for wired frequency modulation communication between the electronic detonator exploder and the electronic detonator comprises a digital logic processing circuit and a driving circuit, wherein the digital logic processing circuit is connected with the driving circuit and controls the driving circuit to work;
the digital logic processing circuit comprises a digital logic chip, the digital logic chip is respectively connected with a power supply and a grounding terminal of the digital logic processing circuit, and the digital logic processing circuit realizes frequency modulation and outputs a control signal of a driving circuit working mode;
drive circuit include a driver chip, drive circuit power, reset resistor, first protective resistor, second protective resistor, first current-limiting resistor, second current-limiting resistor, third current-limiting resistor, pull-up resistance, first protective resistor, second protective resistor, reset capacitor, charge pump output capacitance, charge pump switching capacitance, decoupling capacitance, first overvoltage protection tube, second overvoltage protection tube and third overvoltage protection tube, wherein:
the driving chip is connected to the digital logic processing chip and the grounding end through a first current limiting resistor, a second current limiting resistor and a third current limiting resistor, the driving chip is connected to the cathode of the first overvoltage protection tube through a first protection resistor, the driving chip is connected to the anode of the first overvoltage protection tube through a second protection resistor, and the cathode and the anode of the first overvoltage protection tube are respectively connected to two leg wires of the electronic detonator; the output capacitor of the charge pump is bridged between two pins of the driving chip; the charge pump switching capacitor is bridged with the driving chip; between the other two pins; after the first protection resistor and the second protection resistor are connected in parallel, one end of the first protection resistor and one end of the second protection resistor are connected to the driving chip, and the other end of the first protection resistor and the second protection resistor are connected to a driving circuit power supply; one end of the decoupling capacitor is connected to the driving chip, and the other end of the decoupling capacitor is connected to the grounding end; the cathode of the second overvoltage protection tube is connected to the anode of the first overvoltage protection tube, and the anode of the second overvoltage protection tube is connected to the ground terminal; the cathode of the third overvoltage protection tube is connected to the cathode of the first overvoltage protection tube, and the anode of the third overvoltage protection tube is connected to the ground terminal.
Furthermore, the invention also comprises a crystal oscillator circuit, wherein the crystal oscillator circuit comprises a crystal oscillator which is respectively connected with the grounding terminal and the clock input pin of the digital logic processing chip. The crystal oscillator circuit provides a clock source for the digital logic processing circuit.
Furthermore, the invention also comprises a power-on reset circuit, wherein the power-on reset circuit comprises a reset resistor and a reset capacitor, the reset resistor is connected with the reset capacitor in series, the other end of the reset resistor is connected to a power supply, the other end of the reset capacitor is connected to a grounding terminal, and a reset pin of the digital logic processing chip IC1 is connected between the reset resistor and the reset capacitor. The power-on reset circuit enables the digital logic processing circuit to keep a reset state for a period of time after being powered on, and prevents the digital logic processing circuit from sending out wrong instructions and executing wrong operations.
Has the advantages that: according to the invention, the existing electronic detonator exploder has low communication efficiency with the electronic detonator, poor anti-interference strength and short transmission distance, and can not meet the requirements of blasting sites. The method for communication between the electronic detonator initiator and the electronic detonator is obtained through research, and is simple and easy to operate. A circuit is designed according to the method, the circuit comprises a crystal oscillator circuit, a power-on reset circuit, a digital logic processing circuit and a driving circuit, the composition is simple, and a common driving chip is adopted, so that the cost of the detonator is reduced. The digital logic processing chip IC1 modulates the transmission signal, the frequency modulation signal is output to the drive circuit by the digital logic processing chip IC1, the drive circuit amplifies the frequency modulation signal, and the frequency modulation signal power is increased, so that the training efficiency of the detonator and the electronic detonator is improved, and the detonator can be scanned for 500 minutes only after being obtained through field blasting experiments. In addition, long-distance transmission is realized, and the anti-interference strength is improved.
Drawings
FIG. 1 is a schematic diagram of a wired frequency modulation communication circuit of an electronic detonator initiator and an electronic detonator;
FIG. 2 is a schematic diagram of signal modulation;
fig. 3 is a signal amplification schematic diagram.
Detailed Description
The technical solution of the present invention will be described in detail below with reference to the accompanying drawings in the embodiments of the present invention.
The wired frequency modulation communication method of the electronic detonator initiator and the electronic detonator comprises the following steps:
1) initializing a digital logic processing circuit in the electronic detonator initiator;
2) the digital logic processing circuit modulates the signal;
3) the digital logic circuit outputs a modulation signal to the driving circuit, and the driving circuit amplifies the modulation signal; the digital logic circuit controls the drive circuit to work in a forward mode or a reverse mode, wherein the forward mode outputs a signal with positive polarity, and the reverse mode outputs a signal with negative polarity;
4) the electronic detonator built-in chip demodulates a modulated signal representing a command or data.
The digital logic processing circuit in the step 2) modulates the signals onto two carrier pulses with the frequency f1 and the frequency f2, wherein the carrier pulse with three rising edges and the frequency f1 represents a logic signal "" 0 "" and the carrier pulse with five rising edges and the frequency f2 represents a logic signal "" 1 "; wherein f 1-3 f 0; f2 is 5f0, f0 is 2000-3000 Hz.
In the invention, the high level of 2 times t0 is continuously output to represent the start bit signal, and the high level of 1.5 times t0 is continuously output to represent the end bit signal; wherein sequentially outputting 1 start bit signal, 8 permutation combination signals of logic signals "1" and "0" and 1 stop bit signal means outputting a complete data frame, the interval between data frames is 1-10mS, each frame data can be represented as command or data, and t0 is 1/f 0.
The digital logic processing chip IC1 outputs low level, keeps for a period of time t1, outputs high level, keeps for a period of time t1, and circulates three times in this way to represent that a modulation signal '0' is output; if the digital logic processing chip IC1 outputs a low level, keeps the low level for a period of time t2, outputs a high level again, delays the high level for a period of time t2, and repeats the process five times, which indicates that a modulation signal "1" is output, where t1 is 3/5t 2; t1 is 1/f 1; t2 ═ 1/f 2.
It can be seen from the diagram that the output of the level belongs to the continuous output, and the high level and the low level have no definite boundary distinction, so that the high level and the low level are just clearly distinguished. The high level is 3.3-5V, and the low level is 0V.
In this embodiment, the 10-bit signal constitutes a byte, which includes a start bit, 8 data bits, and 1 stop bit. Wherein the start bit is 2 times high level of t0, and the stop bit is 1.5 times high level of t 0. The 8 data bits may be function codes or data. The interval between bytes is 1-10 mS.
The specific scheme of the step 3) comprises the following steps: the digital logic processing chip IC1 of the digital logic circuit outputs a high level control signal and a low level control signal, the driving chip IC2 in the control driving circuit works in a forward mode or a reverse mode, if the driving chip IC2 works in the forward mode, the output port of the driving chip IC2 outputs a positive frequency modulation carrier signal, and if the driving chip IC2 works in the reverse mode, the output port of the driving chip IC2 outputs a positive frequency modulation carrier signal; in all the working modes, the driver IC2 is controlled by the digital logic processing IC1, i.e., the digital logic processing IC1 outputs high level, the driver IC2 outputs high level, otherwise the driver IC2 outputs low level, and the signal amplitude is put to the power voltage, which is 9-40V.
The electronic detonator in the step 4) judges a bus through a built-in chip, and when a continuous high level 2 times t0 exists, the host starts to send an instruction; reading the rising edge times of the amplified modulation signal rectangular pulse output by the driving circuit, and when the rising edge times are three times in the time of 2 × t0, receiving a logic signal '0' by the electronic detonator; when the number of rising edges is five within the time of 2 × t0, the electronic detonator receives a logic signal "1", and when there is a continuous high level 1.5 times t0, the host stops sending the command, wherein t0 is 1/f 0.
In this embodiment, the high level of 2 times t0 is continuously received as the start bit signal, and the 8 data bit signals are continuously received until a high level of 1.5 times t0 is continuously received to indicate that one byte of data is received, and then the next byte of data is received with a delay of 1-10mS until no data is available.
The circuit for wired frequency modulation communication between the electronic detonator initiator and the electronic detonator comprises a digital logic processing circuit and a driving circuit, wherein the digital logic processing circuit is connected with the driving circuit and controls the driving circuit to work;
the digital logic processing circuit comprises a digital logic chip IC1, in this embodiment, pin 1, pin 5, and pin 17 of the digital logic chip IC1 are connected to a digital logic processing circuit power supply VCC, and pin 16, pin 32, and pin 31 of the digital logic chip IC1 are connected to a ground terminal GND.
The driving circuit comprises a driving chip IC2, a reset resistor R1, a first protection resistor R2, a second protection resistor R3, a first current limiting resistor R4, a second current limiting resistor R5, a third current limiting resistor R6, a pull-up resistor R7, a first protection resistor R8, a second protection resistor R9, a reset capacitor C1, a charge pump output capacitor C2, a charge pump switching capacitor C3, a decoupling capacitor C4, a first overvoltage protection tube Z1, a second overvoltage protection tube Z2 and a third overvoltage protection tube Z3, wherein:
in this embodiment, pin 1, pin 3, and pin 4 of the driver chip IC2 are connected to pin 29, pin 25, and pin 26 of the digital logic processing chip IC1 through resistors R4, R5, and R6, respectively, pin 5, pin 2, pin 12, and pin 7 of the driver chip IC2 are connected to the ground GND, pin 6 of the driver chip IC2 is connected to the cathode of the first overvoltage protection tube Z1 through a first protection resistor R8, and pin 9 of the driver chip IC2 is connected to the anode of the first overvoltage protection tube Z1 through a second protection resistor R9; the cathode and the anode of the first overvoltage protection tube Z1 are respectively connected to two leg wires of the electronic detonator; the charge pump output capacitor C2 is connected between the pin 8 and the pin 13 of the driving chip IC2 in a bridge mode; the charge pump switching capacitor C3 is connected across the pin 10 and the pin 11 of the driver IC 2; after being connected in parallel, the first protection resistor R2 and the second protection resistor R3 have one end connected to a pin 8 of the driving chip IC2 and the other end connected to a driving circuit power supply VDD; one end of the decoupling capacitor C4 is connected to pin 8 of the driver IC2, and the other end is connected to the ground GND; the cathode of the second overvoltage protection tube Z2 is connected to the anode of the first overvoltage protection tube Z1, and the anode of the second overvoltage protection tube Z2 is connected to the ground GND; the cathode of the third overvoltage protection tube Z3 is connected to the cathode of the first overvoltage protection tube Z1 and the anode of the third overvoltage protection tube Z3 is connected to ground GND.
The embodiment further includes a crystal oscillator circuit, the crystal oscillator circuit includes a crystal oscillator X1, the crystal oscillator X1 is respectively connected to the ground GND and the clock input pin 3 of the digital logic processing chip IC1, and the clock input pin 3 of the logic processing chip IC1 is connected to the clock input pin 2 of the logic processing chip IC 1. The crystal oscillator circuit provides a clock source for the digital logic processing circuit.
The embodiment further comprises a power-on reset circuit, wherein the power-on reset circuit comprises a reset resistor R1 and a reset capacitor C1, the reset resistor R1 is connected in series with the reset capacitor C1, the other end of the reset resistor R1 is connected to the power supply VCC, the other end of the reset capacitor C1 is connected to the ground GND, and the reset pin 4 of the digital logic processing chip IC1 is connected between the reset resistor R1 and the reset capacitor C1. The power-on reset circuit enables the digital logic processing circuit to keep a reset state for a period of time after being powered on, and prevents the digital logic processing circuit from sending out wrong instructions and executing wrong operations.
The circuit is used for communicating the electronic detonator exploder and the electronic detonator, and comprises the following steps:
the first step is as follows: the digital logic processing circuit 102 is powered on, and the reset circuit 101 enables the digital logic processing circuit to keep a reset state for a period of time, so that the digital logic processing circuit is prevented from sending an error instruction and executing error operation;
the second step is that: after the digital logic processing circuit 102 is normally reset, the digital logic processing circuit starts to initialize, and an output I/O port is set to be in a corresponding high-low state;
the third step: the digital logic processing chip IC1 modulates the modulation signal, and meanwhile, the pin 29 of the digital logic processing chip IC1 outputs the modulated signal;
the fourth step: the digital logic processing chip IC1 outputs a modulated signal to the driver circuit 103 and also outputs a driver circuit 103 operating mode control signal. The driving circuit amplifies 103 the modulated signal, and increases the power of the modulated signal, so that the modulated signal has longer transmission distance and larger load capacity;
the fifth step: the electronic detonator RLG demodulates the modulated signal through a built-in chip to realize wired frequency modulation communication between the initiator and the electronic detonator.
As shown in fig. 2, in the wired frequency modulation communication method for the electronic detonator initiator and the electronic detonator, the digital logic processing circuit modulates the signal in step 2), and the digital logic processing circuit modulates the modulated signal to two carrier frequencies with frequency f0 and frequency 2 xf 0, wherein a rectangular pulse with three rising edges and frequency f0 represents a logic signal "0", and a rectangular pulse with five rising edges and frequency 2 xf 0 represents a logic signal "1".
Further, in the wired frequency modulation communication method of the electronic detonator initiator and the electronic detonator, a pin 29 of a digital logic processing chip IC1 in a digital logic processing circuit outputs a low level, delays for a period of time t1, then outputs a high level, delays for a period of time t1, and the process is circulated for three times to represent that a logic signal '0' is output; then, pin 29 of the digital logic processing chip IC1 outputs a low level, delays for a period of time t0/2, outputs a high level again, delays for a period of time t0/2, and repeats five times to represent that a logic signal "1" is output, where t1 is 3/5t 2; t1 is 1/f 1; t2 ═ 1/f 2; wherein, the high level of 2 times t0 is continuously output to represent the start bit signal, and the high level of 1.5 times t0 is continuously output to represent the end bit signal; wherein sequentially outputting 1 start bit signal, 8 permutation combination signals of logic signals '1' and '0' and 1 stop bit signal means outputting one complete data frame, the interval between data frames is 1-10mS, and each frame data can be represented as command or data.
As shown in fig. 3, in the wired frequency modulation communication method of the electronic detonator initiator and the electronic detonator, the driving circuit in step 3) amplifies the modulation signal, and the method comprises the following steps: pin 26 and pin 25 of digital logic processing chip IC1 of the digital logic circuit output a high level control signal and a low level control signal respectively, and control driving chip IC2 in the driving circuit to work in a forward and reverse output state, in this working mode, the output of driving chip IC2 changes with the output of pin 29 of digital logic processing chip IC1, that is, when pin 29 outputs a low level, OUTA of driving chip IC2 outputs a low level, OUTB outputs a high level VDD, and at this time, driving chip IC2 outputs OUTA-OUTB, that is, -VDD; when pin 29 of digital logic processing chip IC1 outputs high VCC, OUTA of driver chip IC2 outputs high VDD, OUTB outputs low VDD, and at this time, the output voltage of driver chip IC2 is OUTA-OUTB, i.e., VDD, so the output voltage waveform of driver chip IC2 matches the modulated signal output waveform of digital logic processing chip IC1, and the amplitude of the modulated signal is amplified to VDD.
Further, the wired frequency modulation communication method of the electronic detonator initiator and the electronic detonator, in the step 4), the electronic detonator built-in chip demodulates the modulation signal, and comprises the following steps: the electronic detonator judges the bus through a chip arranged in the electronic detonator, and when a continuous high level 2 times t0 exists, the host starts to send an instruction; reading the rising edge times of the amplified modulation signal rectangular pulse output by the driving circuit, and when the rising edge times are three times in the time of 2 × t0, receiving a logic signal '0' by the electronic detonator; when the number of rising edges is five times in the time of 2 × t0, the electronic detonator receives a logic signal "1", and when there is a continuous high level 1.5 times t0, the host stops sending commands.
The invention is not limited to the embodiments described in the specific embodiments, and those skilled in the art can derive other embodiments according to the technical solutions of the invention, and the embodiments also belong to the technical innovation scope of the invention. It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (9)
1. A wired frequency modulation communication method for an electronic detonator initiator and an electronic detonator is characterized by comprising the following steps:
1) initializing a digital logic processing circuit in the electronic detonator initiator;
2) digital logic processing circuitry modulates signals representing commands or data;
3) the digital logic circuit outputs a modulation signal to the driving circuit, and the driving circuit amplifies the modulation signal; the digital logic circuit controls the drive circuit to work in a forward mode or a reverse mode, wherein the forward mode outputs a signal with positive polarity, and the reverse mode outputs a signal with negative polarity;
4) the electronic detonator built-in chip demodulates the modulation signal.
2. The wired frequency modulation communication method for the electronic detonator initiator and the electronic detonator according to claim 1, wherein the digital logic processing circuit of step 2) modulates the signal onto two carrier pulses with frequency f1 and frequency f2, wherein the carrier pulse with three rising edges and frequency f1 represents the logic signal "0", and the carrier pulse with five rising edges and frequency f2 represents the logic signal "1"; wherein f 1-3 f 0; f2 is 5f0, f0 is 2000-3000 Hz.
3. The electronic detonator initiator and electronic detonator wired frequency modulation communication method according to claim 2, wherein the digital logic processing chip (IC1) outputs a low level, keeps the low level for a period of time t1, outputs a high level again, keeps the high level for a period of time t1, and circulates the steps three times to represent that a modulation signal "0" is output; if the digital logic processing chip (IC1) outputs a low level, keeps the low level for a period of time t2, outputs a high level again, delays the high level for a period of time t2, and circulates five times to represent that a modulation signal '1' is output, wherein t1 is 3/5t 2; t1 is 1/f 1; t2 ═ 1/f 2.
4. The electronic detonator initiator and electronic detonator wired frequency modulation communication method according to claim 3, wherein: the high level is 3.3-5V, and the low level is 0V.
5. The electronic detonator initiator and electronic detonator wired frequency modulation communication method according to claim 1, wherein the specific scheme of the step 3) comprises the following steps: a digital logic processing chip (IC1) of the digital logic circuit outputs a high-level control signal and a low-level control signal, a driving chip (IC2) in the driving circuit is controlled to work in a forward mode or a reverse mode, if the driving chip works in the forward mode, an output port of the driving chip (IC2) outputs a positive-polarity frequency modulation carrier signal, and if the driving chip works in the reverse mode, an output port of the driving chip (IC2) outputs a positive-polarity frequency modulation carrier signal; in all the working modes, the driving chip (IC2) is controlled by the digital logic processing chip (IC1), namely the digital logic processing chip (IC1) outputs high level, the driving chip (IC2) outputs high level, otherwise, the driving chip (IC2) outputs low level, and the signal amplitude is released to the driving power supply voltage, and the driving power supply voltage is 9-40V.
6. The wired frequency modulation communication method of the electronic detonator initiator and the electronic detonator according to claim 2, 3 or 4, wherein the electronic detonator built-in chip of step 4) demodulates the modulation signal, comprising the steps of: the electronic detonator judges the bus through a chip arranged in the electronic detonator, and when a continuous high level 2 times t0 exists, the host starts to send an instruction; reading the rising edge times of the amplified modulation signal rectangular pulse output by the driving circuit, and when the rising edge times are three times in the time of 2 × t0, receiving a logic signal '0' by the electronic detonator; when the number of rising edges is five within the time of 2 × t0, the electronic detonator receives a logic signal "1", and when there is a continuous high level 1.5 times t0, the host stops sending the command, wherein t0 is 1/f 0.
7. A circuit for realizing wired frequency modulation communication between the electronic detonator initiator and the electronic detonator according to claim 1, which comprises a digital logic processing circuit and a driving circuit, wherein the digital logic processing circuit is connected with the driving circuit and controls the driving circuit to work;
the digital logic processing circuit comprises a digital logic chip (IC1), a digital logic processing circuit power supply (VCC) and a grounding terminal (GND) which are respectively connected with the digital logic chip (IC1), and the digital logic processing circuit realizes frequency modulation and outputs a driving circuit working mode control signal;
the driving circuit comprises a driving chip (IC2), a driving circuit power supply (VDD), a reset resistor (R1), a first protection resistor (R2), a second protection resistor (R3), a first current-limiting resistor (R4), a second current-limiting resistor (R5), a third current-limiting resistor (R6), a pull-up resistor (R7), a first protection resistor (R8), a second protection resistor (R9), a reset capacitor (C1), a charge pump output capacitor (C2), a charge pump switching capacitor (C3), a decoupling capacitor (C4), a first overvoltage protection tube (Z1), a second overvoltage protection tube (Z2) and a third overvoltage protection tube (Z3), wherein:
the driving chip (IC2) is connected to the digital logic processing chip (IC1) and a ground terminal (GND) through a first current-limiting resistor (R4), a second current-limiting resistor (R5) and a third current-limiting resistor (R6), the driving chip (IC2) is connected to the cathode of a first overvoltage protection tube (Z1) through a first protection resistor (R8), the driving chip (IC2) is connected to the anode of the first overvoltage protection tube (Z1) through a second protection resistor (R9), and the cathode and the anode of the first overvoltage protection tube (Z1) are respectively connected to two pin wires of the electronic detonator; the output capacitor (C2) of the charge pump is connected between two pins of the driving chip (IC2) in a bridging way; the charge pump switching capacitor (C3) is connected across the driving chip (IC 2); between the other two pins; after being connected in parallel, the first protection resistor (R2) and the second protection resistor (R3) are connected with each other, one end of the first protection resistor is connected to the driving chip (IC2), and the other end of the first protection resistor is connected to the driving circuit power supply (VDD); one end of the decoupling capacitor (C4) is connected to the driving chip (IC2), and the other end is connected to the Ground (GND); the cathode of the second overvoltage protection tube (Z2) is connected to the anode of the first overvoltage protection tube (Z1), and the anode of the second overvoltage protection tube (Z2) is connected to the Ground (GND); the cathode of the third overvoltage protection tube (Z3) is connected to the cathode of the first overvoltage protection tube (Z1), and the anode of the third overvoltage protection tube (Z3) is connected to Ground (GND).
8. The circuit for wired frequency modulation communication of the electronic detonator initiator and the electronic detonator according to claim 7, further comprising a crystal oscillator circuit, wherein the crystal oscillator circuit comprises a crystal oscillator (X1), and the crystal oscillator (X1) is respectively connected with a ground terminal (GND) and a clock input pin of the digital logic processing chip (IC 1).
9. The circuit for wired frequency modulation communication of the electronic detonator initiator and the electronic detonator according to claim 7, further comprising a power-on reset circuit, wherein the power-on reset circuit comprises a reset resistor (R1) and a reset capacitor (C1), the reset resistor (R1) and the reset capacitor (C1) are connected in series, the other end of the reset resistor (R1) is connected to the power supply (VCC), the other end of the reset capacitor (C1) is connected to the ground terminal (GND), and the reset pin of the digital logic processing chip IC1 is connected between the reset resistor (R1) and the reset capacitor (C1).
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