CN110634940A - 使用横向外延过生长制造肖特基势垒二极管 - Google Patents

使用横向外延过生长制造肖特基势垒二极管 Download PDF

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CN110634940A
CN110634940A CN201910428595.3A CN201910428595A CN110634940A CN 110634940 A CN110634940 A CN 110634940A CN 201910428595 A CN201910428595 A CN 201910428595A CN 110634940 A CN110634940 A CN 110634940A
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hard mask
substrate
diode
schottky
layer
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S·达斯古普塔
M·拉多萨夫列维奇
H·W·田
P·菲舍尔
W·哈菲兹
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Intel Corp
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Abstract

本文公开了一种二极管。所述二极管包括半导体衬底、形成在衬底上方的硬掩模、与硬掩模的侧面相邻的第一材料的垂直取向的部件、以及在硬掩模的顶部上的第一材料的横向取向的部件。所述横向取向的部件被定向在第一方向和第二方向上。二极管还包括在第一材料顶部的第二材料。第二材料形成肖特基势垒。

Description

使用横向外延过生长制造肖特基势垒二极管
技术领域
本公开的实施例涉及制造肖特基二极管，并且具体而言，涉及使用横向外延过生长来制造肖特基二极管。
背景技术
一些常规射频(RF)系统使用片上静电放电(ESD)保护电路来为系统电路提供ESD保护。用于这种系统的ESD保护电路的设计可能具有挑战性。ESD保护电路需要具有电流密度和泄漏电流特性，使得ESD保护电路能够提供有效的保护。具体而言，ESD保护电路需要具有响应于ESD事件而处理大量电流的能力并且在正常操作期间表现出低反向泄漏电流。
GaN晶体管是用于诸如5G产品的未来RF产品中的有希望的候选。为了使得完全集成的GaN RF前端能够用于这种产品，需要使用高性能肖特基二极管的ESD保护电路。然而，肖特基二极管可以表现出比一些其它类型的二极管更高的泄漏电流。用于ESD保护电路设计的常规方法不能充分解决电流密度和反向泄漏电流的挑战。
附图说明
图1是根据实施例的集成金属氧化物半导体高电子迁移率晶体管(MOSHEMT)和GaN肖特基二极管结构的图示。
图2A-2F是根据实施例的在制造期间的集成MOSHEMT和肖特基势垒二极管结构的截面图的图示。
图3示出了根据实施例的计算装置。
图4示出了包括一个或多个实施例的内插器。
具体实施方式
描述了用于使用横向外延过生长来制造肖特基二极管的方法。在下面的描述中，示出了许多具体细节，例如具体集成及材料体系，以提供对本公开的实施例的深入了解。对本领域的技术人员将显而易见的是，可以在没有这些具体细节的情况下实践本公开的实施例。在其它实例中，没有详细地描述诸如集成电路设计布局的公知特征，以避免不必要地使本公开的实施例难以理解。此外，应当认识到，在图中示出的各种实施例是例示性的表示并且未必是按比例绘制的。
以下描述中还仅为了参考的目的使用了某些术语，因此这些术语并非旨在进行限制。例如，诸如“上部”、“下部”、“上方”和“下方”等术语是指附图中提供参考的方向。诸如“正面”、“背面”、“后面”和“侧面”等术语描述在一致但任意的参照系内部件的某些部分的取向和/或位置，通过参考描述所讨论部件的文字和相关联的附图可以清楚地了解这些取向和/或位置。这种术语可以包括上面具体提及的词语、它们的衍生词语以及类似意义的词语。
在实施例中，使用外延材料的单次操作再生长来完成GaN晶体管和肖特基二极管在同一管芯中的共同集成，以形成共同集成的半导体结构的肖特基二极管部件以及晶体管源极和漏极部件。作为肖特基二极管的制造的部分，实施例利用高掺杂材料的再生长来形成材料层，在该材料层之上形成肖特基势垒。在用于共同集成的晶体管的源极-漏极外延再生长操作期间形成高掺杂材料层。实施例利用高掺杂材料的横向过生长来形成在肖特基势垒下面具有低缺陷密度的高掺杂材料层。这些材料特性用于制造可以输送高电流密度的肖特基二极管。此外，低缺陷密度降低了反向偏置垂直泄漏电流。在实施例中，在单次操作中形成高掺杂材料而没有额外的再生长。
图1是根据实施例的集成MOSHEMT和GaN肖特基二极管半导体结构的图示。在实施例中，单次操作外延再生长用于形成薄膜，作为共同集成的半导体结构的晶体管源极和漏极区以及肖特基二极管阴极部件的结构化的部分。该工艺产生了输送高电流密度并表现出低反向偏置泄漏电流的肖特基二极管。
图1示出了肖特基二极管100A，其包括衬底101、外延层103、第一阴极区105、第二阴极区107、半导体109、极化层111、绝缘体层113、高掺杂和低缺陷密度半导体材料115、非人为掺杂层117、肖特基势垒层119、绝缘体121、第一阴极区接触部123、第二阴极区接触部125、肖特基金属127和绝缘体129。此外，图1示出了晶体管100B，其除了包括与集成肖特基二极管100A共享的结构之外，还包括源极接触部131、源极133、高k材料135、栅极接触部137、栅极139、绝缘体141(硬掩模)、漏极接触部143和漏极145。
参考图1，肖特基二极管100A包括高掺杂且具有低缺陷密度的半导体材料115。半导体材料115的低缺陷密度使得肖特基二极管100A能够输送的电流的密度比使用具有较高缺陷密度的材料可以输送的电流密度更高。在实施例中，半导体材料115由高掺杂的GaN形成。在实施例中，在形成源极133、漏极145、第一阴极区105和第二阴极区107期间形成半导体材料115。在半导体结构100的第一阴极区105和第二阴极区107中生长的材料积聚在那些区域中并沿着包括半导体层109、极化层111、硬掩模层113和外延层103的部分的半导体结构100的材料堆叠体的侧壁垂直上升。在实施例中，半导体材料115最终在硬掩模113上方延伸。之后，在实施例中，工艺条件被调整为促进半导体材料的横向生长。然后，积聚材料从硬掩模113的侧面横向移动，直到覆盖硬掩模113的顶表面。本文参考图2A-2E讨论了外延材料的横向再生长用于形成高掺杂且低缺陷密度的半导体材料115的方式。
硬掩模层113将位于硬掩模层113上方的材料层与位于硬掩模层113下方的衬底101的缺陷隔离。例如，衬底101的缺陷从衬底101向上突出穿过GaN外延层103、半导体层109和极化层111。然而，硬掩模层113具有不能被缺陷穿透的物理结构。于是，通过硬掩模层113阻止缺陷的向上突出。应当认识到，在实施例中，位于硬掩模层113上方的诸如低缺陷密度且高掺杂的半导体115、非人为掺杂层117和肖特基势垒层119的材料受到硬掩模层113的缺陷阻挡效用的保护。
在操作中，在发生ESD事件时，肖特基二极管100A变为正向偏置并将ESD电流路由到地。通过这种方式，防止了电流损坏电路，例如RF器件前端电路，其可以包括诸如晶体管100B的晶体管(其可以位于相关联的RF器件的前端)。在实施例中，因为在肖特基势垒下面形成的材料是高掺杂的，所以在肖特基二极管100A中流动的电流的电流密度高，这为肖特基二极管100A提供了鲁棒的电流处理能力。此外，当肖特基二极管100A被反向偏置时，因为在肖特基势垒下面形成的材料的缺陷少，所以反向电流泄漏低，并且反向电压保护最大。
在实施例中，衬底101可以由硅形成。在其它实施例中，衬底101可以由其它材料形成。在实施例中，外延层103可以由GaN形成。在其它实施例中，外延层103可以由其它材料形成。在实施例中，第一阴极105和第二阴极107可以由InGaN形成。在其它实施例中，第一阴极105和第二阴极107可以由其它材料形成。在实施例中，可以由AlN形成半导体109。在其它实施例中，半导体109可以由其它材料形成。在实施例中，极化层111可以由AlInN形成。在其它实施例中，极化层111可以由其它材料形成。在实施例中，硬掩模层113可以由氮化物形成。在其它实施例中，硬掩模层113可以由其它材料形成。在实施例中，高掺杂且低缺陷密度的半导体层115可以由InGaN形成。在其它实施例中，高掺杂且低缺陷密度的半导体层115可以由其它材料形成。在实施例中，非人为掺杂半导体117可以由GaN形成。在其它实施例中，非人为掺杂半导体117可以由其它材料形成。在实施例中，肖特基势垒层119可以由AlGaN或AlInN形成。在其它实施例中，肖特基势垒层119可以由其它材料形成。在实施例中，绝缘体121可以由氧化物形成。在其它实施例中，绝缘体121可以由其它材料形成。在实施例中，第一阴极接触部123可以由Ti、Al或W形成。在其它实施例中，第一阴极接触部123可以由其它材料形成。在实施例中，第二阴极接触部125可以由Ti、Al或W形成。在其它实施例中，第二阴极接触部125可以由其它材料形成。在实施例中，肖特基金属127可以由镍、铂或氮化钛形成。在其它实施例中，肖特基金属127可以由其它材料形成。在实施例中，绝缘体129可以由氧化物形成。在其它实施例中，绝缘体129可以由其它材料形成。在实施例中，源极133可以由InGaN形成。在其它实施例中，源极133可以由其它材料形成。在实施例中，源极接触部131可以由Ti、Al或W形成。在其它实施例中，源极接触部131可以由其它材料形成。在实施例中，漏极145可以由InGaN形成。在其它实施例中，漏极145可以由其它材料形成。在实施例中，漏极接触部143可以由Ti、Al或W形成。在其它实施例中，漏极接触部143可以由其它材料形成。在一个实施例中，栅极139可以由镍、铂或氮化钛形成。在其它实施例中，栅极139可以由其它材料形成。在实施例中，栅极接触部137可以由Ti、Al或W形成。在其它实施例中，栅极接触部137可以由其它材料形成。在实施例中，高k材料135可以包括但不限于氧化铪。在其它实施例中，高k材料可以包括其它材料。在实施例中，可以由多晶硅或二氧化硅形成高硬掩模141。在其它实施例中，高硬掩模141可以由其它材料形成。
实施例的优点包括在用于形成共同集成的晶体管100B的源极和漏极的操作期间在肖特基势垒层119下方形成高掺杂且低缺陷密度的半导体层115并且形成肖特基势垒层119本身。于是，避免了用于形成这些结构的多次操作。如上所述，在实施例中，可以使用横向过生长技术来实现高掺杂且低缺陷密度的半导体层115的形成。在实施例中，由具有低缺陷密度的高质量材料形成高掺杂且低缺陷密度的半导体层115。此外，在实施例中，横向过生长的取向对高掺杂且低缺陷密度的半导体层115的低缺陷密度有贡献。此外，如上所述，硬掩模113保护高掺杂且低缺陷密度的半导体层115免受从衬底103突出的缺陷的影响。具有低缺陷密度的高掺杂且低缺陷密度的半导体层115产生了输送高电流密度并表现出低反向偏置泄漏电流的肖特基二极管。
图2A-2F是在使用横向过生长的肖特基势垒二极管的制造工艺期间的半导体结构200的截面图的图示。参考图2A，在多次操作之后，形成半导体结构200的横截面，其包括衬底201、外延层203、半导体层205、极化层207、短硬掩模209、高硬掩模211、氧化物213、半导体215、极化层217和短硬掩模219。在实施例中，图2A的横截面是在源极/漏极外延再生长操作之前的半导体结构200的外观的图示。在实施例中，与使用基于外延区蚀刻和底切的源极/漏极外延再生长工艺的常规掩模方法不同，高硬掩模211用于外延再生长。在实施例中，形成高(例如，大于150nm)硬掩模211以用于晶体管区中的源极-漏极外延再生长。此外，形成短(例如，约20-30nm)硬掩模209以用于肖特基二极管区中的外延再生长。在其它实施例中，可以使用其它高度的硬掩模。在实施例中，外延底切(EUC)的深度在晶体管和肖特基二极管区中可以是相同的。
参考图2B，在产生图2A中所示的半导体结构200的横截面的一次或多次操作之后，执行源极-漏极外延生长操作。在实施例中，通过将晶片装载到用于源极-漏极外延生长操作的外延反应器中，可以执行源极-漏极外延生长操作。在其它实施例中，可以采用执行外延生长操作的任何其它适合的方式来执行外延生长操作。在实施例中，生长的第一薄膜是高掺杂的n+InGaN膜221。在实施例中，高掺杂的n+InGaN膜221掺杂有Si。在其它实施例中，n+InGaN膜221可以掺杂有其它材料。因为用于肖特基区的硬掩模209是浅的，所以最初，n+InGaN膜221沿着硬掩模209的侧壁垂直生长，并且最终在硬掩模209的顶部上方垂直延伸。然后，n+InGaN膜221从两侧沿着硬掩模209的顶表面横向生长223，并最终完全覆盖硬掩模209的顶表面。沿着硬掩模209的侧壁生长的InGaN晶体是具有低缺陷密度的高质量InGaN晶体。这种具有低缺陷密度的相同的高质量InGaN晶体使浅硬掩模区209横向过生长。外延生长操作有助于将衬底的缺陷与肖特基二极管200A的关键区域分离，因为浅硬掩模209上方的过生长受到浅硬掩模209的保护以免受从衬底201突出的缺陷的影响。因此，在实施例中，因为肖特基二极管反向泄漏电流与缺陷密度成正比，所以肖特基二极管200A能够提供低反向泄漏电流。以这此方式，解决了本文描述的实现低缺陷密度的挑战。
参考图2C，在产生如图2B中所示的横截面的一次或多次操作之后，通过配置工艺条件以促进硬掩模209的顶表面的横向过生长而不是垂直生长，使沿着硬掩模209的顶表面横向生长的n+InGaN膜223生长得更长。在实施例中，该工艺引起了n+InGaN膜223在硬掩模209的顶表面上的过生长被合并到肖特基二极管区200A中。
参考图2D，在产生如图2C中所示的半导体结构200的横截面的一次或多次操作之后，生长未掺杂的GaN 225的薄层。在实施例中，未掺杂的GaN 225的薄层可以具有大约20-30nm的厚度。在其它实施例中，未掺杂的GaN 225的薄层可以具有其它厚度。参考图2E，在产生如图2D中所示的半导体结构200的横截面的一次或多次操作之后，被选择用于设置用于肖特基二极管的肖特基势垒的材料227被生长在未掺杂的GaN 225的薄层上方。在实施例中，被选择用于设置肖特基势垒的材料227可以包括具有10nm厚度的AlGaN(30％)～1eV势垒的薄层。在其它实施例中，具有其它厚度的其它材料可以用于设置肖特基势垒的材料。
参考图2F，在产生诸如图2E中所示的半导体结构200的横截面的一次或多次操作之后(在已经完成外延生长之后)，半导体结构200的不同高度区域被平坦化。之后，形成MOSHEMT器件229的栅极、二极管的肖特基接触部231、以及MOS HEMT器件200B的源极区235和漏极区237的欧姆金属接触部233和236。在实施例中，使用干法蚀刻来蚀刻掉未掺杂的GaN的225和AlGaN 227层，以在沉积欧姆金属之前在肖特基二极管区中形成用于欧姆金属接触部的空间。
可以在诸如半导体衬底的衬底上形成或执行本发明的实施例的实施方式。在一种实施方式中，半导体衬底可以是使用体硅或绝缘体上硅子结构形成的晶体衬底。在其它实施方式中，半导体衬底可以使用替代材料形成，替代材料可以或可以不与硅组合，包括但不限于锗、锑化铟、碲化铅、砷化铟、磷化铟、砷化镓、砷化铟镓、锑化镓、或III-V族或IV族材料的其它组合。尽管这里描述了可以形成衬底的材料的几个示例，但可以充当可以构建半导体器件的基础的任何材料都落在本发明的精神和范围内。
可以在衬底上制造多个晶体管，例如金属氧化物半导体场效应晶体管(MOSFET或简称MOS晶体管)。在本发明的各种实施方式中，MOS晶体管可以是平面晶体管、非平面晶体管或两者的组合。非平面晶体管包括诸如双栅极晶体管和三栅极晶体管的FinFET晶体管、以及诸如纳米带和纳米线晶体管的环绕式或全包围栅极晶体管。尽管本文描述的实施方式可以仅示出平面晶体管，但是应当指出，本发明也可以使用非平面晶体管来实行。
每个MOS晶体管包括由至少两个层(栅极电介质层和栅极电极层)形成的栅极堆叠体。栅极电介质层可以包括一个层或层的堆叠体。一个或多个层可以包括氧化硅、二氧化硅(SiO2)和/或高k电介质材料。高k电介质材料可以包括诸如铪、硅、氧、钛、钽、镧、铝、锆、钡、锶、钇、铅、钪、铌和锌的元素。可以用于栅极电介质层中的高k材料的示例包括但不限于氧化铪、硅氧化铪、氧化镧、氧化镧铝、氧化锆、硅氧化锆、氧化钽、氧化钛、氧化钡锶钛、氧化钡钛、氧化锶钛、氧化钇、氧化铝、氧化铅钪钽和铌酸铅锌。在一些实施例中，可以对栅极电介质层执行退火工艺，以在使用高k材料时改善其质量。
栅极电极层形成在栅极电介质层上，并且根据晶体管是PMOS还是NMOS晶体管，栅极电极层可以由至少一种P型功函数金属或N型功函数金属构成。在一些实施方式中，栅极电极层可以由两个或更多金属层的堆叠体构成，其中一个或多个金属层是功函数金属层，并且至少一个金属层是填充金属层。
对于PMOS晶体管，可以用于栅极电极的金属包括但不限于钌、钯、铂、钴、镍和导电金属氧化物，例如氧化钌。P型金属层将使得能够形成具有介于大约4.9eV和大约5.2eV之间的功函数的PMOS栅极电极。对于NMOS晶体管，可以用于栅极电极的金属包括但不限于铪、锆、钛、钽、铝、这些金属的合金、以及这些金属的碳化物，例如碳化铪、碳化锆、碳化钛、碳化钽和碳化铝。N型金属层将使得能够形成具有介于大约3.9eV和大约4.2eV之间的功函数的NMOS栅极电极。
在一些实施方式中，栅极电极可以由“U”形结构构成，该U形结构包括基本平行于衬底表面的底部部分以及基本垂直于衬底顶表面的两个侧壁部分。在另一实施方式中，形成栅极电极的金属层中的至少一个可以简单地是基本平行于衬底顶表面的平面层，并且不包括基本垂直于衬底顶表面的侧壁部分。在本发明的其它实施方式中，栅极电极可以由U形结构和平面非U形结构的组合构成。例如，栅极电极可以由在一个或多个平面非U形层顶部形成的一个或多个U形金属层构成。
在本发明的一些实施方式中，可以在栅极堆叠体的相对侧上形成一对侧壁间隔体，其夹住栅极堆叠体。侧壁间隔体可以由诸如氮化硅、氧化硅、碳化硅、掺有碳的氮化硅和氮氧化硅的材料形成。用于形成侧壁间隔体的工艺是现有技术公知的，并且一般包括沉积和蚀刻工艺步骤。在替代的实施方式中，可以使用多个间隔体对，例如，可以在栅极堆叠体的相对侧上形成两对、三对或四对侧壁间隔体。
如本领域所熟知的，在衬底内的与每个MOS晶体管的栅极堆叠体相邻处形成源极区和漏极区。通常可以使用注入/扩散工艺或蚀刻/沉积工艺形成源极区和漏极区。在前一工艺中，可以向衬底中离子注入掺杂剂，例如硼、铝、锑、磷或砷，以形成源极区或漏极区。在离子注入工艺之后，典型地接着进行退火工艺，该退火工艺激活掺杂剂并使它们向衬底中扩散更远。在后一工艺中，衬底可以首先被蚀刻以在源极区和漏极区的位置处形成凹陷。然后可以执行外延沉积工艺以利用用于制造源极区和漏极区的材料填充凹陷。在一些实施方式中，可以使用诸如硅锗或碳化硅的硅合金来制造源极区和漏极区。在一些实施方式中，可以利用诸如硼、砷或磷的掺杂剂对外延沉积的硅合金进行原位掺杂。在另一实施例中，可以使用诸如锗或III-V族材料或合金的一种或多种替代半导体材料来形成源极区或漏极区。并且在其它实施例中，可以使用金属和/或金属合金的一层或多层来形成源极区和漏极区。
在MOS晶体管之上沉积一个或多个层间电介质(ILD)。可以使用已知适用于集成电路结构中的诸如低k电介质材料的电介质材料来形成ILD层。可以使用的电介质材料的示例包括但不限于二氧化硅(SiO2)、碳掺杂氧化物(CDO)、氮化硅、有机聚合物(例如全氟环丁烷或聚四氟乙烯)、氟硅酸盐玻璃(FSG)、和有机硅酸盐(例如倍半硅氧烷、硅氧烷)或有机硅酸盐玻璃。ILD层可以包括孔隙或气隙以进一步降低其介电常数。
图3示出了根据本发明的一种实施方式的计算装置300。计算装置300容纳板302。板302可以包括若干部件，包括但不限于处理器304和至少一个通信芯片306。处理器304物理和电耦合到板302。在一些实施方式中，至少一个通信芯片306还物理和电耦合到板302。在其它实施方式中，通信芯片306是处理器304的部分。
取决于其应用，计算装置300可以包括可以或可以不物理和电耦合到板302的其它部件。这些其它部件包括但不限于易失性存储器(例如，DRAM)、非易失性存储器(例如，ROM)、闪速存储器、图形处理器、数字信号处理器、密码处理器、芯片组、天线、显示器、触摸屏显示器、触摸屏控制器、电池、音频编解码器、视频编解码器、功率放大器、全球定位系统(GPS)装置、罗盘、加速度计、陀螺仪、扬声器、相机和大容量存储装置(例如，硬盘驱动器)、压缩磁盘(CD)、数字多用盘(DVD)等。
通信芯片306能够实现用于向和从计算装置300传输数据的无线通信。术语“无线”及其派生词可以用于描述可以通过非固体介质通过使用经调制的电磁辐射来传送数据的电路、装置、系统、方法、技术、通信信道等。该术语不暗示相关联的装置不包含任何线路，尽管在一些实施例中它们可能不包含。通信芯片306可以实施若干无线标准或协议中的任何标准或协议，包括但不限于Wi-Fi(IEEE802.11系列)、WiMAX(IEEE802.16系列)、IEEE802.20、长期演进(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、蓝牙、其衍生物、以及被指定为3G、4G、5G和更高版本的任何其它无线协议。计算装置300可以包括多个通信芯片306。例如，第一通信芯片306可以专用于诸如Wi-Fi和蓝牙的较短距离无线通信，并且第二通信芯片306可以专用于诸如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO或其它的较长距离无线通信。
计算装置300的处理器304包括封装于处理器304内的集成电路管芯。在本发明的一些实施方式中，处理器的集成电路管芯包括一个或多个器件，例如，根据本发明实施方式构造的MOS-FET晶体管。术语“处理器”可以指处理来自寄存器和/或存储器的电子数据以将该电子数据变换成可以存储于寄存器和/或存储器中的其它电子数据的任何装置或装置的部分。
通信芯片306还包括封装于半导体芯片306内的集成电路管芯。在本发明的另一实施方式中，通信芯片的集成电路管芯包括一个或多个器件，例如，根据本发明的实施方式构造的MOS-FET晶体管。
在其它实施方式中，计算装置300内容纳的另一个部件可以包含集成电路管芯，该集成电路管芯包括一个或多个器件，例如根据本发明的实施方式构造的MOS-FET晶体管。
在各种实施方式中，计算装置300可以是膝上型计算机、上网本、笔记本、超级本、智能电话、平板计算机、个人数字助理(PDA)、超级移动PC、移动电话、台式计算机、服务器、打印机、扫描仪、监视器、机顶盒、娱乐控制单元、数字相机、便携式音乐播放器或数字视频录像机。在其它实施方式中，计算装置300可以是处理数据的任何其它电子装置。
图4示出了包括本发明的一个或多个实施例的内插器400。内插器400是用于将第一衬底402桥接到第二衬底404的居间衬底。第一衬底402可以是例如集成电路管芯。第二衬底404例如可以是存储器模块、计算机母板或另一集成电路管芯。通常，内插器400的目的是将连接扩展到更宽的间距或将连接重新布线到不同的连接。例如，内插器400可以将集成电路管芯耦合到球栅阵列(BGA)406，球栅阵列406接着可以耦合到第二衬底404。在一些实施例中，第一和第二衬底402/404附接到内插器400的相对侧。在其它实施例中，第一和第二衬底402/404附接到内插器400的相同侧。并且在其它实施例中，利用内插器400互连三个或更多衬底。
内插器400可以由环氧树脂、玻璃纤维加强的环氧树脂、陶瓷材料或诸如聚酰亚胺的聚合物材料形成。在其它实施方式中，内插器可以由交替的刚性或柔性材料形成，其可以包括上文描述为用于半导体衬底中的相同材料，例如硅、锗和其它III-V族和IV族材料。
内插器可以包括金属互连408和通孔410，包括但不限于穿硅通孔(TSV)412。内插器400还可以包括嵌入式器件414，包括无源和有源器件。这样的器件包括但不限于电容器、解耦电容器、电阻器、电感器、熔断器、二极管、变压器、传感器和静电放电(ESD)器件。还可以在内插器400上形成更复杂的器件，例如射频(RF)器件、功率放大器、功率管理器件、天线、阵列、传感器和MEMS器件。根据本发明的实施例，本文公开的设备或工艺可以用于内插器400的制造中。
尽管上面已经描述了具体实施例，但即使相对于特定的特征仅描述了单个实施例，这些实施例也并非旨在限制本公开的范围。在本公开中所提供的特征的示例除非另有说明否则旨在为说明性的而非限制性的。以上描述旨在涵盖将对本领域的技术人员显而易见的具有本公开的有益效果的那些替代物、修改和等同物。
本公开的范围包括本文所公开的任何特征或特征的组合(明示或暗示)，或其任何概括，不管它是否减轻本文所解决的任何或全部问题。因此，在本申请(或要求享有其优先权的申请)进行期间可以针对特征的任何此类组合做出新的权利要求。具体地，参考所附权利要求，可以将从属权利要求的特征与独立权利要求的特征组合，并可以通过任何适当方式而不是仅仅通过所附权利要求中列举的具体组合来组合来自相应独立权利要求的特征。
以下示例涉及其它实施例。不同实施例的各种特征可以通过各种方式与包括的一些特征组合并排除其它特征以适应多种不同应用。
示例性实施例1：一种二极管包括半导体衬底、形成在衬底上方的硬掩模、与硬掩模的侧面相邻的第一材料的垂直取向的部件、以及在硬掩模的顶部上的第一材料的横向取向的部件。横向取向的部件被定向在第一方向和第二方向上。第二材料位于第一材料顶部上。第二材料形成肖特基势垒。
示例性实施例2：根据示例性实施例1所述的二极管，其中从硬掩模的第一侧和硬掩模的第二侧引导横向取向的部件。
示例性实施例3：根据示例性实施例1所述的二极管，其中所述硬掩模防止来自衬底的缺陷到达第一材料。
示例性实施例4：根据示例性实施例1所述的二极管，其中所述硬掩模包括氮化物材料。
示例性实施例5：根据示例性实施例1所述的二极管，其中氮化镓层位于衬底上并位于硬掩模下方。
示例性实施例6：根据示例性实施例1所述的二极管，其中肖特基金属形成在肖特基势垒上方。
示例性实施例7：根据示例性实施例1、2、3、4、5或6所述的二极管，其中所述二极管是肖特基二极管。
示例性实施例8：一种半导体器件包括晶体管和二极管。二极管包括半导体衬底、形成在衬底上方的硬掩模、与硬掩模的侧面相邻的第一材料的垂直取向的部件、以及在硬掩模的顶部上的第一材料的横向取向的部件。横向取向的部件被定向在第一方向和第二方向上。第二材料形成在第一材料上方。第二材料形成肖特基势垒。
示例性实施例9：根据示例性实施例8所述的半导体器件，其中从硬掩模的第一侧和硬掩模的第二侧引导横向取向的部件。
示例性实施例10：根据示例性实施例8所述的半导体器件，其中所述硬掩模防止来自衬底的缺陷到达第一材料。
示例性实施例11：根据示例性实施例8所述的半导体器件，其中所述硬掩模包括氮化物材料。
示例性实施例12：根据示例性实施例8、9、10或11所述的半导体器件，其中氮化镓层位于衬底上并位于硬掩模下方。
示例性实施例13：根据权利要求1所述的半导体器件，其中肖特基金属形成在所述肖特基势垒上方。
示例性实施例14：根据权利要求13所述的半导体器件，其中所述二极管是肖特基二极管。
示例性实施例15：一种方法，包括：形成半导体衬底，在衬底上方形成硬掩模，形成与硬掩模的侧面相邻的第一材料的垂直取向的部件，以及在硬掩模的顶部上形成第一材料的横向取向的部件。横向取向的部件被定向在第一方向和第二方向上。第二材料形成在第一材料上方，所述第二材料形成肖特基势垒。
示例性实施例16：根据示例性实施例15所述的方法，其中从硬掩模的第一侧和硬掩模的第二侧引导横向取向的部件。
示例性实施例17：根据示例性实施例15所述的方法，其中所述硬掩模防止来自衬底的缺陷到达第一材料。
示例性实施例18：根据示例性实施例15所述的方法，其中所述硬掩模包括HSON。
示例性实施例19：根据示例性实施例15所述的方法，其中GaN层位于衬底上并位于硬掩模下方。
示例性实施例20：根据示例性实施例15所述的方法，其中肖特基金属形成在肖特基势垒上方。

Claims (20)

1.一种二极管，包括：
半导体衬底；
在所述衬底上方形成的硬掩模；
与所述硬掩模的侧面相邻的第一材料的垂直取向的部件；
在所述硬掩模的顶部上的所述第一材料的横向取向的部件，所述横向取向的部件被定向在第一方向和第二方向上；以及
所述第一材料上方的第二材料，所述第二材料形成肖特基势垒。
2.根据权利要求1所述的二极管，其中，从所述硬掩模的第一侧和所述硬掩模的第二侧引导所述横向取向的部件。
3.根据权利要求1所述的二极管，其中，所述硬掩模防止来自所述衬底的缺陷到达所述第一材料。
4.根据权利要求1所述的二极管，其中，所述硬掩模包括氮化物材料。
5.根据权利要求1所述的二极管，其中，氮化镓层位于所述衬底上并位于所述硬掩模下方。
6.根据权利要求1所述的二极管，其中，肖特基金属形成在所述肖特基势垒上方。
7.根据权利要求1、2、3、4、5或6所述的二极管，其中，所述二极管是肖特基二极管。
8.一种半导体器件，包括：
晶体管：以及
二极管，所述二极管包括：
半导体衬底；
在所述衬底上方形成的硬掩模；
与所述硬掩模的侧面相邻的第一材料的垂直取向的部件；
在所述硬掩模的顶部上的所述第一材料的横向取向的部件，所述横向取向的部件被定向在第一方向和第二方向上；以及
所述第一材料上方的第二材料，所述第二材料形成肖特基势垒。
9.根据权利要求8所述的半导体器件，其中，从所述硬掩模的第一侧和所述硬掩模的第二侧引导所述横向取向的部件。
10.根据权利要求8所述的半导体器件，其中，所述硬掩模防止来自所述衬底的缺陷到达所述第一材料。
11.根据权利要求8所述的半导体器件，其中，所述硬掩模包括氮化物材料。
12.根据权利要求8、9、10或11所述的半导体器件，其中，氮化镓层位于所述衬底上并位于所述硬掩模下方。
13.根据权利要求8所述的半导体器件，其中，肖特基金属形成在所述肖特基势垒上方。
14.根据权利要求13所述的半导体器件，其中，所述二极管是肖特基二极管。
15.一种方法，包括：
形成半导体衬底；
在所述衬底上方形成硬掩模；
形成与所述硬掩模的侧面相邻的第一材料的垂直取向的部件；
在所述硬掩模的顶部上形成所述第一材料的横向取向的部件，所述横向取向的部件被定向在第一方向和第二方向上；以及
在所述第一材料上方形成第二材料，所述第二材料形成肖特基势垒。
16.根据权利要求15所述的方法，其中，从所述硬掩模的第一侧和所述硬掩模的第二侧引导所述横向取向的部件。
17.根据权利要求15所述的方法，其中，所述硬掩模防止来自所述衬底的缺陷到达所述第一材料。
18.根据权利要求15所述的方法，其中，所述硬掩模包括氮化物材料。
19.根据权利要求15所述的方法，其中，氮化镓层位于所述衬底上并位于所述硬掩模下方。
20.根据权利要求15、16、17、18或19所述的方法，其中，肖特基金属形成在所述肖特基势垒上方。
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