CN110634800A - Method for forming metal gate - Google Patents
Method for forming metal gate Download PDFInfo
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- CN110634800A CN110634800A CN201910842011.7A CN201910842011A CN110634800A CN 110634800 A CN110634800 A CN 110634800A CN 201910842011 A CN201910842011 A CN 201910842011A CN 110634800 A CN110634800 A CN 110634800A
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 80
- 239000002184 metal Substances 0.000 title claims abstract description 80
- 238000000034 method Methods 0.000 title claims abstract description 62
- 230000008569 process Effects 0.000 claims abstract description 41
- 229910010038 TiAl Inorganic materials 0.000 claims abstract description 25
- 238000005530 etching Methods 0.000 claims abstract description 25
- 239000011368 organic material Substances 0.000 claims description 27
- 238000000151 deposition Methods 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 7
- 229920005591 polysilicon Polymers 0.000 claims description 7
- VEXZGXHMUGYJMC-UHFFFAOYSA-N Hydrochloric acid Chemical compound Cl VEXZGXHMUGYJMC-UHFFFAOYSA-N 0.000 claims description 6
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims description 6
- 238000004519 manufacturing process Methods 0.000 claims description 6
- 238000005498 polishing Methods 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 4
- 239000007864 aqueous solution Substances 0.000 claims description 3
- 238000001312 dry etching Methods 0.000 claims description 3
- 238000001039 wet etching Methods 0.000 claims description 3
- 238000010521 absorption reaction Methods 0.000 claims description 2
- 239000002253 acid Substances 0.000 claims description 2
- 230000003647 oxidation Effects 0.000 claims description 2
- 238000007254 oxidation reaction Methods 0.000 claims description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims 5
- 230000009286 beneficial effect Effects 0.000 claims 1
- 229920002120 photoresistant polymer Polymers 0.000 claims 1
- 230000008021 deposition Effects 0.000 abstract description 6
- 230000007547 defect Effects 0.000 abstract description 5
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 229910044991 metal oxide Inorganic materials 0.000 abstract 1
- 150000004706 metal oxides Chemical class 0.000 abstract 1
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 16
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 5
- 230000006872 improvement Effects 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 239000000377 silicon dioxide Substances 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000005429 filling process Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 235000012239 silicon dioxide Nutrition 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 238000009736 wetting Methods 0.000 description 2
- 230000004075 alteration Effects 0.000 description 1
- BLJNPOIVYYWHMA-UHFFFAOYSA-N alumane;cobalt Chemical compound [AlH3].[Co] BLJNPOIVYYWHMA-UHFFFAOYSA-N 0.000 description 1
- UQZIWOQVLUASCR-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti] UQZIWOQVLUASCR-UHFFFAOYSA-N 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000003487 electrochemical reaction Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 238000002294 plasma sputter deposition Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 230000005641 tunneling Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823437—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The invention discloses a method for forming a metal grid, which is characterized in that after TiAl deposition of an NMOS (N-channel metal oxide semiconductor), a back etching process is added, a work function layer at the top of the metal grid is etched, and a bell mouth shape is formed, so that a process window of subsequent grid metal filling is enlarged, the defect of metal grid filling is reduced, and the reliability is improved.
Description
Technical Field
The invention relates to the field of semiconductor device manufacturing processes, in particular to a method for forming a metal gate in a gate last process.
Background
Along with the continuous reduction of the size of the device, the thickness of a grid medium is continuously reduced, the leakage current of the grid is increased, and under the condition of less than 5nm, SiO (silicon dioxide) is generated due to the tunneling effect of electrons2The leakage current generated as a gate dielectric is unacceptable. High dielectric constant (high-k) medium is adopted to replace SiO2The equivalent silicon dioxide insulation thickness can be effectively reduced, and the physical thickness of a gate dielectric can be increased, so that the gate leakage is blocked at the source. At present, two processes, namely a Gate-first process and a Gate-last process, can be adopted in a 32nm node to obtain a High-dielectric constant Metal Gate (HKMG) structure. In a 28nm HK gate-last process, namely a Replacement Metal Gate (RMG) process, a High-K material does not need to undergo a High-temperature process, and the drift of a threshold voltage Vt can be effectively reduced, so that the reliability of a device is improved, but the RMG process needs more process steps, and more challenges are brought to manufacturing.
As the critical dimensions of integrated circuits continue to shrink, metal filling in the post-metal gate process becomes increasingly difficult at the 22nm and below technology nodes. High aspect ratios result in voids of metal fill, which leads to high resistance, reliability, and the like.
In the mainstream 22nm integrated circuit process for preparing metal gate, after removing the dummy polysilicon gate, a layer of tantalum nitride (TaN) of about 20 Å is deposited as an anti-diffusion layer, a layer of titanium nitride (TiN) is deposited as a work function layer of PMOS, the TiN layer of NMOS region is removed by one-time photoetching and etching process, the TiN of PMOS is remained, the deposition of the TiAl of the work function metal layer of NMOS is followed, and finally the deposition of the anti-diffusion layer, the Al filling of the metal gate and the CMP are carried out.
In the mainstream 22nm integrated circuit process, the filling problem of the metal gate has the following two solutions:
one, optimization of the AL metal fill process parameters, such as using a lower AL reflow temperature at the top and a higher AL reflow temperature at the bottom, can negatively impact the device turn-on voltage Vt.
Secondly, the wetting layer material is changed from titanium aluminum to cobalt aluminum, so that the filling capacity of metal AL can be improved, and the influence on the device can not be caused. But the change of the material is easy to generate electrochemical reaction defects when the subsequent chemical mechanical polishing is carried out.
Disclosure of Invention
The technical problem to be solved by the present invention is to provide a method for forming a metal gate, which improves a process window for filling the metal gate.
The invention relates to a method for forming a metal gate, which is a manufacturing process for forming the metal gate in a gate last process and comprises the following process steps:
firstly, after removing the virtual polysilicon gate, depositing a TiN layer as the work function layer of the PMOS, and then removing the TiN layer in the NMOS area by etching.
And secondly, depositing a TiAl layer as a work function layer of the NMOS.
And thirdly, depositing a layer of organic material on the surface of the wafer, and filling the organic material into the metal grid electrode by utilizing the good filling property of the organic material.
And fourthly, etching for the first time, carrying out an organic material back etching process, and opening the top area of the metal grid.
And fifthly, etching for the second time to remove the TiN and TiAl work function layer with the thickness of 10-20nm at the top of the metal grid.
And sixthly, removing the residual organic materials.
And step seven, filling the metal gate electrode with Al.
And eighthly, carrying out chemical mechanical polishing CMP on the metal gate Al.
The further improvement is that the thickness of the organic material is 1000-1500 Å, and the organic material is completely filled in the space for forming the grid electrode.
The further improvement is that in the fourth step, dry etching is adopted for the first etching, and the top of the metal gate is opened by 10-20 nm.
In the fifth step, a wet etching process is adopted for the second etching, and a mixed aqueous solution of hydrochloric acid and hydrogen peroxide is used for removing the TiN and TiAl work function layer with the thickness of 10-20nm at the top of the metal gate; for NMOS, a TiAl work function layer; for PMOS, it is TiN plus TiAl work function layer; after the etching is finished, the organic material of the grid filling space is reserved.
In a further improvement, the organic material is used to protect a work function layer in a metal gate.
In the fifth step, the work function layer on the top of the metal gate is removed, so that the filling opening of the gate is enlarged to form a bell mouth, and the subsequent filling of the metal gate material is facilitated.
In a further improvement, the organic material is DUO which is a deep ultraviolet absorption oxidation material.
According to the invention, after deposition of a work function metal layer TiAl of an NMOS in the prior art, an additional etching process (without a photomask) is added, the work function layer (NMOS: TiAl; PMOS: TiAl + TiN) on the top of a metal gate is etched to form a bell mouth shape, then filling of the metal gate Al is carried out, the filling difficulty is reduced by the bell mouth shape opening, and the process window of filling the metal gate is enlarged.
Drawings
FIGS. 1 to 8 are schematic views of the process steps of the present invention.
FIG. 9 is a flow chart of the process steps of the present invention.
Description of the reference numerals
1 is a substrate or epitaxy, 2 is an isolation trench, 3 is a space for making a metal gate formed after dummy polysilicon removal, 4 is TiN, 5 is TiAl, 6 is organic material DUO, and 7 is metallic Al.
Detailed Description
In order to make the content of the present invention more comprehensible, the following detailed description is given with reference to specific embodiments and accompanying drawings, but the technical content related to the present invention is not limited to the specific embodiments given.
The invention is described in further detail below with reference to the figures and specific examples. Advantages and features of the present invention will become apparent from the following description and from the claims. It is to be noted that the drawings are in a very simplified form and are all used in a non-precise ratio for the purpose of facilitating and distinctly aiding in the description of the embodiments of the invention.
The invention is mainly applied to the manufacturing process of field effect transistors with the wavelength of 22nm and below: as the critical dimensions of integrated circuits continue to shrink, metal filling in the post-metal gate process becomes increasingly difficult at the 22nm and below technology nodes. High aspect ratios result in voids of metal fill, which leads to high resistance, reliability, and the like. The invention adds a back etching process after the deposition of TiAl of an NMOS work function layer in a post metal grid process. And etching off the work function layer (NMOS: TiAl; PMOS: TiAl + TiN) on the top of the metal gate to form a bell mouth shape, thereby increasing the process window of subsequent gate metal filling. The defect of metal gate filling is reduced, and the reliability is improved.
Specifically, the method for forming a metal gate according to the present invention is a process for forming a metal gate in a gate last process, and comprises the following steps:
the first step is to complete the preorder process of the gate-last process and form a virtual polysilicon gate. And then depositing a TiN layer as a work function layer of the PMOS after the virtual polysilicon gate is removed, and then removing the TiN layer of the NMOS area by etching, wherein the PMOS area is not processed.
And secondly, depositing a layer of TiAl as a work function layer of the NMOS, wherein the work function layer in the PMOS area is a composite layer of the TiN layer and the TiAl.
The two process steps are shown in fig. 1 to 3.
It should be particularly noted that, for simplicity and clarity of description, other structures of the device are omitted from the drawings of the present invention, and only a part of the structure related to the present invention is shown, and those skilled in the art should be able to clearly judge the omitted other structural components of the device, without affecting understanding of the technical solution of the present invention.
The third step is to deposit a layer of organic material on the wafer surface, which has better filling performance compared to metal, and has better filling effect for the trench or gap with high aspect ratio, and fill the space to be made with the metal gate formed after removing the dummy polysilicon with good filling performance, the organic material is easy to fill and remove, the embodiment is preferably DUO (Deep ultraviolet Absorbing Oxide), the thickness of which is 1000-1500 Å.
And fourthly, etching for the first time, namely performing a back etching process of the organic material DUO by adopting a dry etching process, as shown in fig. 5, opening the top of the metal gate to be 10-20nm downwards, and reserving the DUO material at the lower part of the metal gate space.
And fifthly, etching for the second time, namely removing the TiN and TiAl work function layer with the top of the metal gate being 10-20nm downwards by using a mixed aqueous solution of hydrochloric acid and hydrogen peroxide by adopting a wet etching process. As shown in fig. 6.
And sixthly, removing all residual organic materials DUO by adopting an acid tank process. After the organic material is removed, a work function layer is remained in the forming space of the metal grid electrode, the work function layer at the opening above the space is removed, a larger opening is formed, the larger opening degree enables the deposited film to have higher quality, and the space filling effect is better.
And step seven, filling the metal grid electrode with Al, wherein the deposited metal film completely fills the space of the metal grid electrode, and simultaneously, the surface of the whole device is covered with a layer of metal film. The metal filling process may employ a physical vapor deposition method such as a plasma sputtering process. As shown in fig. 7.
And eighthly, carrying out chemical mechanical polishing CMP on the metal gate Al. And removing the metal Al film on the surface of the device to form a metal gate. As shown in fig. 8. Through the process, the formed metal grid has good filling effect, and no gap or cavity exists inside the metal grid.
The invention does not bring corresponding defects because the invention does not relate to the change of the metal gate AL filling process and the wetting layer material.
The invention adds a back etching process after the deposition of TiAl of an NMOS work function layer in a post metal grid process. And etching off the work function layer (NMOS: TiAl; PMOS: TiAl + TiN) on the top of the metal gate to form a bell mouth shape, thereby increasing the process window of subsequent gate metal filling. The defect of metal gate filling is reduced, and the reliability is improved.
The above are merely preferred embodiments of the present invention, and are not intended to limit the present invention. Various modifications and alterations to this invention will become apparent to those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (8)
1. A method for forming a metal gate is a manufacturing process for forming the metal gate in a gate last process, and is characterized in that: comprises the following steps:
firstly, after removing a virtual polysilicon grid, depositing a TiN layer as a work function layer of a PMOS, and then removing the TiN layer of an NMOS area by etching;
secondly, depositing a TiAl layer as a work function layer of the NMOS;
thirdly, depositing a layer of organic material on the surface of the wafer, and filling the organic material into the metal grid electrode by utilizing the good filling property of the organic material;
fourthly, etching for the first time, carrying out an organic material back etching process, and opening the top area of the metal grid;
fifthly, etching for the second time to remove the TiN and TiAl work function layer with the thickness of 10-20nm at the top of the metal grid;
sixthly, removing the residual organic materials;
step seven, filling metal gate Al;
and eighthly, carrying out chemical mechanical polishing CMP on the metal gate Al.
2. The method of claim 1, wherein the organic material has a thickness of 1000 to 1500 Å, and the organic material completely fills the space for forming the gate.
3. The method of claim 1, wherein: and in the fourth step, dry etching is adopted for the first etching, and the top of the metal gate is opened by 10-20 nm.
4. The method of claim 1, wherein: in the fifth step, the second etching adopts a wet etching process, and a mixed aqueous solution of hydrochloric acid and hydrogen peroxide is used for removing the TiN and TiAl work function layer with the thickness of 10-20nm on the top of the metal gate; for NMOS, a TiAl work function layer; for PMOS, it is TiN plus TiAl work function layer; after the etching is finished, the organic material of the grid filling space is reserved.
5. The method of claim 1, wherein: the organic material is used for protecting a work function layer in the metal grid electrode.
6. The method of claim 1, wherein: and in the fifth step, removing the work function layer at the top of the metal grid to enlarge the filling opening of the grid and form a horn mouth, thereby being beneficial to the subsequent filling of the metal grid material.
7. The method of claim 1, wherein: and removing redundant organic materials through an acid tank photoresist removing process.
8. The method of forming a metal gate of any of claims 1 to 7, wherein: the organic material is DUO which is a deep ultraviolet absorption oxidation material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910842011.7A CN110634800A (en) | 2019-09-06 | 2019-09-06 | Method for forming metal gate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910842011.7A CN110634800A (en) | 2019-09-06 | 2019-09-06 | Method for forming metal gate |
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| CN110634800A true CN110634800A (en) | 2019-12-31 |
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| CN201910842011.7A Pending CN110634800A (en) | 2019-09-06 | 2019-09-06 | Method for forming metal gate |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101789368A (en) * | 2008-09-12 | 2010-07-28 | 台湾积体电路制造股份有限公司 | Semiconductor device and manufacture method thereof |
| CN106601606A (en) * | 2015-10-19 | 2017-04-26 | 中芯国际集成电路制造(上海)有限公司 | NMOS device, semiconductor device, and production method of semiconductor device |
| CN108447826A (en) * | 2017-02-16 | 2018-08-24 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacturing method and electronic device |
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- 2019-09-06 CN CN201910842011.7A patent/CN110634800A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101789368A (en) * | 2008-09-12 | 2010-07-28 | 台湾积体电路制造股份有限公司 | Semiconductor device and manufacture method thereof |
| CN106601606A (en) * | 2015-10-19 | 2017-04-26 | 中芯国际集成电路制造(上海)有限公司 | NMOS device, semiconductor device, and production method of semiconductor device |
| CN108447826A (en) * | 2017-02-16 | 2018-08-24 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and its manufacturing method and electronic device |
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