CN110632999A

CN110632999A - Power management device of storage equipment

Info

Publication number: CN110632999A
Application number: CN201810663392.8A
Authority: CN
Inventors: 倪勇; 李义
Original assignee: Beijing Memblaze Technology Co Ltd
Current assignee: Beijing Memblaze Technology Co Ltd
Priority date: 2018-06-25
Filing date: 2018-06-25
Publication date: 2019-12-31

Abstract

A power management apparatus for a storage device is provided. The disclosed storage device includes: the device comprises a control component, an NVM chip, an interface and a power management component; the power management component obtains a first power input from the interface and provides power to the control component over a first power channel and provides power to the NVM chip over a second power channel.

Description

Power management device of storage equipment

Technical Field

The present application relates to a storage device, and more particularly, to a power management apparatus of a storage device.

Background

FIG. 1 illustrates a block diagram of a solid-state storage device. The solid-state storage device 102 is coupled to a host for providing storage capabilities to the host. The host and the solid-state storage device 102 may be coupled by various methods, including but not limited to, connecting the host and the solid-state storage device 102 by, for example, SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIE (Peripheral Component interconnect Express), NVMe (NVM Express, high-speed nonvolatile storage), ethernet, fibre channel, wireless communication network, etc. The host may be an information processing device, such as a personal computer, tablet, server, portable computer, network switch, router, cellular telephone, personal digital assistant, etc., capable of communicating with the storage device in the manner described above. The Memory device 102 includes an interface 103, a control section 104, one or more NVM chips 105, and a DRAM (Dynamic Random Access Memory) 110.

NAND flash Memory, phase change Memory, FeRAM (Ferroelectric RAM), MRAM (magnetoresistive Memory), RRAM (Resistive Random Access Memory), etc. are common NVM.

The interface 103 may be adapted to exchange data with a host by means such as SATA, IDE, USB, PCIE, NVMe, SAS, ethernet, fibre channel, etc.

The control unit 104 is used to control data transfer between the interface 103, the NVM chip 105, and the DRAM110, and also used for memory management, host logical address to flash physical address mapping, erase leveling, bad block management, and the like. The control component 104 can be implemented in various manners of software, hardware, firmware, or a combination thereof, for example, the control component 104 can be in the form of an FPGA (Field-programmable gate array), an ASIC (Application-specific integrated Circuit), or a combination thereof. The control component 104 may also include a processor or controller in which software is executed to manipulate the hardware of the control component 104 to process IO (Input/Output) commands. The control component 104 may also be coupled to the DRAM110 and may access data of the DRAM 110. FTL tables and/or cached IO command data may be stored in the DRAM.

Control section 104 includes a flash interface controller (or referred to as a media interface controller, a flash channel controller) that is coupled to NVM chip 105 and issues commands to NVM chip 105 in a manner that conforms to an interface protocol of NVM chip 105 to operate NVM chip 105 and receive command execution results output from NVM chip 105. Known NVM chip interface protocols include "Toggle", "ONFI", etc.

The storage device further comprises power management means for providing power to the various components of the storage device. The power supply circuit of the storage device is shown in chinese patent applications 201210258780.0 and 201510347811.3 as an example of a power management apparatus. Fig. 2 shows the power management device as an integrated circuit. The Vin pin of the power management integrated circuit shown in fig. 2 receives an external power supply, and provides power of, for example, 3.3V through the SW pin, and receives a feedback signal to the power supply voltage through the FB pin to adaptively adjust the output voltage of the SW pin so that the output voltage is stabilized at a specified value (for example, 3.3V), and the PG signal of the circuit of the power management integrated circuit shown in fig. 2 indicates whether the current power supply is normal.

Fig. 3 illustrates another power management integrated circuit. The Vin pin of the power integrated circuit shown in fig. 3 receives external power, including multiple power outputs (Vout1 and Vout 2). Taking a power output Vout1 as an example, the LX1 pin of the power management integrated circuit provides power, and receives a feedback signal of the power supply voltage provided to the LX1 pin through the FB1 pin to adaptively adjust the output voltage of the LX1 pin. The power management integrated circuit shown in fig. 3 further includes a controller (not shown) that can be programmed to execute various programs to control the GPIO pin (general purpose input/output pin) and to control the on/off of the power outputs and the timing thereof. The power management integrated circuit shown in fig. 3 further includes one or more digital-to-analog converters/analog-to-digital converters, and the controller collects or monitors external signals through the analog-to-digital converters/analog-to-digital converters, for example, collects voltage/current values on the Vin pin to calculate power, or collects ambient temperature, etc. The controller also communicates with external devices through interfaces such as a serial port (UART), I2C and the like.

Disclosure of Invention

Power management devices are continually being developed with improvements in storage devices to provide more reliable power, higher power efficiency, and richer functionality.

According to a first aspect of the present application, there is provided a first storage device according to the first aspect of the present application, comprising: the device comprises a control component, an NVM chip, an interface and a power management component; the power management component obtains a first power input from the interface and provides power to the control component through a first power channel and provides power to the NVM chip through a second power channel; the memory device further includes a voltage feedback circuit; the voltage feedback circuit receives the self-adaptive voltage adjusting signal provided by the control part and provides a voltage feedback signal for the first power supply channel; the power management component adjusts the voltage of the power provided by the first power supply channel according to the voltage feedback signal received by the first power supply channel.

According to a first storage device of a first aspect of the present application, there is provided a second storage device of the first aspect of the present application, wherein the power management section lowers a voltage of power supplied to the control section through the first power supply channel when the adaptive voltage adjustment signal indicates that the control section supports the adaptive voltage adjustment function; and the power management component does not reduce the voltage of the power provided to the control component over the first power supply channel when the adaptive voltage adjustment signal indicates that the control component does not support the adaptive voltage adjustment function.

According to the first or second storage device of the first aspect of the present application, there is provided the third storage device of the first aspect of the present application, wherein the power management component supplies power to the IO interface of the NVM chip and the IO interface of the control component through a third channel.

According to one of the first to third memory devices of the first aspect of the present application, there is provided the fourth memory device according to the first aspect of the present application, further comprising a DRAM component; the power management component provides power to the DRAM component through a fourth power channel.

According to a fourth memory device of the first aspect of the present application, there is provided the fifth memory device of the first aspect of the present application, wherein the power management unit supplies power to the IO interface of the DRAM unit and the IO interface of the control unit coupled to the DRAM unit through a fifth power supply channel.

According to one of the first to fifth storage devices of the first aspect of the present application, there is provided the sixth storage device according to the first aspect of the present application, further comprising a backup power supply; the power management component provides power for charging to the backup power source through a sixth power supply channel.

According to one of the first to sixth storage devices of the first aspect of the present application, there is provided the seventh storage device of the first aspect of the present application, further comprising a voltage conversion circuit that converts the first power input into the second power output, the power management section obtaining the first power input and the second power output.

According to one of the first to sixth storage devices of the first aspect of the present application, there is provided the eighth storage device of the first aspect of the present application, wherein the power management section further obtains the second power input from the interface.

According to one of the first to eighth storage devices of the first aspect of the present application, there is provided the ninth storage device of the first aspect of the present application, wherein the voltage feedback circuit outputs a first voltage feedback signal to the power supply management section when the adaptive voltage adjustment signal indicates that the control section supports the adaptive voltage adjustment function; when the adaptive voltage regulation signal indicates that the control component does not support the adaptive voltage regulation function, the voltage feedback circuit outputs a second voltage feedback signal to the power management component; and wherein the first voltage feedback signal is lower in voltage than the second voltage feedback signal.

According to a ninth memory device of the first aspect of the present application, there is provided the tenth memory device of the first aspect of the present application, wherein the voltage feedback circuit includes a first resistor and a second resistor connected in series, the first resistor and the second resistor connected in series being applied with a voltage of the output of the first power supply channel; the junction of the first and second resistors in series provides a voltage feedback signal to the power management component and also provides a voltage to the switch and third resistor in series.

According to a tenth memory device of the first aspect of the present application, there is provided the eleventh memory device of the first aspect of the present application, wherein the series-connected switch and the third resistor are connected in parallel with the second resistor.

According to one of the first to eleventh memory devices of the first aspect of the present application, there is provided the twelfth memory device of the first aspect of the present application, wherein the power management section, in response to the interface of the memory device providing the first power input, first provides the control section with an active reset signal, and then provides the control section, the NVM chip in sequence, and then provides the control section with an inactive reset signal.

According to a twelfth storage device of the first aspect of the present application, there is provided the thirteenth storage device of the first aspect of the present application, wherein the power management section supplies power to the backup power supply before supplying power to the control section.

According to one of the first to thirteenth storage devices of the first aspect of the present application, there is provided the fourteenth storage device of the first aspect of the present application, wherein the power management section provides an active interrupt signal to the control section in response to disappearance of the first power input provided by the interface of the storage device.

According to a second aspect of the present application, there is provided a first storage device according to the second aspect of the present application, comprising: the device comprises a control component, an NVM chip, an interface and a power management component; the power management component obtains a first power input from the storage interface and provides power to the control component through a first power channel and provides power to the NVM chip through a second power channel; the power management component further provides a reset signal and one or more interrupt signals to the control component; the first communication interface of the power management component is also coupled to the communication interface of the control component.

According to a first storage device of the second aspect of the present application, there is provided a second storage device according to the second aspect of the present application, further comprising a debug interface connector; the reset signal and one or more interrupt signals provided by the power management component to the control component are also connected to the debug interface connector; the first communication interface of the power management component is also coupled to the debug interface connector.

According to a second storage device of the second aspect of the present application, there is provided a third storage device of the second aspect of the present application, wherein after the debug interface connector of the storage device is coupled to a debug device, the debug device obtains the provided reset signal and one or more interrupt signals of the power management unit, and the communication interface of the debug device is further coupled to the communication interface of the power management unit.

According to a second or third storage device of the second aspect of the present application, there is provided a fourth storage device according to the second aspect of the present application, wherein

The communication interface of the power management component is coupled to the communication interface of the control component through a switch; a control terminal of the switch is coupled to the debug interface connector; when the debugging interface connector of the storage device is coupled with a debugging device, the debugging device is coupled to the control end of the switch through the debugging interface connector so as to disconnect the coupling of the communication interface of the power management component to the communication interface of the control component.

According to one of the first to fourth storage devices of the second aspect of the present application, there is provided the fifth storage device of the second aspect of the present application, wherein the adaptive voltage regulation signal provided by the control component is coupled to the debug interface connector.

According to a fifth storage device of the second aspect of the present application, there is provided the sixth storage device of the second aspect of the present application, wherein the debug device obtains the adaptive voltage adjustment signal provided by the control unit after the debug interface connector of the storage device is coupled to the debug device.

According to one of the first to sixth storage devices of the second aspect of the present application, there is provided the seventh storage device of the second aspect of the present application, wherein the second communication interface of the control component is coupled to the debug interface connector; and when the debugging interface connector of the storage device is coupled with the debugging device, the second communication interface of the debugging device is communicated with the second communication interface of the control component.

According to the first storage device of the second aspect of the present application, there is provided the eighth storage device of the second aspect of the present application, further comprising a debug device; the reset signal and one or more interrupt signals provided by the power management component to the control component are also connected to the debug device; the communication interface of the power management component is also coupled to the debugging device.

According to an eighth storage device of the second aspect of the present application, there is provided the ninth storage device of the second aspect of the present application, wherein the communication interface of the power management section is coupled to the communication interface of the control section through a switch; a control terminal of the switch is coupled to the debugging device; the debugging device controls the switch to disconnect the coupling of the communication interface of the power management unit to the communication interface of the control unit.

According to an eighth or ninth storage device of the second aspect of the present application, there is provided the tenth storage device of the second aspect of the present application, wherein the adaptive voltage adjustment signal provided by the control unit is coupled to the debugging device.

According to one of the eighth to tenth storage devices of the second aspect of the present application, there is provided the eleventh storage device of the second aspect of the present application, further comprising a debug interface connector; a second communication interface of the commissioning device is coupled to the commissioning interface connector; and a second communication interface of the control component is coupled to the storage interface.

According to one of the first to eleventh memory devices of the second aspect of the present application, there is provided the twelfth memory device of the second aspect of the present application, wherein the memory interface further includes a pin for SMBUS; the pin for the SMBUS is coupled to a second communication interface of the power management component; the power management component responds to the SMBUS access request to the storage device through a second communication interface.

According to a twelfth storage device of the second aspect of the present application, there is provided the thirteenth storage device of the second aspect of the present application, further comprising a commissioning device; wherein the power management component obtains first information from the control component through a first communication interface thereof; the power management component provides the first information through a second communication interface in response to an SMBUS access request to the storage device.

According to a twelfth or thirteenth storage device of the second aspect of the present application, there is provided the fourteenth storage device according to the second aspect of the present application, further comprising a debug device; also includes a second non-volatile memory; the second non-volatile memory is coupled to the pin for SMB, the second non-volatile memory also responding to SMBUS access requests to the storage device.

According to a thirteenth or fourteenth storage device of the second aspect of the present application, there is provided the fifteenth storage device of the second aspect of the present application, wherein the third communication interface of the control unit is coupled to the pin for SMB, and the control unit also responds to an SMBUS access request to the storage device through the third communication interface.

According to a third aspect of the present application, there is provided a first storage device according to the third aspect of the present application, comprising: the device comprises a control component, an NVM chip, an interface and a power management component; the power management component obtains a first power input from the interface and provides power to the control component over a first power channel and provides power to the NVM chip over a second power channel.

According to the first memory device of the third aspect of the present application, there is provided the second memory device of the third aspect of the present application, further comprising a voltage feedback circuit; the voltage feedback circuit receives the self-adaptive voltage adjusting signal provided by the control part and provides a voltage feedback signal for the first power supply channel; the power management component adjusts the voltage of the power provided by the first power supply channel according to the voltage feedback signal received by the first power supply channel.

According to a second storage device of the third aspect of the present application, there is provided the third storage device of the third aspect of the present application, wherein the power supply management section lowers a voltage of the power supplied to the control section through the first power supply channel when the adaptive voltage adjustment signal indicates that the control section supports the adaptive voltage adjustment function; and the power management component does not reduce the voltage of the power provided to the control component over the first power supply channel when the adaptive voltage adjustment signal indicates that the control component does not support the adaptive voltage adjustment function.

According to one of the first to third storage devices of the third aspect of the present application, there is provided the fourth storage device of the third aspect of the present application, wherein the power management unit supplies power to the IO interface of the NVM chip and the IO interface of the control unit through a third channel.

According to one of the first to fourth memory devices of the third aspect of the present application, there is provided the fifth memory device according to the third aspect of the present application, further comprising a DRAM section; the power management component provides power to the DRAM component through a fourth power channel.

According to a fifth memory device of the third aspect of the present application, there is provided the sixth memory device of the third aspect of the present application, wherein the power management unit supplies power to the IO interface of the DRAM unit and the IO interface of the control unit coupled to the DRAM unit through a fifth power supply channel.

According to one of the first to sixth storage devices of the third aspect of the present application, there is provided the seventh storage device according to the third aspect of the present application, further comprising a backup power supply; the power management component provides power for charging to the backup power source through a sixth power supply channel.

According to one of the first to seventh storage devices of the third aspect of the present application, there is provided the eighth storage device of the third aspect of the present application, further comprising a voltage conversion circuit that converts the first power input into the second power output, the power management section obtaining the first power input and the second power output.

According to one of the first to seventh storage devices of the third aspect of the present application, there is provided the ninth storage device of the third aspect of the present application, wherein the power management section further obtains the second power input from the interface.

According to the second storage device of the third aspect of the present application, there is provided the tenth storage device according to the third aspect of the present application, wherein the voltage feedback circuit outputs the first voltage feedback signal to the power supply managing section when the adaptive voltage adjusting signal indicates that the control section supports the adaptive voltage adjusting function; when the adaptive voltage regulation signal indicates that the control component does not support the adaptive voltage regulation function, the voltage feedback circuit outputs a second voltage feedback signal to the power management component; and wherein the first voltage feedback signal is lower in voltage than the second voltage feedback signal.

According to a tenth memory device of the third aspect of the present application, there is provided the eleventh memory device of the third aspect of the present application, wherein the voltage feedback circuit includes a first resistance and a second resistance connected in series, the first resistance and the second resistance connected in series being applied with a voltage of the output of the first power supply channel; the junction of the first and second resistors in series provides a voltage feedback signal to the power management component and also provides a voltage to the switch and third resistor in series.

According to an eleventh memory device of the third aspect of the present application, there is provided the twelfth memory device of the third aspect of the present application, wherein the series-connected switch and the third resistance are connected in parallel with the second resistance.

According to one of the first to twelfth memory devices of the third aspect of the present application, there is provided the thirteenth memory device according to the third aspect of the present application, wherein the power management section first supplies the control section with an active reset signal in response to the interface of the memory device supplying the first power input, and then supplies the control section, the NVM chip in order, and then supplies the control section with an inactive reset signal.

According to a thirteenth storage device of the third aspect of the present application, there is provided the fourteenth storage device of the third aspect of the present application, wherein the power management section supplies power to the backup power supply before supplying power to the control section.

According to one of the first to fourteenth storage devices of the third aspect of the present application, there is provided the fifteenth storage device of the third aspect of the present application, wherein the power management section provides an active interrupt signal to the control section in response to disappearance of the first power input provided by the interface of the storage device.

According to one of the first to fifteenth memory devices of the third aspect of the present application, there is provided the sixteenth memory device according to the third aspect of the present application, wherein the power management section further supplies a reset signal and one or more interrupt signals to the control section; the first communication interface of the power management component is also coupled to the communication interface of the control component.

According to a sixteenth storage device of the third aspect of the present application, there is provided the seventeenth storage device of the third aspect of the present application, further comprising a debug interface connector; the reset signal and one or more interrupt signals provided by the power management component to the control component are also connected to the debug interface connector; the first communication interface of the power management component is also coupled to the debug interface connector.

According to a seventeenth storage device of the third aspect of the present application, there is provided the eighteenth storage device of the third aspect of the present application, wherein when the debug interface connector of the storage device is coupled with a debug device, the debug device obtains the provided reset signal and one or more interrupt signals of the power management unit, and the communication interface of the debug device is further coupled to the communication interface of the power management unit.

According to a seventeenth or eighteenth storage device of the third aspect of the present application, there is provided the nineteenth storage device of the third aspect of the present application, wherein the communication interface of the power management section is coupled to the communication interface of the control section through a switch; a control terminal of the switch is coupled to the debug interface connector; when the debugging interface connector of the storage device is coupled with a debugging device, the debugging device is coupled to the control end of the switch through the debugging interface connector so as to disconnect the coupling of the communication interface of the power management component to the communication interface of the control component.

According to one of the sixteenth to nineteenth storage devices of the third aspect of the present application, there is provided the twentieth storage device of the third aspect of the present application, wherein the adaptive voltage regulation signal provided by the control component is coupled to the debug interface connector.

According to a twentieth storage device of the third aspect of the present application, there is provided the twenty-first storage device of the third aspect of the present application, wherein the debug device acquires the adaptive voltage adjustment signal provided by the control unit after a debug interface connector of the storage device is coupled to the debug device.

According to one of the sixteenth to twenty-first storage devices of the third aspect of the present application, there is provided a twenty-second storage device according to the third aspect of the present application, wherein the second communication interface of the control component is coupled to the debug interface connector; and when the debugging interface connector of the storage device is coupled with the debugging device, the second communication interface of the debugging device is communicated with the second communication interface of the control component.

According to a sixteenth storage device of the third aspect of the present application, there is provided the twenty-third storage device of the third aspect of the present application, further comprising a debug device; the reset signal and one or more interrupt signals provided by the power management component to the control component are also connected to the debug device; the communication interface of the power management component is also coupled to the debugging device.

According to a twenty-third storage device of the third aspect of the present application, there is provided the twenty-fourth storage device of the third aspect of the present application, wherein the communication interface of the power management section is coupled to the communication interface of the control section through a switch; a control terminal of the switch is coupled to the debugging device; the debugging device controls the switch to disconnect the coupling of the communication interface of the power management unit to the communication interface of the control unit.

According to a twenty-third or twenty-fourth memory device of the third aspect of the present application, there is provided a twenty-fifth memory device according to the third aspect of the present application, wherein the adaptive voltage adjustment signal provided by the control means is coupled to the debugging device.

According to one of the twenty-second to twenty-fifth storage devices of the third aspect of the present application, there is provided a twenty-sixth storage device according to the third aspect of the present application, further comprising a debug interface connector; a second communication interface of the commissioning device is coupled to the commissioning interface connector; and a second communication interface of the control component is coupled to the storage interface.

According to one of the first to twenty-sixth storage devices of the third aspect of the present application, there is provided a twenty-seventh storage device according to the third aspect of the present application, wherein the storage interface further includes a pin for an SMBUS; the pin for the SMBUS is coupled to a second communication interface of the power management component; the power management component responds to the SMBUS access request to the storage device through a second communication interface.

According to a twenty-seventh storage device of the third aspect of the present application, there is provided the twenty-eighth storage device of the third aspect of the present application, wherein the power supply management section acquires the first information from the control section through the first communication interface thereof; the power management component provides the first information through a second communication interface in response to an SMBUS access request to the storage device.

A twenty-seventh or twenty-eighth storage device according to the third aspect of the present application, there is provided the twenty-ninth storage device according to the third aspect of the present application, further comprising a second nonvolatile memory; the second non-volatile memory is coupled to the pin for SMB, the second non-volatile memory also responding to SMBUS access requests to the storage device.

According to one of the twenty-seventh to twenty-ninth storage devices of the third aspect of the present application, there is provided the third storage device of the third aspect of the present application, wherein the third communication interface of the control section is coupled to the pin for SMB, and the control section also responds to an SMBUS access request to the storage device through the third communication interface.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art according to the drawings.

FIG. 1 is a schematic diagram of a prior art solid-state memory device provided herein;

FIG. 2 illustrates a power management device as an integrated circuit;

FIG. 3 illustrates another power management integrated circuit;

FIG. 4 illustrates a schematic diagram of a memory device according to an embodiment of the present application;

FIG. 5 illustrates a schematic diagram of a memory device according to yet another embodiment of the present application;

FIG. 6A illustrates a power-up sequence provided by a power management integrated circuit according to an embodiment of the present application;

FIG. 6B illustrates a power down sequence provided by a power management integrated circuit according to an embodiment of the present application;

FIG. 7 illustrates a schematic diagram of a memory device according to another embodiment of the present application;

FIG. 8 illustrates a schematic diagram of a memory device according to yet another embodiment of the present application; and

FIG. 9 illustrates a schematic diagram of a memory device according to yet another embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application are clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

FIG. 4 illustrates a schematic diagram of a memory device according to an embodiment of the present application. A power management integrated circuit 410 is disposed in the storage device. The power management integrated circuit 10 is used to provide power to the various components of the memory device (control component 104, one or more NVM chips 105, one or more DRAMs 110, etc., see also fig. 1).

The power management integrated circuit 410 includes a plurality of power input pins (Vin1 and Vin2), and a plurality of power channels (CH1, CH2, … … CH6) for outputting power. By way of example, a power input pin (Vin2) is coupled to the interface 103 to draw power to the memory device from the interface 103. In the example of fig. 3, the power supplied from the interface 103 is 12V. Power provided from the interface 103 is coupled to the power input pin Vin through the open source 420. The Vin2_ EN pin of the power management integrated circuit 410 is connected to the control terminal of the switch 420 to control the switch 420 to be turned off or on. Optionally, the power provided by the interface 103 is also passed through a voltage transformation circuit to generate power of other voltage values and coupled to the power input pin Vin 2. Still alternatively, the interface 103 provides two or more paths of power, each coupled to a respective power input pin of the power management integrated circuit. Still by way of example, when the storage device uses the U.2 standard interface 103, the power management ic 410 obtains a single 12V power from the interface 103; when the memory device uses the m.2 standard interface 103, the power management integrated circuit 410 draws a single 3.3V power from the interface 103.

The components of the memory device (control component 104, NVM chip 105, DRAM110, etc.) each require one or more power supplies. The NVM chip 105 needs to be provided with power for the memory cell array (denoted as V1), power for the IO interface (denoted as Vp), and optionally additional power (denoted as Vpp). DRAM110 needs to be provided with power for the memory cell array (denoted V1), power for the IO interface (denoted Vp), and optionally additional power (denoted Vpp). The control component 104 needs to be provided with power for the core circuitry (noted as VDD), power for coupling the IO interface of the NVM chip 105, and power for coupling the IO interface of the DRAM110, and optionally power for its GPIO pins.

Each power supply channel of power management integrated circuit 410 is programmed, for example, to set the output voltage specification and is coupled to the power supply pin of the respective component. Referring to FIG. 4, the power channel CH1 of the power management integrated circuit 410 is used to provide the control unit 104 with power (VDD) for the core circuitry. The power channel CH2 is used to provide power for the IO interface of the DRAM110, and the power channel CH2 is also used to provide power for the IO interface of the control unit 104 coupled to the DRAM110, so that the IO interface of the DRAM110 and the IO interface of the control unit 104 coupled to the DRAM110 use the same specification of power. The power channel CH4 is used to provide power to the IO interface of one or more NVM chips 105, and the power channel CH4 is also used to provide power to the IO interface of the control unit 104 coupled to the NVM chip 105, so that the IO interface of the NVM chip 105 and the IO interface of the control unit 104 coupled to the NVM chip 105 use the same specification of power. The power channel CH3 is used to provide power for the GPIO pin of the control component. The power channel CH5 is used to provide power for the core circuitry for the DRAM 110. The power channel CH6 is used to provide power for the core circuitry for the NVM chip 105. Optionally, power management integrated circuit 410 also includes additional power channels for providing power for charging of a backup power source, such as a storage device. It will be appreciated that the manner in which the power supply channels of the power management circuit 410 are coupled to the components of the memory device may vary, for example, power supply channel CH1 may be used to provide power for the GPIO pins of the control component, and power supply channel CH2 may be used to provide power (VDD) for the core circuitry to the control component 104.

The power management integrated circuit 410 also includes a controller (not shown). The controller runs a program and may be programmed.

The power management integrated circuit 410 also includes an I2C interface, serial port, and one or more GPIO pins (INT0, INT1, Reset) coupled to, for example, the control component 104. The control component 104 configures the power management integrated circuit 410 through, for example, an I2C interface. The controller of the power management integrated circuit acquires configuration information supplied from the control section 104 from the I2C interface, and sets output power specifications (voltage value and/or current value, etc.) of each power supply channel, and controls on/off of each power supply channel and timing thereof. The power management integrated circuit 410 also provides a reset signal and one or more interrupt signals to the control component 104 via the GPIO interface to indicate the status of the power supply to the control component 104. For example, the power management integrated circuit 104 provides an active signal to the control unit 104 through the Reset pin after a specified condition is satisfied (e.g., power is stable for a specified time, and power is provided to the components of the memory device through the power supply channels for a specified time) after power is obtained from the interface 103 to instruct the control unit 104 to Reset. Alternatively, the power management integrated circuit 104, upon recognizing an interruption in the supply of power from the interface 103, provides a specified signal to the control unit 104 via the INT0/INT1 pin to indicate to the control unit 104 the occurrence of a power supply event after a specified condition is met (e.g., a specified time of power interruption, or the output voltage of the backup power supply drops below a specified level).

Optionally, the power management integrated circuit 410 further includes one or more digital-to-analog converters/analog-to-digital converters, and the controller collects or monitors external signals through the analog-to-digital converters/analog-to-digital converters, for example, collects voltage/current values on the Vin pin to calculate power, or collects ambient temperature, etc.

FIG. 5 illustrates a schematic diagram of a memory device according to yet another embodiment of the present application. The power management integrated circuit 410 according to the embodiment of fig. 5 also identifies whether the control component 104 supports AVS (Adaptive voltage scaling) to adjust the power supplied to the control component 104.

Referring to fig. 5, the power channel CH1 of the power management integrated circuit 410 is used to provide power (VDD) for its core circuitry to the control component 104. Optionally, the pin CH1 SW of the power supply channel CH1 is coupled to the inductor 510, and the other end of the inductor 510 is coupled as an output terminal of the power supply channel CH1 to a power input terminal of the control unit. Inductor 510 is used to protect supply channel pin CH1 SW from excessive varying currents appearing thereon. The output terminal (denoted as Vout) of the supply channel CH1 is also coupled to ground through a resistor 520 and a resistor 522 in series. The point at which the series connected resistor 520 and resistor 522 are connected to each other is coupled to pin CH1 FB of the supply channel CH1 to provide voltage feedback to the supply channel CH 1. The point at which the series resistance 520 and 522 are connected to each other is also coupled to ground through the series resistance 524 and the switch 530. When the switch 530 is closed, the resistor 524 is connected in parallel with the resistor 522, and the resistor 524 is connected in parallel with the resistor 522 and then connected in series with the resistor 520. When switch 530 is open, resistor 524 is disconnected from the circuit and only circuit 522 and resistor 520 are connected into circuit. AVS-enabled control component 104 provides an AVE _ EN signal that is coupled to a control terminal of switch 530 such that when the AVS _ EN signal is active, switch 530 is closed, and when the AVS _ EN signal is inactive or absent, switch 530 is open. Resistor 520, resistor 522, resistor 524, and switch 530 form a voltage feedback circuit for providing a voltage feedback signal to power management integrated circuit 410.

The control component 104 that supports the AVS functionality may accept a lower supply voltage and thus reduce power consumption than a control component that does not support the AVS functionality. As an example, if the control portion 104 supports the AVS function, after receiving the RESET signal (RESET), the control portion 104 outputs the AVS _ EN signal at a low level first and then outputs the AVS _ EN signal at a high level. In response to the AVS _ EN signal being low, the switch 530 is turned off, the point at which the series resistor 520 and the resistor 522 are connected to each other has a voltage value V1 and is provided as a feedback signal to the pin CH1 FB, and the power management integrated circuit 410 stabilizes the output voltage of the pin CH1 SW at Vo1 according to the feedback voltage value V1 of the pin CH1 FB. In response to the AVS _ EN signal being high, the switch 530 is closed, and the point at which the series resistor 520 and the resistor 522 are connected to each other has a voltage value V2, and the voltage value V2 has a tendency to fall with respect to the voltage value V1. The power management integrated circuit 410 is provided to the pin CH1 FB as a feedback signal to stabilize the output voltage of the pin CH1 SW at Vo2 according to the feedback voltage value V2 of the pin CH1 FB, wherein the output voltage Vo2 is smaller than the output voltage Vo 1. If the control component 104 coupled to the power management integrated circuit 410 does not support the AVS function, the AVS _ EN signal provided to the switch 530 remains low at all times and keeps the switch 530 turned off, and the output voltage of the pin CH1 SW settles to Vo1 and does not change to Vo 1. Therefore, the circuit according to the embodiment of fig. 5 can be used for the control component 104 supporting the AVS function and the control component 104 not supporting the AVS function, so that the memory device does not need to adopt different circuit designs according to whether the control component 104 supports the AVS function in the manufacturing process, and the design and production cost is saved.

In still another example, the control section 104 outputs an AVS _ EN signal of high level (instead of a change signal of low level first and then high level) when the AVS function is supported, and outputs an AVS _ EN signal of low level when the AV function is not supported. Such a control unit 104 is also suitable for the circuit illustrated in fig. 5.

In yet another example, the AVS _ EN signal output by control component 104 is independent of the Reset signal (Reset). Such a control unit 104 is also suitable for the circuit illustrated in fig. 5.

In yet another embodiment according to the present application, the AVS _ EN signal provided by control component 104 is coupled to one of the GIPO pins of power management integrated circuit 410. The controller of the power management integrated circuit 410 collects the level of the GPIO pin coupled to the AVS _ EN signal to identify whether the control component 104 supports the AVS function and outputs a relatively high voltage on the power channel CH1 when the control component 104 does not support the AVS function and a relatively low voltage on the power channel CH1 when the control component 104 supports the AVS function.

FIG. 6A illustrates a power-up sequence provided by a power management integrated circuit according to an embodiment of the present application.

In response to power-up (the power input pin Vin of the power management integrated circuit 410 receives power), the power supply channels of the power management integrated circuit 410 provide power out in time sequence, and the GPIO pin provides a designated signal out in time sequence, according to the power-up sequence shown in fig. 6A. Referring to fig. 6A, at time 1, the power input pin Vin1 receives power of 12V, while the power management integrated circuit 104 sets the pin INT0(GPIO) to a designated level (high level in fig. 6A) to indicate to the control section 104 that the power supply is normal (although the control section 104 has not yet been activated at this time, such setting avoids following activation of the control section 104 to consider the power supply to be in an abnormal state), and the power management integrated circuit 410 also sets the pin reset (GPIO) to a designated level (low level in fig. 6A) to indicate to the control section 104 a reset signal. Optionally, at a subsequent time 2, the power input pin Vin2 receives 5V of power. Next, the power management integrated circuit 410 turns on the power supply of each power supply channel according to the preferred timing. At the subsequent time 3, the power supply channel for charging the backup power supply is first turned on (see fig. 5, CH 7). Charging the standby power supply consumes a relatively large amount of power, and the power supply channel CH7 is independently turned on, thereby avoiding adverse effects on the host to which the storage device is coupled due to excessive power changes in a short time. Then, power supply to the core circuit of the control section 104 is turned on at time 4 (the power supply channel CH1 is turned on). The control section 104 needs a certain time to perform its own initialization, and power is supplied to the control section 104 early to shorten the startup time of the storage device. Next at time 5, power to the GPIO pin of the control component 104 is turned on. So that the control unit 104 can operate some peripheral components. Next, at time 6, the memory cell arrays of the DRAM110 and the NVM chip 105 are powered (CH5 and CH6), and at subsequent time 7, the IO interfaces of the DRAM110 and the NVM lower chip 105 are powered (CH2 and CH4), and the IO interface of the control unit 104 coupled to the NVM chip 105/DRAM 110 is powered (CH2 and CH4), so that the DRAM110 and the NVM chip 105 can operate, and the control unit 104 can access the DRAM110 and the NVM chip 105. At a subsequent time 8, power management integrated circuit 410 provides an overridden reset signal to control component 104, causing control component 104 to begin loading, for example, firmware stored in NVM chip 105. At this point, power management integrated circuit 410 has begun to supply power to all major components of the memory device, each of which may be operating properly.

Optionally, power management integrated circuit 410 employs different power-up sequences to power the components of the memory device to ensure that the power requirements are smooth during power-up and that sufficient power is already provided when the components are started up or need to be used.

FIG. 6B illustrates a power down sequence provided by a power management integrated circuit according to an embodiment of the present application. Fig. 6 also illustrates a power down sequence provided by the power management integrated circuit 410. When the storage device is powered down, a series of operations need to be performed to shut down various portions of the storage device and to save necessary information.

Referring to fig. 6B, at time 1, the host to which the storage device is coupled stops providing 12V of power to the power input pin Vin 1. For example, the power management integrated circuit 104 identifies whether 12V power provided by the host is stored according to the voltage level of the power input pin Vin 1. In response to identifying that the host stops providing 12V power, the power management integrated circuit 104 indicates a host power supply exception signal to the control component 104 through an INT0(GPIO) pin. The power management integrated circuit 104 then maintains power to the various primary components of the memory device for a period of time to wait for the control components to save the necessary information and prepare for a power loss. For example, the power supply is maintained by the backup power supply of the storage device for this period of time. Optionally, the power supply is maintained for this period of time using a 5V power supply provided by the host.

Then at time 2, the power management integrated circuit 410 cuts off the power path (CH7) for charging the backup power supply to avoid sinking the remaining power that the power management circuit 410 may provide due to the power down of the backup power supply.

Then at time 3, the power management integrated circuit 410 cuts off the power supply channel (CH3) supplying power to the GPIO pin of the control component 104, so far, the control component 104 can no longer use the GPIO.

Subsequently, at time 4, the power supply channels (CH4 and CH6) for supplying power to the memory cell array and the IO interface of the NVM chip 105 are cut off, and thus the control unit 104 can no longer access the NVM chip 105.

Subsequently, at time 5, the power supply path (CH2 and CH5) for supplying power to the memory cell array and the IO interface of the DRAM is cut off, and the power supply path (CH1) for supplying power to the core circuit of the control section 104 is cut off, so far, both the control section 104 and the DRAM110 do not operate.

Then at time 6, the 5V power supplied by the host disappears and the power management integrated circuit 410 no longer guarantees that the reset signal supplied by the GPIO pin is invalid.

Through the power down sequence illustrated in fig. 6B, the storage device gradually cuts off one or more power supply channels during power down, reducing power consumption, and the remaining power is used to ensure that the control unit 104 performs the necessary operations required to complete the power down.

FIG. 7 illustrates a schematic diagram of a memory device according to another embodiment of the present application. According to the embodiment of fig. 7, the memory device is provided with the capability to debug the power management integrated circuit 410. Since the power management integrated circuit 410 includes a controller and a program running in the controller, it needs to be effectively debugged during the program process, and also needs to debug the cooperation of the power management integrated circuit 410 and the control unit 104 during the operation of the storage device to ensure that the components operate normally.

Referring to fig. 7, the storage device also includes a debug interface 710. By way of example, the debug interface 710 includes one or more pins for debugging. In one example, the debug interface 710 is integrated into the interface 103 to connect the debug pins through the interface 103 to the memory device. In the example shown in fig. 7, the debug interface 710 is independent of the interface 103. The memory device is debugged by additionally connecting a debugging device to the debugging interface 710. And because the debugging equipment is outside the storage equipment and does not belong to a part of the storage equipment, the manufacturing cost of the storage equipment is also reduced. The debugging device comprises for example a Microcontroller (MCU).

The power management integrated circuit 410 provides the I2C interface to the control component 104, and one or more GPIO pins (INT0, INT1, and Reset) are coupled to the debug interface 710. When the debug interface 710 of the memory device is not connected to the debug device, the I2C and one or more GPIO pins (INT0, INT1, and Reset) of the power management integrated circuit 410 only sense the presence of the control unit 104 and communicate with the control unit 104, so that the memory device not connected to the debug device operates normally. When the debugging interface 710 of the memory device is connected to the debugging device, the debugging device provides information to the I2C interface of the power management integrated circuit 410 through the debugging interface 710, and the debugging device obtains the input of one or more GPIO pins (INT0, INT1 and Reset), thereby realizing debugging of the power management integrated circuit 410 and the memory device.

With continued reference to FIG. 7, the I2C interface of the control component 104 is coupled to the I2C interface of the power management integrated circuit 410 through the switch 720. Under normal conditions, switch 720 is turned on so that control unit 104 can provide information to power management integrated circuit 410 via the I2C interface. The control terminal of the switch is also coupled to the Debug interface 710, where the Debug device is coupled to the control terminal of the switch 720 through the Debug interface, such that the Debug device opens the switch 720 through, for example, a GPIO pin (Debug _ EN), and the I2C interface of the Debug device is coupled to the I2C interface of the power management integrated circuit 410 through the Debug interface 720, such that the Debug device can exchange information to the power management integrated circuit 410 through the I2C interface. The GPIO pins of the debug device are also coupled to the GPIOs (INT0, INT1, and Reset) of the power management integrated circuit 410 through the debug interface 720, respectively, to enable the debug device to capture the values of the critical signals (INT0, INT1, and Reset) generated by the power management integrated circuit 41 and the times at which these times are generated.

Optionally, the Debug device closes switch 720 through, for example, a GPIO pin (Debug _ EN), thereby allowing information to be provided by control component 104 to power management integrated circuit 410 through the I2C interface during Debug. The debug device also obtains information that the control component 104 provides over the I2C interface to identify whether the behavior of the control component 104 is as expected and whether the behavior of the power management integrated circuit 410 is as expected.

Optionally, one or more GPIO pins (AVS _ EN, GPIO, etc.) of control component 104 are also coupled to debug interface 710. The debug device couples these GPIO pins of the control component 104 through the debug interface 710 to exchange information with the control component 104. For example, the debug device obtains the AVS _ EN signal output by the control component 104 through the debug interface 710 and obtains the voltage output by the power channel CH1 through the I2C interface of the power management integrated circuit 410 to identify whether the power management integrated circuit 410 correctly responds to the AVS signal provided by the control component 104.

Still optionally, the debugging device further obtains, through the debugging interface 710, a time when the input pin Vin of the power management integrated circuit 410 receives power provided by the host, and obtains signals that the power management integrated circuit 410 subsequently outputs through the GPIO pins (INT0, INT1, and Reset), and a timing and a voltage value when each power supply channel provides power to each component of the storage device, so as to identify whether the operation of the power management integrated circuit 410 is expected.

Optionally, the debugging device further comprises other interfaces such as UART interfaces, JTAG interfaces, etc. coupled to the control component 104 through the debugging interface 710 to communicate with the control component 104, e.g. to obtain information output by the control component 104 on these interfaces and/or to provide debugging commands to the control component 104 through these interfaces.

The debug apparatus is particularly useful in debugging power-up and power-down sequences of the power management integrated circuit 104. For debugging convenience, the power management ic 410 collects the voltage/current values of its power input pins and the power output pins of the power supply channels, and for example, the time when the power input interface is supplied with stable power and the time when each power supply is powered on to stably output power, and stores them in its own register. The debug device obtains the values of the registers of the power management integrated circuit 410 through the I2C interface or other interfaces such as UART/JTAG to know the behavior of the power management integrated circuit 410 during power up and power down. For example, the debug device knows the time when the power input pin of the power management integrated circuit 410 is supplied with 12V voltage, and then generates power output on each power supply channel and the voltage value of the output, and the signal and timing output by the GPIO pins (INT0, INT1, and Reset) through the debug interface, thereby determining whether the power-on process is expected. The debug device also knows the time of the 12V voltage message at the power input pin of the power management integrated circuit 410 through the debug interface, and then the time of the power output message on each power supply channel, and the signals and timing output by the GPIO pins (INT0, INT1, and Reset), to determine whether the power down process is expected.

In an alternative embodiment, the debug device is also connected to the interface 103 and provides power, e.g. 12V, to the power management integrated circuit 410 via the interface 103 in order to debug the power-up and or power-down procedure. The commissioning device is thus able to control and monitor the entire power up/down procedure. The debug device also selects the preferred configuration to provide to the power management integrated circuit 410 through an iterative power up/down process. For example, the debug device sets the specification and timing of the output voltage of each power supply channel for the power management integrated circuit through the I2C interface, provides 12V power to the power management integrated circuit 410 through the interface 103, and monitors whether the outputs of each power supply channel and GPIO pin of the power management integrated circuit 410 meet the expectations. In the event that the expectation is not met, the debug component changes the configuration of the power management integrated circuit 410 via the I2C interface and again provides 12V of power to the power management integrated circuit 410 via the interface 103 and monitors whether the behavior of the power management integrated circuit 410 providing 12V of power via the interface 103 meets the expectation. Debugging of the power management integrated circuit 410 is accomplished in this manner and the debugging time is reduced.

As another example, the debug device actively cuts off the 12V power supplied to the power management ic 410 through the interface 103, and observes, through the debug interface, whether the power management ic 410 generates signals INT0, INT1, etc. that meet expectations at the right timing through the GPIO pin, and whether the standby power and the output voltage of each power supply channel remain valid for a specified time after the power supply to the power input pin Vin of the power management ic 410 is cut off. In the event that the output of the power management integrated circuit 410 does not meet expectations, the debug component changes the configuration of the power management integrated circuit 410 through the I2C interface and again provides 12V of power to the power management integrated circuit 410 through the interface 103 and cuts off 12V of power and monitors whether the behavior of the power management integrated circuit 410 through the interface 103 meets expectations.

FIG. 8 illustrates a schematic diagram of a memory device according to yet another embodiment of the present application. According to the embodiment of 8, the memory device is provided with the capability to debug the power management integrated circuit 410.

In contrast to the embodiment shown in fig. 7, in the embodiment according to fig. 8 the storage device comprises a commissioning device. The debug device couples the I2C interface and one or more GPIO pins (INT0, INT1, and Reset) of the power management integrated circuit 410. When the memory device works, the debugging device acquires the states of each power input pin, each power supply channel and each GPIO of the power management integrated circuit 410 at any time to identify whether the behavior of the power management integrated circuit 410 meets expectations.

According to the embodiment of fig. 8, optionally also a debug interface independent of interface 103 is included. The UART interface or JTAG interface of the debugging device is coupled to the debugging interface, so that when the memory device is connected to an external computer or a debugging computer through the debugging interface, the debugging device is accessed through the debugging interface, and thus, the respective operating states of the power management integrated circuit 410 and the control part 104 are obtained through the debugging device. The debugging computer also changes the behavior of the debugging device through the debugging interface.

With continued reference to fig. 8, optionally, the interface 103 also includes pins coupled to the UART interface/JTAG interface of the control component 104, and the debugging computer is coupled to the UART/JATG interface of the control component 104 through the interface 103 in addition to connecting the UART/JTAG interface of the debugging device through the debugging interface. The debugging computer thus communicates with the control unit 104 via the interface 103 and with the debugging device via the debugging interface to debug the control unit 104 and the power management integrated circuit 410 simultaneously.

FIG. 9 illustrates a schematic diagram of a memory device according to yet another embodiment of the present application. The storage device provides an SMBUS interface through which the host accesses the storage device outside of the storage interface, e.g., by retrieving configuration information for the storage device. Part of the pins of the interface 103 of the memory device are used to provide the SMBUS interface. According to the embodiment shown in fig. 9, the storage device comprises an EEPROM (electrically erasable and programmable memory). The EERPOM, control component 104, and/or power management integrated circuit 410 are coupled to the SMBUS. The host reads information from the EEPROM, control component 104, and/or power management integrated circuit 410 by accessing the SMBUS.

In one example, EEPROM stores configuration information for the memory device. The host reads configuration information from the EEPROM through the SMBUS. And optionally, for some dynamic information, for example, temperature information of the storage device, the control unit or the power management integrated circuit 410 writes the dynamic information into the EEPROM so that the host can read the dynamic information from the EERPOM through the SMBUS.

In yet another example, the host reads configuration information from EEPROM through the SMBUS, and dynamic information from the control component and/or power management integrated circuit 410 through the SMBUS.

In yet another example, control component 104 is coupled to the SMBUS of interface 103, while power management integrated circuit 410 is not coupled to the SMBUS of interface 103. The control unit 104 acquires dynamic information such as temperature, capacitance health status and the like collected by the power management integrated circuit 410 through the I2C interface, and responds to the access of the host through the SMBUS. And optionally the host also accesses EERPOM through SMBUS of interface 103.

In yet another example, power management integrated circuit 410 is coupled to the SMBUS of interface 103, while control component 104 is not coupled to the SMBUS of interface 103. The control section 104 supplies information such as temperature grasped by it to the power management integrated circuit 410 through the I2C interface, and the host accesses the power management integrated circuit 410 through the SMBUS to obtain this dynamic information. And optionally the host also accesses EERPOM through the SMBUS of interface 103 to obtain other configuration information.

Although the present invention has been described with reference to examples, which are intended to be illustrative only and not to be limiting of the application, changes, additions and/or deletions may be made to the embodiments without departing from the scope of the application.

Many modifications and other embodiments of the application set forth herein will come to mind to one skilled in the art to which these embodiments pertain having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is to be understood that the application is not to be limited to the specific embodiments disclosed and that modifications and other embodiments are intended to be included within the scope of the appended claims. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.

Claims

1. A storage device, comprising: the device comprises a control component, an NVM chip, an interface and a power management component;

the power management component obtains a first power input from the interface and provides power to the control component through a first power channel, an

Power is provided to the NVM chip through a second power supply channel.

2. The memory device of claim 1, further comprising a voltage feedback circuit; the voltage feedback circuit receives the self-adaptive voltage adjusting signal provided by the control part and provides a voltage feedback signal for the first power supply channel;

the power management component adjusts the voltage of the power provided by the first power supply channel according to the voltage feedback signal received by the first power supply channel.

3. The storage device of claim 2, wherein

The power management component reduces a voltage of the power provided to the control component through the first power supply channel when the adaptive voltage adjustment signal indicates that the control component supports the adaptive voltage adjustment function; and

the power management component does not reduce the voltage of the power provided to the control component over the first power supply channel when the adaptive voltage adjustment signal indicates that the control component does not support the adaptive voltage adjustment function.

4. Storage device according to one of claims 1 to 3, wherein

And the power management part provides power for the IO interface of the NVM chip and the IO interface of the control part through a third channel.

5. The storage device of any of claims 1-4, further comprising a backup power source;

the power management component provides power for charging to the backup power source through a sixth power supply channel.

6. The storage device of one of claims 1 to 5, wherein

The power management component provides an active reset signal to the control component in response to the interface of the memory device providing a first power input, and subsequently provides an inactive reset signal to the control component after sequentially providing power to the control component and the NVM chip.

7. The storage device of one of claims 1 to 6,

the power management component further provides a reset signal and one or more interrupt signals to the control component;

the first communication interface of the power management component is also coupled to the communication interface of the control component.

8. The storage device of claim 7, further comprising a debug interface connector;

the reset signal and one or more interrupt signals provided by the power management component to the control component are also connected to the debug interface connector; the first communication interface of the power management component is also coupled to the debug interface connector.

9. The storage device of claim 7 or 8, wherein

The communication interface of the power management component is coupled to the communication interface of the control component through a switch;

a control terminal of the switch is coupled to the debug interface connector;

when the debugging interface connector of the storage device is coupled with a debugging device, the debugging device is coupled to the control end of the switch through the debugging interface connector so as to disconnect the coupling of the communication interface of the power management component to the communication interface of the control component.

10. The storage device of claim 7, further comprising a debug device;

the reset signal and one or more interrupt signals provided by the power management component to the control component are also connected to the debug device; the communication interface of the power management component is also coupled to the debugging device.