CN110632999A - Power Management Device for Storage Devices - Google Patents

Abstract

A power management apparatus for a storage device is provided. The disclosed storage device includes: the device comprises a control component, an NVM chip, an interface and a power management component; the power management component obtains a first power input from the interface and provides power to the control component over a first power channel and provides power to the NVM chip over a second power channel.

Description

Power Management Device for Storage Devices

technical field

The present application relates to a storage device, and more specifically, to a power management device for a storage device.

Background technique

Figure 1 shows a block diagram of a solid-state storage device. The solid-state storage device 102 is coupled with the host, and is used to provide storage capacity for the host. The host and the solid-state storage device 102 can be coupled in various ways, including but not limited to SATA (Serial Advanced Technology Attachment, serial advanced technology attachment), SCSI (Small Computer System Interface, small computer system interface) , SAS (Serial Attached SCSI, serial connection SCSI), IDE (Integrated Drive Electronics, integrated drive electronics), USB (Universal Serial Bus, universal serial bus), PCIE (Peripheral Component Interconnect Express, PCIe, high-speed peripheral component interconnection), NVMe (NVM Express, high-speed non-volatile storage), Ethernet, Fiber Channel, wireless communication network, etc. to connect the host and the solid-state storage device 102 . A host may be an information processing device capable of communicating with a storage device in the above manner, for example, a personal computer, a tablet computer, a server, a portable computer, a network switch, a router, a cellular phone, a personal digital assistant, and the like. The storage device 102 includes an interface 103 , a control unit 104 , one or more NVM chips 105 , and a DRAM (Dynamic Random Access Memory, dynamic random access memory) 110 .

NAND flash memory, phase change memory, FeRAM (Ferroelectric RAM, ferroelectric memory), MRAM (Magnetic Random Access Memory, magnetoresistive memory), RRAM (Resistive Random Access Memory, resistive variable memory), etc. are common NVM.

The interface 103 can be adapted to exchange data with the host through methods such as SATA, IDE, USB, PCIE, NVMe, SAS, Ethernet, Fiber Channel, and the like.

The control unit 104 is used to control the data transmission between the interface 103, the NVM chip 105 and the DRAM 110, and is also used for storage management, host logic address to flash memory physical address mapping, erasure equalization, bad block management, etc. The control unit 104 can be implemented in multiple ways of software, hardware, firmware or combinations thereof. For example, the control unit 104 can be an FPGA (Field-programmable gate array, field programmable gate array), an ASIC (Application Specific Integrated Circuit, application-specific integration circuit) or a combination thereof. The control unit 104 may also include a processor or a controller, and software is executed in the processor or the controller to manipulate the hardware of the control unit 104 to process IO (Input/Output) commands. Control component 104 may also be coupled to DRAM 110 and may access data of DRAM 110 . Data of FTL tables and/or cached IO commands can be stored in DRAM.

The control unit 104 includes a flash memory interface controller (or called a media interface controller, a flash memory channel controller), and the flash memory interface controller is coupled to the NVM chip 105, and sends commands to the NVM chip 105 in a manner that follows the interface protocol of the NVM chip 105 , to operate the NVM chip 105 and receive command execution results output from the NVM chip 105 . Known NVM chip interface protocols include "Toggle", "ONFI" and the like.

The storage device also includes a power management device, configured to provide power for various components of the storage device. In Chinese patent applications 201210258780.0 and 201510347811.3, a power supply circuit of a storage device is shown as an example of a power management device. Figure 2 shows a power management device as an integrated circuit. The Vin pin of the power management integrated circuit shown in Figure 2 receives external power supply, and provides power such as 3.3V through the SW pin, and receives the feedback signal of the power supply voltage through the FB pin to adaptively adjust the output of the SW pin The voltage stabilizes the output voltage at a specified value (for example, 3.3V), and the PG signal of the power management integrated circuit shown in Figure 2 indicates whether the current power supply is normal.

Figure 3 shows another power management IC. The Vin pin of the power integrated circuit shown in FIG. 3 receives external power supply, including multiple power supply outputs (Vout1 and Vout2). Taking one power supply output Vout1 as an example, the LX1 pin of the power management integrated circuit provides power, and receives the feedback signal of the supply voltage provided by the LX1 pin through the FB1 pin, so as to adaptively adjust the output voltage of the LX1 pin. The power management integrated circuit shown in Figure 3 also includes a controller (not shown), which can be programmed to execute various programs to control GPIO pins (general-purpose input and output pins), and to control the power-on of various power outputs /cut and its timing. The power management integrated circuit shown in Figure 3 also includes one or more digital-to-analog converters/analog-to-digital converters, and the controller collects or monitors external signals through the analog-to-digital converters/digital-to-analog converters, for example, to collect the Voltage/current values to calculate power, or collect ambient temperature, etc. The controller also communicates with external devices through serial ports (UART), I2C and other interfaces.

Contents of the invention

The power management device needs to continue to develop along with the improvement of the storage device, so as to provide more reliable power supply, higher power efficiency and richer functions.

According to the first aspect of the present application, there is provided the first storage device according to the first aspect of the present application, including: a control component, an NVM chip, an interface, and a power management component; the power management component obtains the first power input from the interface, and passes through the first A power supply channel provides power to the control unit, and provides power to the NVM chip through the second power supply channel; the storage device also includes a voltage feedback circuit; the voltage feedback circuit receives the adaptive voltage adjustment signal provided by the control unit, and supplies power to the first The channel provides a voltage feedback signal; the power management component adjusts the voltage of the power provided by the first power supply channel according to the voltage feedback signal received by the first power supply channel.

According to the first storage device according to the first aspect of the present application, there is provided the second storage device according to the first aspect of the present application, wherein when the adaptive voltage adjustment signal indicates that the control unit supports the adaptive voltage adjustment function, the power management unit reducing the voltage of the power supplied to the control component through the first power supply channel; and when the adaptive voltage regulation signal indicates that the control component does not support the adaptive voltage regulation function, the power management component does not reduce the voltage of the power supplied to the control component through the first power supply channel The voltage of the power supplied.

According to the first or second storage device according to the first aspect of the present application, the third storage device according to the first aspect of the present application is provided, wherein the power management component communicates with the IO interface of the NVM chip through a third channel and the The IO interface of the control unit provides power.

According to one of the first to third storage devices according to the first aspect of the present application, the fourth storage device according to the first aspect of the present application is provided, further comprising a DRAM component; the power management component supplies the DRAM component with a fourth power supply channel Provide electricity.

According to the fourth storage device according to the first aspect of the present application, the fifth storage device according to the first aspect of the present application is provided, wherein the power management component communicates with the control component through the fifth power supply channel to the IO interface of the DRAM component The IO interfaces coupled to the DRAM components provide power.

According to one of the first to fifth storage devices according to the first aspect of the present application, the sixth storage device according to the first aspect of the present application is provided, further comprising a backup power supply; The power supply provides power for charging.

According to one of the first to sixth storage devices according to the first aspect of the present application, there is provided the seventh storage device according to the first aspect of the present application, further comprising a voltage conversion circuit that converts the first power input into the second Two power outputs, the power management component obtains the first power input and the second power output.

According to one of the first to sixth storage devices according to the first aspect of the present application, there is provided the eighth storage device according to the first aspect of the present application, wherein the power management part also obtains the second power input from the interface.

According to one of the first to eighth storage devices according to the first aspect of the present application, there is provided the ninth storage device according to the first aspect of the present application, wherein when the adaptive voltage adjustment signal indicates that the control unit supports the adaptive voltage adjustment function, The voltage feedback circuit outputs a first voltage feedback signal to the power management unit; when the adaptive voltage adjustment signal indicates that the control unit does not support the adaptive voltage adjustment function, the voltage feedback circuit outputs a second voltage feedback signal to the power management unit; and Wherein the voltage of the first voltage feedback signal is lower than that of the second voltage feedback signal.

The ninth storage device according to the first aspect of the present application provides the tenth storage device according to the first aspect of the present application, wherein the voltage feedback circuit includes a first resistor and a second resistor connected in series, and the first resistor and the second resistor connected in series The output voltage of the first power supply channel is applied; the connection point of the first resistor in series and the second resistor provides a voltage feedback signal to the power management component, and also provides voltage to the switch in series and the third resistor.

According to the tenth storage device according to the first aspect of the present application, there is provided the eleventh storage device according to the first aspect of the present application, wherein the switch and the third resistor connected in series are connected in parallel with the second resistor.

According to one of the first to eleventh storage devices according to the first aspect of the present application, there is provided a twelfth storage device according to the first aspect of the present application, wherein the power management component provides a first power input in response to an interface of the storage device, Firstly, a valid reset signal is provided to the control unit, and after power is supplied to the control unit and the NVM chip in sequence, then an invalid reset signal is provided to the control unit.

According to the twelfth storage device according to the first aspect of the present application, there is provided the thirteenth storage device according to the first aspect of the present application, wherein the power management component also supplies power to the backup power supply before supplying power to the control component.

According to one of the first to thirteenth storage devices according to the first aspect of the present application, there is provided the fourteenth storage device according to the first aspect of the present application, wherein the power management part disappears in response to the first power input provided by the interface of the storage device , to provide a valid interrupt signal to the control unit.

According to the second aspect of the present application, there is provided the first storage device according to the second aspect of the present application, including: a control component, an NVM chip, an interface, and a power management component; the power management component obtains the first power input from the storage interface, and passes The first power supply channel provides power to the control unit, and provides power to the NVM chip through the second power supply channel; the power management unit also provides a reset signal and one or more interrupt signals to the control unit; the power management unit’s The first communication interface is also coupled to the communication interface of the control component.

According to the first storage device according to the second aspect of the present application, there is provided the second storage device according to the second aspect of the present application, further comprising a debugging interface connector; a reset signal provided by the power management component to the control component and one or A plurality of interrupt signals is also connected to the debug interface connector; the first communication interface of the power management component is also coupled to the debug interface connector.

According to the second storage device according to the second aspect of the present application, the third storage device according to the second aspect of the present application is provided, wherein after the debugging interface connector of the storage device is coupled to the debugging device, the debugging device obtains the power The reset signal and one or more interrupt signals provided by the management component, and the communication interface of the debugging device are also coupled to the communication interface of the power management component.

According to the second or third storage device according to the second aspect of the present application, there is provided the fourth storage device according to the second aspect of the present application, wherein

The communication interface of the power management component is coupled to the communication interface of the control component through a switch; the control terminal of the switch is coupled to the debugging interface connector; when the debugging interface connector of the storage device is coupled to the debugging device, The debug device is coupled to the control terminal of the switch through the debug interface connector to decouple the communication interface of the power management component from the communication interface of the control component.

According to one of the first to fourth storage devices according to the second aspect of the present application, there is provided the fifth storage device according to the second aspect of the present application, wherein the adaptive voltage adjustment signal provided by the control part is coupled to the debugging interface connection device.

According to the fifth storage device according to the second aspect of the present application, the sixth storage device according to the second aspect of the present application is provided, wherein after the debugging interface connector of the storage device is coupled to the debugging device, the debugging device obtains the control The adaptive voltage regulation signal provided by the part.

According to one of the first to sixth storage devices according to the second aspect of the present application, there is provided the seventh storage device according to the second aspect of the present application, wherein the second communication interface of the control component is coupled to the debugging interface connector; After the debugging interface connector of the storage device is coupled to the debugging device, the second communication interface of the debugging device communicates with the second communication interface of the control component.

According to the first storage device according to the second aspect of the present application, there is provided the eighth storage device according to the second aspect of the present application, further including a debugging device; a reset signal provided by the power management component to the control component and one or more An interrupt signal is also connected to the debug device; and the communication interface of the power management component is also coupled to the debug device.

According to the eighth storage device according to the second aspect of the present application, there is provided the ninth storage device according to the second aspect of the present application, wherein the communication interface of the power management component is coupled to the communication interface of the control component through a switch; the switch The control end of the control terminal is coupled to the debugging device; the debugging device controls the switch to disconnect the communication interface of the power management component from the communication interface of the control component.

According to the eighth or ninth storage device according to the second aspect of the present application, there is provided the tenth storage device according to the second aspect of the present application, wherein the adaptive voltage adjustment signal provided by the control unit is coupled to the debugging device.

According to one of the eighth to tenth storage devices according to the second aspect of the present application, the eleventh storage device according to the second aspect of the present application is provided, further comprising a debugging interface connector; the second communication interface of the debugging device is coupled to the debug interface connector; and a second communication interface of the control component coupled to the storage interface.

According to one of the first to eleventh storage devices according to the second aspect of the present application, a twelfth storage device according to the second aspect of the present application is provided, wherein the storage interface further includes pins for SMBUS; The SMBUS pin is coupled to the second communication interface of the power management component; the power management component responds to the SMBUS access request to the storage device through the second communication interface.

According to the twelfth storage device according to the second aspect of the present application, there is provided the thirteenth storage device according to the second aspect of the present application, which further includes a debugging device; wherein the power management component receives from the control component through its first communication interface Acquire first information; the power management component responds to the SMBUS access request to the storage device, and provides the first information through the second communication interface.

According to the twelfth or thirteenth storage device according to the second aspect of the present application, there is provided the fourteenth storage device according to the second aspect of the present application, which also includes a debugging device; also includes a second non-volatile memory; the second non-volatile memory A volatile memory is coupled to the pin for SMB, and the second non-volatile memory also responds to SMBUS access requests to the storage device.

According to the thirteenth or fourteenth storage device according to the second aspect of the present application, there is provided the fifteenth storage device according to the second aspect of the present application, the third communication interface of the control part is coupled to the pin for SMB , the control component also responds to the SMBUS access request to the storage device through the third communication interface.

According to the third aspect of the present application, there is provided the first storage device according to the third aspect of the present application, including: a control component, an NVM chip, an interface, and a power management component; the power management component obtains the first power input from the interface, and passes through the first A power supply channel provides power to the control components, and supplies power to the NVM chip through the second power supply channel.

According to the first storage device according to the third aspect of the present application, there is provided the second storage device according to the third aspect of the present application, further comprising a voltage feedback circuit; the voltage feedback circuit receives the adaptive voltage adjustment signal provided by the control unit, and sends the first The power supply channel provides a voltage feedback signal; the power management component adjusts the voltage of the power provided by the first power supply channel according to the voltage feedback signal received by the first power supply channel.

According to the second storage device according to the third aspect of the present application, there is provided the third storage device according to the third aspect of the present application, wherein when the adaptive voltage adjustment signal indicates that the control unit supports the adaptive voltage adjustment function, the power management unit reducing the voltage of the power supplied to the control component through the first power supply channel; and when the adaptive voltage regulation signal indicates that the control component does not support the adaptive voltage regulation function, the power management component does not reduce the voltage of the power supplied to the control component through the first power supply channel The voltage of the power supplied.

According to one of the first to third storage devices according to the third aspect of the present application, the fourth storage device according to the third aspect of the present application is provided, wherein the power management component communicates with the IO interface of the NVM chip through a third channel The IO interface of the control unit provides power.

According to one of the first to fourth storage devices according to the third aspect of the present application, the fifth storage device according to the third aspect of the present application is provided, further comprising a DRAM component; the power management component supplies the DRAM with the fourth power supply channel Components provide power.

According to the fifth storage device according to the third aspect of the present application, the sixth storage device according to the third aspect of the present application is provided, wherein the power management component communicates with the control component through the fifth power supply channel to the IO interface of the DRAM component The IO interfaces coupled to the DRAM components provide power.

According to one of the first to sixth storage devices according to the third aspect of the present application, there is provided the seventh storage device according to the third aspect of the present application, further comprising a backup power supply; The power supply provides power for charging.

According to one of the first to seventh storage devices according to the third aspect of the present application, there is provided the eighth storage device according to the third aspect of the present application, further comprising a voltage conversion circuit that converts the first power input into the second Two power outputs, the power management component obtains the first power input and the second power output.

According to one of the first to seventh storage devices according to the third aspect of the present application, there is provided the ninth storage device according to the third aspect of the present application, wherein the power management part also obtains the second power input from the interface.

According to the second storage device according to the third aspect of the present application, there is provided the tenth storage device according to the third aspect of the present application, wherein when the adaptive voltage adjustment signal indicates that the control component supports the adaptive voltage adjustment function, the voltage feedback circuit sends The management unit outputs a first voltage feedback signal; when the adaptive voltage adjustment signal indicates that the control unit does not support the adaptive voltage adjustment function, the voltage feedback circuit outputs a second voltage feedback signal to the power management unit; and wherein the first voltage feedback The voltage of the signal is lower than the second voltage feedback signal.

According to the tenth storage device according to the third aspect of the present application, there is provided the eleventh storage device according to the third aspect of the present application, wherein the voltage feedback circuit includes a first resistor and a second resistor connected in series, and the first resistor and the second resistor connected in series The resistor is applied with the output voltage of the first power supply channel; the connection point of the first resistor in series and the second resistor provides a voltage feedback signal to the power management component, and also provides voltage to the switch in series and the third resistor.

According to the eleventh storage device according to the third aspect of the present application, there is provided the twelfth storage device according to the third aspect of the present application, wherein the switch and the third resistor connected in series are connected in parallel with the second resistor.

According to one of the first to twelfth storage devices according to the third aspect of the present application, there is provided the thirteenth storage device according to the third aspect of the present application, wherein the power management component provides the first power input in response to the interface of the storage device, Firstly, a valid reset signal is provided to the control unit, and after power is supplied to the control unit and the NVM chip in sequence, then an invalid reset signal is provided to the control unit.

The thirteenth storage device according to the third aspect of the present application provides the fourteenth storage device according to the third aspect of the present application, wherein the power management component also supplies power to the backup power supply before supplying power to the control component.

According to one of the first to fourteenth storage devices according to the third aspect of the present application, there is provided the fifteenth storage device according to the third aspect of the present application, wherein the power management part disappears in response to the first power input provided by the interface of the storage device , to provide a valid interrupt signal to the control unit.

According to one of the first to fifteenth storage devices according to the third aspect of the present application, there is provided the sixteenth storage device according to the third aspect of the present application, wherein the power management component further provides the control component with a reset signal and a or a plurality of interrupt signals; the first communication interface of the power management component is also coupled to the communication interface of the control component.

According to the sixteenth storage device according to the third aspect of the present application, there is provided the seventeenth storage device according to the third aspect of the present application, further comprising a debugging interface connector; a reset signal provided by the power management component to the control component; and One or more interrupt signals are also connected to the debug interface connector; the first communication interface of the power management component is also coupled to the debug interface connector.

According to the seventeenth storage device according to the third aspect of the present application, the eighteenth storage device according to the third aspect of the present application is provided, wherein after the debugging interface connector of the storage device is coupled to the debugging device, the debugging device obtains the The reset signal and one or more interrupt signals provided by the power management component, and the communication interface of the debugging device are also coupled to the communication interface of the power management component.

According to the seventeenth or eighteenth storage device according to the third aspect of the present application, there is provided the nineteenth storage device according to the third aspect of the present application, wherein the communication interface of the power management component is coupled to the control component through a switch. Communication interface; the control end of the switch is coupled to the debugging interface connector; when the debugging interface connector of the storage device is coupled to the debugging device, the debugging device is coupled to the switch through the debugging interface connector The control terminal is used to disconnect the communication interface of the power management component from the communication interface of the control component.

According to one of the sixteenth to nineteenth storage devices according to the third aspect of the present application, there is provided the twentieth storage device according to the third aspect of the present application, wherein the adaptive voltage adjustment signal provided by the control unit is coupled to the Debug interface connector.

According to the twentieth storage device according to the third aspect of the present application, the twenty-first storage device according to the third aspect of the present application is provided, wherein after the debugging interface connector of the storage device is coupled to the debugging device, the debugging device obtains The adaptive voltage regulation signal provided by the control unit.

According to one of the sixteenth to twenty-first storage devices according to the third aspect of the present application, there is provided the twenty-second storage device according to the third aspect of the present application, wherein the second communication interface of the control unit is coupled to the A debugging interface connector; when the debugging interface connector of the storage device is coupled with a debugging device, the second communication interface of the debugging device communicates with the second communication interface of the control component.

According to the sixteenth storage device according to the third aspect of the present application, there is provided the twenty-third storage device according to the third aspect of the present application, further including a debugging device; a reset signal provided by the power management component to the control component and a or a plurality of interrupt signals, also connected to the debug device; the communication interface of the power management component is also coupled to the debug device.

According to the twenty-third storage device according to the third aspect of the present application, there is provided the twenty-fourth storage device according to the third aspect of the present application, wherein the communication interface of the power management component is coupled to the communication interface of the control component through a switch ; the control end of the switch is coupled to the debugging device; the debugging device controls the switch to disconnect the communication interface of the power management component from the communication interface of the control component.

According to the twenty-third or twenty-fourth storage device according to the third aspect of the present application, there is provided the twenty-fifth storage device according to the third aspect of the present application, wherein the adaptive voltage adjustment signal provided by the control unit is coupled to the Debug equipment.

According to one of the twenty-second to twenty-fifth storage devices according to the third aspect of the present application, there is provided the twenty-sixth storage device according to the third aspect of the present application, which also includes a debugging interface connector; the first debugging device A second communication interface is coupled to the debug interface connector; and a second communication interface of the control component is coupled to the storage interface.

According to one of the first to twenty-sixth storage devices according to the third aspect of the present application, the twenty-seventh storage device according to the third aspect of the present application is provided, wherein the storage interface further includes pins for SMBUS; The pin for SMBUS is coupled to the second communication interface of the power management component; the power management component responds to the SMBUS access request to the storage device through the second communication interface.

According to the twenty-seventh storage device according to the third aspect of the present application, there is provided the twenty-eighth storage device according to the third aspect of the present application, wherein the power management component obtains the first Information: the power management component provides the first information through the second communication interface in response to the SMBUS access request to the storage device.

According to the twenty-seventh or twenty-eighth storage device according to the third aspect of the present application, there is provided the twenty-ninth storage device according to the third aspect of the present application, which also includes a second non-volatile memory; the second non-volatile A memory is coupled to the pin for SMB, and the second non-volatile memory also responds to SMBUS access requests to the memory device.

According to one of the twenty-seventh to twenty-ninth storage devices according to the third aspect of the present application, a third storage device according to the third aspect of the present application is provided, the third communication interface of the control unit is coupled to the user As for the SMB pin, the control component also responds to the SMBUS access request to the storage device through the third communication interface.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments described in this application, and those skilled in the art can also obtain other drawings based on these drawings.

FIG. 1 is a schematic diagram of a solid-state storage device in the prior art provided by the present application;

Figure 2 shows a power management device as an integrated circuit;

Figure 3 shows another power management IC;

FIG. 4 shows a schematic diagram of a storage device according to an embodiment of the present application;

FIG. 5 shows a schematic diagram of a storage device according to another embodiment of the present application;

FIG. 6A shows a power-on sequence provided by a power management integrated circuit according to an embodiment of the present application;

FIG. 6B shows a power-off sequence provided by a power management integrated circuit according to an embodiment of the present application;

FIG. 7 shows a schematic diagram of a storage device according to another embodiment of the present application;

FIG. 8 shows a schematic diagram of a storage device according to yet another embodiment of the present application; and

FIG. 9 shows a schematic diagram of a storage device according to yet another embodiment of the present application.

Detailed ways

The technical solutions in the embodiments of the present application are clearly and completely described below in combination with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of them. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without making creative efforts belong to the scope of protection of this application.

FIG. 4 shows a schematic diagram of a storage device according to an embodiment of the present application. A power management integrated circuit 410 is arranged in the storage device. The power management integrated circuit 10 is used to provide power to various components of the storage device (control component 104, one or more NVM chips 105, one or more DRAMs 110, etc., see also FIG. 1).

The power management integrated circuit 410 includes a plurality of power input pins (Vin1 and Vin2 ), and a plurality of output power supply channels (CH1, CH2, . . . CH6). As an example, the power input pin (Vin2) is coupled to the interface 103 so as to obtain the power provided from the interface 103 for the storage device. In the example of FIG. 3 , the power supplied from the interface 103 is 12V. The power provided from the interface 103 is coupled to the power input pin Vin through the open source 420 . The Vin2_EN pin of the power management integrated circuit 410 is connected to the control terminal of the switch 420 to control the switch 420 to be turned off or on. Optionally, the power provided by the interface 103 can also be used to generate power with other voltage values through the transformer circuit and coupled to the power input pin Vin2. Still optionally, the interface 103 provides two or more channels of power, which are respectively coupled to power input pins of the power management integrated circuit. Still as an example, when the storage device adopts the U.2 standard interface 103, the power management integrated circuit 410 obtains a single 12V power from the interface 103; when the storage device adopts the M.2 standard interface 103, the power management integrated circuit 410 obtains from Interface 103 draws a single 3.3V power supply.

The various components of the storage device (control component 104, NVM chip 105, DRAM 110, etc.) each require one or more power supplies. The NVM chip 105 needs to be supplied with power for the memory cell array (denoted as V1 ), power for the IO interface (denoted as Vp), and optionally additional power (denoted as Vpp). The DRAM 110 needs to be supplied with power for the memory cell array (denoted as V1 ), power for the IO interface (denoted as Vp), and optionally additional power (denoted as Vpp). The control unit 104 needs to be provided with power for the core circuit (denoted as VDD), power for coupling the IO interface of the NVM chip 105, and power for coupling the IO interface of the DRAM 110, and optionally for its GPIO pin power.

Each supply channel of the power management integrated circuit 410 is programmed, for example, to set an output voltage specification, and is coupled to a power supply pin of a respective component. Referring to FIG. 4 , the power supply channel CH1 of the power management integrated circuit 410 is used to provide the control unit 104 with power (VDD) for the core circuit. The power supply channel CH2 is used to provide power to the IO interface of the DRAM 110, and the power supply channel CH2 is also used to provide power to the IO interface of the control unit 104 coupled to the DRAM 110, so that the IO interface of the DRAM 110 and the control unit 104 are coupled to the DRAM The 110's IO interface uses the same specification of power. The power supply channel CH4 is used to provide power to the IO interface of one or more NVM chips 105, and the power supply channel CH4 is also used to provide power to the IO interface of the control unit 104 coupled to the NVM chip 105, so that the IO interface of the NVM chip 105 and The IO interface of the control unit 104 coupled to the NVM chip 105 uses the same specification of power. The power supply channel CH3 is used to provide the control part with power for its GPIO pins. The power supply channel CH5 is used to provide the DRAM 110 with power for core circuits. The power supply channel CH6 is used to provide power for core circuits to the NVM chip 105 . Optionally, the power management integrated circuit 410 further includes an additional power supply channel for providing power for charging, for example, a backup power supply of a storage device. It can be understood that the coupling mode between each power supply channel of the power management circuit 410 and each component of the storage device can be changed, for example, the power supply channel CH1 is used to provide power for the GPIO pin of the control component, and the power supply channel CH2 is used to provide power for its GPIO pin. To provide power (VDD) for the core circuit to the control unit 104 .

The power management integrated circuit 410 also includes a controller (not shown). The controller runs the program and can be programmed.

The power management integrated circuit 410 also includes an I2C interface coupled to, for example, the control component 104, a serial port, and one or more GPIO pins (INT0, INT1, Reset). The control part 104 configures the power management integrated circuit 410 through, for example, an I2C interface. The controller of the power management integrated circuit obtains the configuration information provided by the control part 104 from the I2C interface, and sets the output power specification (voltage value and/or current value, etc.) opportunity. The power management integrated circuit 410 also provides a reset signal and one or more interrupt signals to the control unit 104 through the GPIO interface, so as to indicate the status of the power supply to the control unit 104 . For example, after the power management integrated circuit 104 obtains power from the interface 103, after satisfying the specified conditions (for example, the power is stable for a specified time, and each power supply channel provides power to each component of the storage device for a specified time), the reset pin sends a signal to the control The component 104 provides an active signal to instruct the control component 104 to reset. Optionally, after the power management integrated circuit 104 recognizes that the power supply from the interface 103 is interrupted, after a specified condition is met (for example, the specified time of the power interruption, or the output voltage of the backup power supply drops below a specified level), A designated signal is provided to the control unit 104 through the INT0/INT1 pins to indicate to the control unit 104 the occurrence of the power supply.

Optionally, the power management integrated circuit 410 also includes one or more digital-to-analog converters/analog-to-digital converters, and the controller collects or monitors external signals through the analog-to-digital converters/digital-to-analog converters, for example, to collect to calculate the power, or collect the ambient temperature, etc.

Fig. 5 shows a schematic diagram of a storage device according to yet another embodiment of the present application. The power management integrated circuit 410 according to the embodiment of FIG. 5 also recognizes whether the control unit 104 supports AVS (Adaptive Voltage Scaling) and adjusts the power supplied to the control unit 104 .

Referring to FIG. 5 , the power supply channel CH1 of the power management integrated circuit 410 is used to supply the control unit 104 with power (VDD) for its core circuits. Optionally, the pin CH1 SW of the power supply channel CH1 is coupled to the inductor 510, and the other end of the inductor 510 is coupled to the power input terminal of the control component as the output terminal of the power supply channel CH1. The inductance 510 is used to protect the power supply channel pin CH1 SW from excessive changing currents thereon. The output terminal (denoted as Vout) of the power supply channel CH1 is also coupled to the ground through a resistor 520 and a resistor 522 connected in series. The point where the resistor 520 and the resistor 522 in series are connected to each other is coupled to the pin CH1 FB of the power supply channel CH1 to provide voltage feedback to the power supply channel CH1 . The point at which series resistor 520 and resistor 522 are connected to each other is also coupled to ground through series resistor 524 and switch 530 . When the switch 530 is closed, the resistor 524 and the resistor 522 are connected in parallel, and the resistor 524 and the resistor 522 are connected in parallel and then connected in series with the resistor 520 . When the switch 530 is turned off, the resistor 524 is disconnected from the circuit, and only the circuit 522 and the resistor 520 are connected into the circuit. The control unit 104 supporting AVS provides the AVE_EN signal, and couples the AVE_EN signal to the control terminal of the switch 530, so that when the AVS_EN signal is active, the switch 530 is closed, and when the AVS_EN signal is invalid or absent, the switch 530 is open. The resistor 520 , the resistor 522 , the resistor 524 and the switch 530 form a voltage feedback circuit for providing a voltage feedback signal to the power management integrated circuit 410 .

The control unit 104 that supports the AVS function can accept a lower power supply voltage than the control unit that does not support the AVS function, thereby reducing power consumption. As an example, if the control unit 104 supports the AVS function, after receiving the reset signal (RESET), the control unit 104 first outputs a low-level AVS_EN signal, and then outputs a high-level AVS_EN signal. In response to the low level of the AVS_EN signal, the switch 530 is turned off, and the point where the resistor 520 and the resistor 522 in series are connected to each other has a voltage value V1, which is provided to the pin CH 1 FB as a feedback signal, and the power management integrated circuit 410 according to the pin CH The feedback voltage value of 1 FB is V1, and the output voltage of pin CH 1 SW is stabilized at Vo1. In response to the AVS_EN signal being at a high level, the switch 530 is closed, and the point where the series resistors 520 and 522 are connected to each other has a voltage value V2 , and the voltage value V2 has a downward trend relative to the voltage value V1 . Provided as a feedback signal to the pin CH 1 FB, the power management integrated circuit 410 stabilizes the output voltage of the pin CH 1 SW at Vo2 according to the feedback voltage value V2 of the pin CH 1 FB, wherein the output voltage Vo2 is smaller than the output voltage Vo1 . If the control unit 104 coupled with the power management integrated circuit 410 does not support the AVS function, the AVS_EN signal provided to the switch 530 is always kept at a low level, and the switch 530 is kept turned off, so that the output voltage of the pin CH1 SW is stabilized at Vo1, without changing to Vo1. Thereby, the circuit according to the embodiment of FIG. 5 can be used for both the control unit 104 supporting the AVS function and the control unit 104 not supporting the AVS function, so that the storage device does not need to be based on whether the control unit 104 supports the AVS function in the manufacturing process. And adopting different circuit designs saves design and production costs.

In yet another example, when the control unit 104 supports the AVS function, it outputs a high-level AVS_EN signal (instead of a low-level and then high-level change signal), and when it does not support the AVS function, it outputs a low-level signal the AVS_EN signal. Such a control unit 104 is also suitable for the circuit shown in FIG. 5 .

In yet another example, the AVS_EN signal output by the control component 104 does not depend on the reset signal (Reset). Such a control unit 104 is also suitable for the circuit shown in FIG. 5 .

In yet another embodiment according to the present application, the AVS_EN signal provided by the control unit 104 is coupled to one of the GIPO pins of the power management integrated circuit 410 . The controller of the power management integrated circuit 410 collects the level of the GPIO pin coupled to the AVS_EN signal to identify whether the control unit 104 supports the AVS function, and when the control unit 104 does not support the AVS function, the output on the power supply channel CH1 is relatively high When the control unit 104 supports the AVS function, a relatively low voltage is generated on the power supply channel CH1.

FIG. 6A shows a power-on sequence provided by a power management integrated circuit according to an embodiment of the present application.

In response to power-on (the power input pin Vin of the power management integrated circuit 410 receives power), according to the power-on sequence shown in FIG. Provide the specified signal to the outside in time sequence. Referring to FIG. 6A, at time 1, the power input pin Vin1 receives 12V power, and the power management integrated circuit 104 sets the pin INT0 (GPIO) to a specified level (high level in FIG. 6A ) to control Part 104 indicates that the power supply is normal (although the control part 104 has not started at this time, it is set to avoid thinking that the power supply is in an abnormal state after the subsequent control part 104 starts), and the power management integrated circuit 410 also sets the pin Reset (GPIO) is a specified level (low level in FIG. 6A ) to indicate a reset signal to the control unit 104 . Optionally, at a subsequent time 2, the power input pin Vin2 receives power of 5V. Next, the power management integrated circuit 410 turns on the power supply of each power supply channel according to the preferred timing. At the subsequent time 3, the power supply channel (see FIG. 5, CH7) for charging the backup power supply is firstly opened. Charging the backup power source will consume a large amount of power, and the power supply channel CH 7 is turned on separately to avoid adverse effects of excessive power changes in a short period of time on the host coupled to the storage device. Then at time 4, the power supply to the core circuit of the control part 104 is turned on (the power supply channel CH1 is turned on). The control unit 104 needs a certain period of time to initialize itself, and supplies power to the control unit 104 in advance to shorten the startup time of the storage device. Next at time 5, the power supply to the GPIO pin of the control part 104 is turned on. In order to enable the control unit 104 to operate some peripheral components. Next, at time 6, supply power to the memory cell arrays of DRAM 110 and NVM chip 105 (CH5 and CH6), and at subsequent time 7, supply power to the IO interfaces of DRAM 110 and NVM lower chip 105 (CH 2 and CH 4), And supply power to the IO interface (CH2 and CH4) of the control unit 104 coupled to the NVM chip 105/DRAM 110, so far the DRAM 110 and the NVM chip 105 can work, and the control unit 104 can access the DRAM 110 and the NVM chip 105. At a subsequent time 8 , the power management integrated circuit 410 provides a deactivated reset signal to the control component 104 so that the control component 104 starts loading, for example, firmware stored in the NVM chip 105 . At this point, the power management integrated circuit 410 has started to supply power to all main components of the storage device, and each main component can work normally.

Optionally, the power management integrated circuit 410 adopts different power-on sequences to supply power to various components of the storage device, so as to ensure that the power demand during the power-on process is stable, and sufficient power has been provided when each component starts or needs to be used. electricity.

FIG. 6B shows a power-off sequence provided by a power management integrated circuit according to an embodiment of the present application. FIG. 6 also shows the power-down sequence provided by the power management integrated circuit 410 . When the storage device is powered off, a series of operations need to be performed to shut down various parts of the storage device and save necessary information.

Referring to FIG. 6B , at time 1 , the host coupled to the storage device stops providing 12V power to the power input pin Vin1 . As an example, the power management integrated circuit 104 identifies whether the 12V power provided by the host is stored according to the voltage of the power input pin Vin1. In response to recognizing that the host stops providing 12V power, the power management integrated circuit 104 indicates a host power supply abnormal signal to the control unit 104 through the INT0 (GPIO) pin. Subsequently, the power management integrated circuit 104 keeps supplying power to the main components of the storage device for a period of time, waiting for the control components to save necessary information and prepare for power down. For example, during this time the power supply is maintained by the backup power supply of the storage device. Optionally, the 5V power supply provided by the host computer is used to maintain the power supply during this time.

Then at time 2, the power management integrated circuit 410 cuts off the charging power supply channel (CH7) to the backup power supply, so as to avoid absorbing the remaining power provided by the power management circuit 410 due to the power drop of the backup power supply.

Then at time 3, the power management integrated circuit 410 cuts off the power supply channel (CH3) supplying power to the GPIO pin of the control unit 104, so far, the control unit 104 can no longer use the GPIO.

Then at time 4, cut off the power supply channels (CH4 and CH6) for the memory cell array and the IO interface of the NVM chip 105, so far, the control unit 104 can no longer access the NVM chip 105.

Then at time 5, cut off the power supply channels (CH2 and CH5) that supply power to the memory cell array of DRAM and the IO interface, and cut off the power supply passage (CH1) that supplies power to the core circuit of the control unit 104, so far, the control unit 104 and DRAM110 Neither work anymore.

Then at time 6, the 5V power provided by the host disappears, and the power management integrated circuit 410 no longer ensures that the reset signal provided by the GPIO pin is invalid.

Through the power-off sequence shown in FIG. 6B , during the power-off process, the storage device gradually cuts off one or more power supply channels to reduce power consumption, and uses the remaining power to ensure that the control unit 104 completes necessary operations required for power-off.

Fig. 7 shows a schematic diagram of a storage device according to another embodiment of the present application. According to the embodiment of FIG. 7 , a memory device is provided with the ability to debug the power management integrated circuit 410 . Since the power management integrated circuit 410 includes the controller and the program running in the controller, it needs to be effectively debugged during the program process, and the coordination between the power management integrated circuit 410 and the control unit 104 is also required during the operation of the storage device. Perform commissioning to ensure that components are functioning properly.

Referring to FIG. 7 , the storage device further includes a debug interface 710 . By way of example, debug interface 710 includes one or more pins for debugging. In one example, the debug interface 710 is integrated into the interface 103 and connected to the debug pin through the interface 103 of the storage device. In the example shown in FIG. 7 , debug interface 710 is independent of interface 103 . The memory device is debugged by additionally connecting a debug device to the debug interface 710 . And because the debugging device is outside the storage device and does not belong to a part of the storage device, the manufacturing cost of the storage device is also reduced. Debug devices include, for example, microcontrollers (MCUs).

The power management integrated circuit 410 provides an I2C interface to the control unit 104 , and one or more GPIO pins (INT0, INT1 and Reset) are coupled to the debug interface 710 . When the debug interface 710 of the storage device is not connected to the debug device, the I2C and one or more GPIO pins (INT0, INT1 and Reset) of the power management integrated circuit 410 only sense the existence of the control unit 104, and communicate with the control unit 104 communication so that the storage device without the debug device attached can function normally. And when the debugging interface 710 of the storage device is connected to the debugging device, the debugging device provides information to the I2C interface of the power management integrated circuit 410 through the debugging interface 710, and the debugging device obtains one or more GPIO pins (INT0, INT1 and Reset) input, so as to realize the debugging of the power management integrated circuit 410 and the storage device.

Continuing to refer to FIG. 7 , the I2C interface of the control unit 104 is coupled to the I2C interface of the power management integrated circuit 410 through a switch 720 . Normally, the switch 720 is turned on, so that the control unit 104 can provide information to the power management integrated circuit 410 through the I2C interface. The control end of the switch is also coupled to the debug interface 710, and the debug device is coupled to the control end of the switch 720 through the debug interface, so that the debug device disconnects the switch 720 through, for example, a GPIO pin (Debug_EN), and the I2C interface of the debug device passes through the debug The interface 720 is coupled to the I2C interface of the power management integrated circuit 410 , so that the debugging device can exchange information with the power management integrated circuit 410 through the I2C interface. The GPIO pins of the debugging device are also coupled to the GPIOs (INT0, INT1 and Reset) of the power management integrated circuit 410 through the debugging interface 720, so that the debugging device can obtain the key signals (INT0, INT1 and Reset) generated by the power management integrated circuit 41. ) values and the times at which these times are generated.

Optionally, the debug device closes the switch 720 through, for example, a GPIO pin (Debug_EN), thereby allowing the control unit 104 to provide information to the power management integrated circuit 410 through the I2C interface during the debugging process. The debugging device also obtains information provided by the control component 104 through the I2C interface to identify whether the behavior of the control component 104 is as expected, and whether the behavior of the power management integrated circuit 410 is as expected.

Optionally, one or more GPIO pins (AVS_EN, GPIO, etc.) of the control component 104 are also coupled to the debug interface 710 . A debug device couples these GPIO pins of the control unit 104 through the debug interface 710 to exchange information with the control unit 104 . For example, the debugging device obtains the AVS_EN signal output by the control unit 104 through the debugging interface 710, and obtains the voltage output by the power supply channel CH1 through the I2C interface of the power management integrated circuit 410, so as to identify whether the power management integrated circuit 410 correctly responds to the voltage provided by the control unit 104. AVS signal.

Still optionally, the debugging device also obtains the time when the input pin Vin of the power management integrated circuit 410 receives the power provided by the host through the debugging interface 710, and obtains the time when the power management integrated circuit 410 then passes the GPIO pins (INT0, INT1 and Reset) The output signal, as well as the timing and voltage value of each power supply channel supplying power to each component of the storage device, thereby identifying whether the work of the power management integrated circuit 410 meets expectations.

Optionally, the debugging device also includes other interfaces such as a UART interface, a JTAG interface, etc., and these other interfaces are coupled to the control unit 104 through the debugging interface 710 to communicate with the control unit 104, for example, to obtain information output by the control unit 104 on these interfaces. information, and/or provide debugging commands to the control unit 104 through these interfaces.

Debugging equipment is particularly useful during debugging the power-up sequence and power-down sequence of the power management integrated circuit 104 . In order to facilitate debugging, the power management integrated circuit 410 collects the voltage/current value of each power input pin and the power output pin of each power supply channel, as well as, for example, the time when the power input interface is provided with stable power, and the time when each power supply supplies stable power time, and stored in its own registers. The debugging device obtains the value of the register of the power management integrated circuit 410 through the I2C interface or other interfaces such as UART/JTAG, so as to know the behavior of the power management integrated circuit 410 during the power-on process and the power-off process. For example, the debugging device knows the time when the power input pin of the power management integrated circuit 410 is supplied with 12V voltage through the debugging interface, and the time when power output is generated on each power supply channel and the output voltage value, and the GPIO pin (INT0, INT1 and Reset) output signals and timing, so as to determine whether the power-on process meets expectations. The debugging device also knows the time of the 12V voltage message of the power input pin of the power management integrated circuit 410 through the debugging interface, and the time of the power output message on each power supply channel, as well as the time of the GPIO pin (INT0, INT1 and Reset) output Signal and timing, so as to determine whether the power-off process meets expectations.

In an optional embodiment, in order to debug the power-on and/or power-off process, the debugging device is also connected to the interface 103 and provides the power management integrated circuit 410 with eg 12V power through the interface 103 . Thus, the debugging device can control and monitor the whole power-up/power-down process. The debugging device also selects the preferred configuration provided to the power management integrated circuit 410 through the repeated power-up/down process. For example, the debugging device sets the specification and timing of the output voltage of each power supply channel for the power management integrated circuit through the I2C interface, and provides 12V power to the power management integrated circuit 410 through the interface 103, and also monitors the power supply channels of the power management integrated circuit 410 and GPIO Whether the output of the pin is as expected. If it does not meet expectations, the debugging component changes the configuration of the power management integrated circuit 410 through the I2C interface, and provides 12V power to the power management integrated circuit 410 through the interface 103 again, and monitors the power supplied to the power management integrated circuit 410 through the interface 103. Does providing 12V of power 410 behave as expected. In this way, the debugging of the power management integrated circuit 410 is completed, and the debugging time is shortened.

As another example, the debugging device actively cuts off the 12V power provided to the power management integrated circuit 410 through the interface 103, and observes through the debugging interface whether the power management integrated circuit 410 generates the expected INT0 and INT1 at the right time through the GPIO pin and other signals, and after the power supply of the power input pin Vin of the power management integrated circuit 410 is cut off, whether the backup power supply and the output voltage of each power supply channel remain valid within a specified time. When the output of the power management integrated circuit 410 does not meet expectations, the debugging component changes the configuration of the power management integrated circuit 410 through the I2C interface, and provides 12V power to the power management integrated circuit 410 through the interface 103 again and cuts off the 12V power supply. power, and monitor whether the behavior to the power management integrated circuit 410 through the interface 103 is as expected.

Fig. 8 shows a schematic diagram of a storage device according to yet another embodiment of the present application. According to the embodiment of FIG. 8 , the ability to debug the power management integrated circuit 410 is provided for the storage device.

Different from the embodiment shown in FIG. 7 , in the embodiment according to FIG. 8 the storage device includes a debug device. The debug device is coupled to the I2C interface of the power management integrated circuit 410 and one or more GPIO pins (INT0, INT1 and Reset). When the storage device is working, the debugging device obtains the status of each power input pin, each power supply channel and each GPIO of the power management integrated circuit 410 at any time, so as to identify whether the behavior of the power management integrated circuit 410 meets expectations.

According to the embodiment of FIG. 8 , a debugging interface independent of the interface 103 is also optionally included. The UART interface or JTAG interface of the debugging device is coupled to the debugging interface, so that when the storage device is connected to an external computer or debugging computer through the debugging interface, the debugging device can be accessed through the debugging interface, and then the power management integrated circuit 410 and the control system can be obtained through the debugging device. Each working state of the component 104. The debug computer also changes the behavior of the debug device through the debug interface.

Continue to refer to Fig. 8, optionally, the interface 103 also includes the pin of the UART interface/JTAG interface that is coupled to the control part 104, and the debugging computer is connected to the UART/JTAG interface of the debugging device through the debugging interface, and the control part is also coupled through the interface 103 104 UART/JATG interface. Therefore, the debugging computer communicates with the control component 104 through the interface 103 , and communicates with the debugging device through the debugging interface, so as to debug the control component 104 and the power management integrated circuit 410 at the same time.

FIG. 9 shows a schematic diagram of a storage device according to yet another embodiment of the present application. The storage device provides an SMBUS interface, and the host accesses the storage device through the SMBUS interface outside the storage interface, for example, obtains configuration information of the storage device through the SMBUS. Some pins of the interface 103 of the storage device are used to provide an SMBUS interface. According to the embodiment shown in Fig. 9, the memory device comprises an EEPROM (Electrically Erasable Programmable Memory). The EERPOM, control unit 104 and/or power management integrated circuit 410 are coupled to the SMBUS. The host reads information from the EEPROM, the control unit 104 and/or the power management integrated circuit 410 by accessing the SMBUS.

In one example, configuration information of the storage device is stored in the EEPROM. The host reads configuration information from EEPROM via SMBUS. And optionally, for some dynamic information, such as temperature information of the storage device, the control unit or the power management integrated circuit 410 writes the dynamic information into the EEPROM, so that the host can read the dynamic information from the EEPROM through the SMBUS.

In yet another example, the host reads configuration information from the EEPROM via SMBUS, and reads dynamic information from the control unit and/or power management integrated circuit 410 via SMBUS.

In yet another example, the control component 104 is coupled to the SMBUS of the interface 103 , while the power management integrated circuit 410 is not coupled to the SMBUS of the interface 103 . The control unit 104 obtains the collected dynamic information such as temperature and capacitor health status from the power management integrated circuit 410 through the I2C interface, and responds to the access of the host through the SMBUS. And optionally, the host also accesses the EERPOM through the SMBUS of the interface 103 .

In yet another example, the power management integrated circuit 410 is coupled to the SMBUS of the interface 103 while the control component 104 is not coupled to the SMBUS of the interface 103 . The control unit 104 provides information such as temperature to the power management integrated circuit 410 through the I2C interface, and the host accesses the power management integrated circuit 410 through the SMBUS to obtain the dynamic information. And optionally, the host also accesses the EERPOM through the SMBUS of the interface 103 to obtain other configuration information.

Although the present invention has been described with reference to examples, it is for the purpose of explanation only and not to limit the application, changes, additions and/or deletions to the embodiments may be made without departing from the scope of the application.

Many modifications and other embodiments of the applications set forth herein will come to mind to those skilled in the art to which these embodiments pertain having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is to be understood that the application is not to be limited to the particular embodiments disclosed and that modifications and other embodiments are intended to be included within the scope of the appended claims. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.

Claims (10)

1. A storage device, comprising: the device comprises a control component, an NVM chip, an interface and a power management component;

the power management component obtains a first power input from the interface and provides power to the control component through a first power channel, an

Power is provided to the NVM chip through a second power supply channel.

2. The memory device of claim 1, further comprising a voltage feedback circuit; the voltage feedback circuit receives the self-adaptive voltage adjusting signal provided by the control part and provides a voltage feedback signal for the first power supply channel;

the power management component adjusts the voltage of the power provided by the first power supply channel according to the voltage feedback signal received by the first power supply channel.

3. The storage device of claim 2, wherein

The power management component reduces a voltage of the power provided to the control component through the first power supply channel when the adaptive voltage adjustment signal indicates that the control component supports the adaptive voltage adjustment function; and

the power management component does not reduce the voltage of the power provided to the control component over the first power supply channel when the adaptive voltage adjustment signal indicates that the control component does not support the adaptive voltage adjustment function.

4. Storage device according to one of claims 1 to 3, wherein

And the power management part provides power for the IO interface of the NVM chip and the IO interface of the control part through a third channel.

5. The storage device of any of claims 1-4, further comprising a backup power source;

the power management component provides power for charging to the backup power source through a sixth power supply channel.

6. The storage device of one of claims 1 to 5, wherein

The power management component provides an active reset signal to the control component in response to the interface of the memory device providing a first power input, and subsequently provides an inactive reset signal to the control component after sequentially providing power to the control component and the NVM chip.

7. The storage device of one of claims 1 to 6,

the power management component further provides a reset signal and one or more interrupt signals to the control component;

the first communication interface of the power management component is also coupled to the communication interface of the control component.

8. The storage device of claim 7, further comprising a debug interface connector;

the reset signal and one or more interrupt signals provided by the power management component to the control component are also connected to the debug interface connector; the first communication interface of the power management component is also coupled to the debug interface connector.

9. The storage device of claim 7 or 8, wherein

The communication interface of the power management component is coupled to the communication interface of the control component through a switch;

a control terminal of the switch is coupled to the debug interface connector;

when the debugging interface connector of the storage device is coupled with a debugging device, the debugging device is coupled to the control end of the switch through the debugging interface connector so as to disconnect the coupling of the communication interface of the power management component to the communication interface of the control component.

10. The storage device of claim 7, further comprising a debug device;

the reset signal and one or more interrupt signals provided by the power management component to the control component are also connected to the debug device; the communication interface of the power management component is also coupled to the debugging device.

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