CN110620140B - 一种柔性梯度应变薄膜及其制备方法和应用 - Google Patents
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- 238000002360 preparation method Methods 0.000 title abstract description 16
- 239000000758 substrate Substances 0.000 claims abstract description 42
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 25
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- 239000010703 silicon Substances 0.000 claims abstract description 25
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- 238000011160 research Methods 0.000 abstract description 5
- 238000005530 etching Methods 0.000 abstract description 4
- 239000002120 nanofilm Substances 0.000 abstract description 2
- 239000000463 material Substances 0.000 description 15
- 230000008859 change Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
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- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 1
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- 239000013078 crystal Substances 0.000 description 1
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- 230000000694 effects Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 238000004321 preservation Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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Abstract
本发明提供一种柔性梯度应变薄膜的制备方法及其应用,属于纳米薄膜制备技术领域。本发明通过在硅薄膜表面刻蚀形成对称且具有共同底边的等腰梯形结构,然后将具备图案的硅薄膜转移至经过预加载的PDMS衬底上,然后释放预加载,即可制备具有梯度应变的周期性纹波结构。本发明制备的具有纹波结构的柔性薄膜能够产生梯度应变,可以在不拉伸和不重复制样的前提下制备出不同大小的应变值,适用于多种环境和条件下的应变工程研究,节约资源,制备工艺简单,使用方便;并且梯度波纹和均匀波纹一样,具备一定的耐拉伸性。
Description
技术领域
本发明属于纳米薄膜制备技术领域,具体涉及一种柔性梯度应变薄膜及其制备方法和应用。
背景技术
近年来,应变工程成为了热点研究领域,特别是对于新兴二维材料和薄膜材料的应变工程研究。应变工程主要是通过在材料上产生一定的应变,来调控和优化材料的物理和化学性能。例如,在半导体领域,研究人员发现,通过对硅基底施加应变,可以使MOS器件的迁移率得到提高,从而使器件响应时间得到提升;在光伏领域,施加应变能够使材料的吸收带边发生偏移,有效抑制电子-空穴对的复合,并提升空穴迁移速率;在催化领域,研究发现应变能增加材料在某一晶面的活性位点,从而提升其催化效率。因此,由于应变带来的对材料性能的改变,如何在材料中产生合适的应变,并研究应变对其的影响,已经成为一个热点领域。
传统的应变工程主要是在材料制备过程中通过晶格适配来产生应变,或是通过基底的电致伸缩来实现。其中晶格适配是指将一种材料通过外延方法生长在另外一种具有不同晶格的基底上,两种材料不同的晶格参数会产生内部的应变,但是该方法制备较为复杂,且应变量一经固定就无法改变;电致伸缩基底是在通电可以伸长/缩短的基底上生长薄膜,生长完毕后对基底通电,基底进行伸缩的同时会给薄膜施加一定的应力,但这种方法对衬底的要求比较高,普适性较低。随着柔性电子的兴起,一种新的方法受到了人们的关注:通过将均匀的无机半导体薄膜转移到预拉伸过的衬底上,之后释放预拉伸,得到了均匀的正弦周期性波纹结构。由于周期波纹的波峰和波谷分别存在着大小相等的拉应变和压应变,周期波纹结构被广泛地应用在应变工程中。这种方法简便易行,免去了薄膜生长中的晶格匹配问题,也不需要电致伸缩材料作为基底,且其应变可以随柔性基底的拉伸而改变,受到了广泛的欢迎。但周期波纹结构也有其不足,由于产生的波纹结构是均匀的,波长和振幅是一个常数,所以所有的波峰处的拉应变也是相同的,所有的波谷处的压应变同样也是相同的,不能在同一张薄膜上产生数值不一的拉应变和压应变。在应用时,如需测试数值不同的应变对材料的影响,可以进行拉伸或者是用不同的工艺制备多个样品,前者在某些测试条件下不允许(譬如测试空间狭小,不够放置拉伸夹具,且对拉伸夹具的精度要求较高),后者则需要重复实验,耗费样品和实验时间。因此,需要一种可以在同一块薄膜上产生数值不一应变的方法。
发明内容
针对背景技术所存在的问题,本发明的目的在于提供一种柔性梯度应变薄膜及其制备方法和应用。本发明通过对薄膜图案进行优化,在周期波纹结构的基础上,制备了具有梯度应变的周期性纹波结构。
为实现上述目的,本发明的技术方案如下,
一种柔性梯度应变薄膜,包括柔性衬底和在衬底表面具有周期性纹波结构的硅薄膜,其特征在于,所述硅薄膜图形为两个关于上底边对称的等腰梯形,且所述两个等腰梯形具有同一上底边。
一种柔性梯度应变薄膜的制备方法,包括以下步骤:
步骤1.在SOI衬底上通过光刻和等离子体干法刻蚀相结合,在SOI顶层硅表面制备两个关于上底边对称的等腰梯形,且所述两个等腰梯形具有同一上底边;
步骤2.将具有图形结构的顶层硅薄膜转移至PDMS印章上;
步骤3.制备PDMS衬底,并对衬底进行紫外光照预处理,然后对其进行预拉伸处理;
步骤4.将PDMS印章上的顶层硅薄膜转移至步骤3预拉伸处理后的PDMS衬底上,释放预拉伸,得到所述具有柔性梯度应变薄膜。
进一步地,等腰梯形图案的上底边与下底边的长度比值为0.3~0.6,上底边和高之间的长度比值为0.1~0.2。其中,两条底边的长度差越大,形成的应变梯度就越大,但中间部分太过狭窄不利于薄膜转移;上底边与下底边的比值固定时,高越长形成的应变梯度越小。
进一步地,步骤1所述顶层硅薄膜的厚度为200~500nm。
进一步地,步骤3所述预拉伸处理为:小于5%的预拉伸量可以通过热膨胀法获得,大于5%的预拉伸量通过拉伸夹具获得。
进一步地,所述热膨胀法具体为将薄膜加热至110~180℃,加热至110℃可得到2.79%的预拉伸,130℃可得到3.56%的预拉伸。
一种调控薄膜梯度应变的方法,具体为:改变预拉伸量,对波纹结构的波长和振幅进行调控,预拉伸越大,波长越小,振幅越大,对应的应变也就越大。
综上所述,由于采用了上述技术方案,本发明的有益效果是:
本发明制备的具有纹波结构的柔性薄膜能够产生梯度应变,可以在不拉伸和不重复制样的前提下制备出不同大小的应变值,适用于多种环境和条件下的应变工程研究,节约资源,制备工艺简单,使用方便;并且梯度波纹和均匀波纹一样,具备一定的耐拉伸性。
附图说明
图1为SOI顶层硅上对称等腰梯形的结构示意图。
图2为本发明柔性梯度应变薄膜波纹结构的光学显微镜图。
图3为本发明柔性梯度应变薄膜波纹结构截面的轮廓图。
图4为本发明柔性梯度应变薄膜的Abaqus力学仿真应力分布图。
图5为基于本发明柔性梯度应变薄膜制备的光电探测器在405nm激光照射下不同拉伸下的IV曲线图。
图6为基于本发明柔性梯度应变薄膜制备的光电探测器在施加不同应变时的电流响应。
具体实施方式
为使本发明的目的、技术方案和优点更加清楚,下面结合实施方式和附图,对本发明作进一步地详细描述。
一种柔性梯度应变薄膜,包括柔性衬底和在衬底表面具有周期性纹波结构的硅薄膜,其特征在于,所述硅薄膜图形为两个关于上底边对称的等腰梯形,且所述两个等腰梯形具有同一上底边。
其中,等腰梯形中较短的底边定义为上底边,较长的底边定义为下底边。
实施例1
一种柔性梯度应变薄膜的制备方法,包括以下步骤:
步骤1.使用AZ6112正胶作为掩膜,光刻曝光时间3.5s,显影45s,在SOI衬底表面制备两个等腰梯形图案,所述两个等腰梯形关于上底边对称的等腰梯形,且所述两个等腰梯形具有同一上底边,该结构上底边b长0.080mm,下底边a长0.252mm,梯形的高0.5c为0.7165mm;
步骤2.使用SF6与O2混合气体来对SOI衬底的硅薄膜层进行等离子刻蚀,RIE功率为100W,刻蚀时间为60s;
步骤3.将步骤2图形化后的SOI基片放入质量分数40%的HF溶液中进行刻蚀,刻蚀后将固化后的PDMS印章与SOI基片紧密贴合后将印章揭起,即可将顶层硅薄膜层转移至PDMS印章上,所述印章按基体与固化剂的重量比为5:1,在60℃加热两小时固化后所得;
步骤4.按基体与固化剂的重量比为10:1,在60℃加热两小时固化后制备得到PDMS衬底,并对衬底进行5min的紫外光照预处理(紫外光会形成臭氧环境,臭氧环境会改变PDMS基底表面的悬挂键,使得其可以和硅形成牢固的硅-氧键接触),然后将衬底加热至130℃,保温6min,得到预拉伸处理后的PDMS衬底;
步骤5.将PDMS衬底被紫外照射的一面与印章有硅膜的一面相贴合,在120℃加热3min,然后将印章揭下(衬底的黏附性大于印章的,所以能转移硅膜),冷却至室温释放预拉伸,即得到所述具有柔性梯度应变薄膜。
一种基于上述柔性梯度应变薄膜制备光电探测器的方法为:使用金属掩膜板,在上述柔性梯度应变薄膜两端溅射制备金电极,电极厚度为150nm,即可制备得到所述光电探测器。
步骤1在SOI顶层硅上制备的对称等腰梯形的结构示意图如图1所示。图2和图3分别为柔性梯度应变薄膜纹波结构的光学显微镜图和截面轮廓图,从图2和图3可以看出,在基底预加载3.56%的应变时,在PDMS制备衬底上制备了梯度波纹硅膜,图2中较亮区域为波峰或波谷,较暗区域为峰谷间的过渡区域,由图3可以看出,从边缘到中间,波纹的振幅逐渐增大,波长逐渐减小,波纹结构的最小波长为56μm,最大波长为63.75μm,振幅从1μm到8.4μm之间变化。为分析其应力应变状态,对其进行Abaqus力学仿真分析,得到应力分布图如图4所示,应变等于应力除以杨氏模量,从图4可见,梯度图案可以带来波纹结构波峰和波谷应力的梯度变化,在样品中间的波峰初应变最大,往两边慢慢缩小,实现了应变的梯度分布。对基于柔性梯度应变薄膜制备的光电探测器,使用KeysightB2902A数字源表,对该期间进行光电响应与应变的响应关系测试,得到的405nm激光照射下不同外加拉伸应变施加下薄膜的I-V曲线图如图5所示,从图5可以看出,随着拉伸量的增大,波纹结构渐渐被拉平,对光的反射慢慢减少,导致吸收减弱。固定光波长405nm和激光功率20mW,实时改变其拉伸,得到光电流-拉伸量的实时变化图如图6,可见在改变其拉伸量后,电流发生了明显变化,说明该器件仍和非梯度应变的周期性纹波结构相同,具有可延展的功能。
以上所述,仅为本发明的具体实施方式,本说明书中所公开的任一特征,除非特别叙述,均可被其他等效或具有类似目的的替代特征加以替换;所公开的所有特征、或所有方法或过程中的步骤,除了互相排斥的特征和/或步骤以外,均可以任何方式组合。
Claims (7)
1.一种柔性梯度应变薄膜,包括柔性衬底和在衬底表面具有周期性纹波结构的硅薄膜,其特征在于,所述硅薄膜图形为两个关于上底边对称的等腰梯形,且所述两个等腰梯形具有同一上底边,其中,等腰梯形中较短的底边定义为上底边,较长的底边定义为下底边。
2.如权利要求1所述柔性梯度应变薄膜的制备方法,其特征在于,包括以下步骤:
步骤1.在SOI衬底上通过光刻和等离子体干法刻蚀相结合,在SOI顶层硅表面制备两个关于上底边对称的等腰梯形图案,且所述两个等腰梯形具有同一上底边;
步骤2.将具有图形结构的顶层硅薄膜转移至PDMS印章上;
步骤3.制备PDMS衬底,并对衬底进行紫外光照预处理,然后对其进行预拉伸处理;
步骤4.将PDMS印章上的顶层硅薄膜转移至步骤3预拉伸处理后的PDMS衬底上,释放预拉伸,得到所需具有柔性梯度应变薄膜。
3.如权利要求2所述柔性梯度应变薄膜的制备方法,其特征在于,等腰梯形图案的上底边与下底边的长度比值为0.3~0.6,上底边与高的长度比值为0.1~0.2。
4.如权利要求2所述柔性梯度应变薄膜的制备方法,其特征在于,步骤1所述顶层硅的厚度为200~500nm。
5.如权利要求2所述柔性梯度应变薄膜的制备方法,其特征在于,步骤3所述预拉伸处理为:小于5%的预拉伸量通过热膨胀法获得,大于5%的预拉伸量通过拉伸夹具获得。
6.如权利要求5所述柔性梯度应变薄膜的制备方法,其特征在于,所述热膨胀法具体为将薄膜加热至110~180℃,加热至110℃得到2.79%的预拉伸,130℃得到3.56%的预拉伸。
7.一种如权利要求1所述柔性梯度应变薄膜的调控方法,具体为:改变预拉伸量,对波纹结构的波长和振幅进行调控,预拉伸越大,波长越小,振幅越大,应变也越大。
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