CN110619916A - Memory programming method and device, electronic equipment and readable storage medium - Google Patents
Memory programming method and device, electronic equipment and readable storage medium Download PDFInfo
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- CN110619916A CN110619916A CN201910738267.3A CN201910738267A CN110619916A CN 110619916 A CN110619916 A CN 110619916A CN 201910738267 A CN201910738267 A CN 201910738267A CN 110619916 A CN110619916 A CN 110619916A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
- G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/24—Bit-line control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
- G11C16/3436—Arrangements for verifying correct programming or erasure
- G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
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Abstract
The invention provides a memory programming method, a device, an electronic device and a readable storage medium, wherein the memory programming method comprises the following steps: 1) programming a memory cell to be programmed in the memory by adopting an initial programming voltage; 2) verifying whether the memory cells are programmed or not, and classifying the memory cells which do not pass the verification according to the programming speed; 3) and respectively programming the memory cells which have different programming speeds and do not pass the verification again by adopting different programming voltages. The invention classifies the programming speed of the memory cells in the verification process after programming by introducing a new memory programming method, a new memory programming device, electronic equipment and a readable storage medium, and different programming voltages are applied to the memory cells with different programming speeds when reprogramming, thereby further reducing the interval range of threshold voltage and ensuring the reliability of the memory.
Description
Technical Field
The present invention relates to the field of semiconductor memory technology, and in particular, to a memory programming method and apparatus, an electronic device, and a readable storage medium.
Background
The NAND flash memory is a nonvolatile memory, and has the advantages of low cost, low power consumption, and large storage capacity. Memory cells (memory cells) of the NAND flash memory differentiate memory states by setting different threshold voltages. If the interval between different threshold voltage intervals is small, the discrimination of each storage state is reduced, and the storage data is easy to generate errors. This requires that the threshold voltage of each memory state fall within a narrow range as much as possible during programming for rewriting the NAND flash memory to increase the interval between threshold voltage ranges.
Currently, for NAND flash memories, an incremental pulse programming (ISPP) method is commonly used to perform programming to obtain a narrower range of threshold voltage. That is, the memory cells are programmed sequentially using a plurality of pulse programming voltages which are incremented step by step, and whether the memory cells pass the verification is verified after each programming, the verified memory cells are masked, and the programming and verification are continued using the incremented pulse programming voltages for the memory cells which do not pass the verification until the number of the verified memory cells reaches a set value. The method relieves the phenomenon of too wide threshold voltage distribution range when single high voltage programming is adopted to a certain extent by gradually increasing the pulse programming voltage.
However, with the increasing development of NAND technology, the number of memory states provided in a single memory cell is also increasing in order to increase the memory capacity. In contrast to distinguishing only two memory states of "1" or "0" in a single-level cell (SLC), four memory states of "11", "10", "01", and "00" can be distinguished in a multi-level cell (MLC). In the TLC or QLC with higher storage capacity, the storage state is also multiplied accordingly. This requires further reduction of the threshold voltage range of each memory state during programming, so as to increase the storage capacity and ensure the reliability of the NAND flash memory.
Therefore, it is necessary to provide a new memory programming method, device, electronic device and readable storage medium to solve the above problems.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a memory programming method, device, electronic device and readable storage medium, which are used to solve the problem of the prior art that the threshold voltage range is too wide when programming a memory.
To achieve the above and other related objects, the present invention provides a memory programming method, comprising:
1) programming a memory cell to be programmed in the memory by adopting an initial programming voltage;
2) verifying whether the memory cells are programmed or not, and classifying the memory cells which do not pass the verification according to the programming speed;
3) and respectively programming the memory cells which have different programming speeds and do not pass the verification again by adopting different programming voltages.
As an alternative of the present invention, in step 2), whether the memory cell is programmed is verified, and the method for classifying the memory cells which are not verified according to the programming speed includes: verifying the programmed memory cell by adopting a programming pass verification voltage and at least one programming speed verification voltage; determining the memory cells verified by the program-pass verification voltage as the memory cells verified by the verification voltage, and determining the memory cells not verified by the program-pass verification voltage as the memory cells not verified by the verification voltage; and classifying the programming speed of the memory cells which do not pass the verification according to whether the programming speed verification voltage verification is passed or not.
As an alternative of the present invention, the program speed verifying voltage is a voltage that determines the memory cells that have not been verified by the program speed verifying voltage as fast cells and determines the memory cells that have not been verified by the program speed verifying voltage as slow cells.
As an alternative of the invention, the different programming voltages comprise programming voltages having different voltage values and/or durations.
As an alternative of the present invention, the different programming voltages include a first programming voltage and a second programming voltage, the duration of the first programming voltage being less than the second programming voltage; and reprogramming the fast unit by adopting the first programming voltage, and reprogramming the slow unit by adopting the second programming voltage.
As an alternative of the present invention, a method of generating the first and second programming voltages includes: and applying word line voltage pulses to word lines of the fast unit and the slow unit, wherein the word line voltage pulses are divided into a first time interval and a second time interval which are connected in a front-back mode in duration, a high level is applied to a bit line of the fast unit in the first time interval, the bit line is grounded in the second time interval, and the bit line of the slow unit is grounded in the first time interval and the second time interval.
As an alternative of the present invention, the different programming voltages include a third programming voltage and a fourth programming voltage, the duration of the third programming voltage is less than the fourth programming voltage, and the voltage value of the third programming voltage is less than the voltage value of the fourth programming voltage; and reprogramming the fast unit by adopting the third programming voltage, and reprogramming the slow unit by adopting the fourth programming voltage.
As an alternative of the present invention, a method of generating the third and fourth program voltages includes: the word line voltage pulse is divided into a first time interval and a second time interval which are connected in the front and back direction in duration, the voltage value of the word line voltage pulse in the first time interval is higher than that of the word line voltage pulse in the second time interval, the bit line of the fast unit applies high level in the first time interval and is grounded in the second time interval, and the bit line of the slow unit is grounded in the first time interval and the second time interval.
As an alternative of the present invention, after the memory cells which have different programming speeds and have failed verification are respectively programmed again by using different programming voltages, the method further comprises the following steps:
4) verifying whether the memory cell completes programming again;
5) respectively programming the memory cells which have different programming speeds and do not pass the verification again by adopting different programming voltages;
6) and circularly executing the steps 4) to 5) until the count of the storage units passing the verification is larger than a set value.
As an alternative of the present invention, in step 4), a process of reclassifying the memory cells which do not pass the verification according to the programming speed is further included.
As an alternative of the present invention, in step 3), the voltage value of the programming voltage is higher than the voltage value of the initial programming voltage; in step 6), each time step 4) to step 5) are executed in a loop, the voltage value of the program voltage in step 5) is higher than the voltage value of the program voltage in step 5) in the previous loop.
As an alternative of the present invention, in step 6), the ratio of the voltage value of the programming voltage to the duration of the programming voltage in step 5) is a fixed value every time step 4) to step 5) are cyclically performed.
As an alternative of the present invention, in step 2), before classifying the memory cells that fail to be verified according to the programming speed, a step of performing a specified number of programming and verifying processes on the memory cells that fail to be verified is further included.
As an alternative of the invention, the memory comprises a NAND flash memory.
The invention also provides a memory programming device, which is characterized in that: the method comprises the following steps:
the initial programming module is used for programming a memory cell to be programmed in the memory by adopting an initial programming voltage;
the verification module is used for verifying whether the programming of the memory unit is finished and classifying the memory units which do not pass the verification according to the programming speed;
and the reprogramming module is used for respectively reprogramming the memory cells which have different programming speeds and do not pass the verification by adopting different programming voltages.
As an alternative of the present invention, the verifying module includes a program-pass verifying unit verifying the memory cells with a program-pass verifying voltage, determining the memory cells verified by the program-pass verifying voltage as the memory cells verified, and determining the memory cells not verified by the program-pass verifying voltage as the memory cells not verified; the programming speed verification unit classifies the programming speed of the memory cells which do not pass the verification by adopting at least one programming speed verification voltage.
As an alternative of the invention, the reprogramming module comprises:
a re-verifying unit for re-verifying whether the memory cell is programmed;
a reprogramming unit for respectively reprogramming the memory cells which have different programming speeds and have not passed the verification by using different programming voltages;
and the circulation judging unit is used for controlling the reprogramming unit and the re-verifying unit to circularly execute the re-programming and re-verifying processes until the count of the storage unit passing the verification is greater than a set value.
The invention also provides an electronic device, which is characterized in that: the method comprises the following steps:
a processor for implementing the memory programming method according to the present invention;
an instruction memory coupled to the processor for storing instructions executable by the processor.
The present invention also provides a computer-readable storage medium having stored thereon a computer program characterized in that: which when executed by a processor implements the memory programming method according to the invention.
As described above, the present invention provides a memory programming method, device, electronic device and readable storage medium, which have the following advantages:
the invention classifies the programming speed of the memory cells in the verification process after programming by introducing a new memory programming method, a new memory programming device, electronic equipment and a readable storage medium, and different programming voltages are applied to the memory cells with different programming speeds when reprogramming, thereby further reducing the interval range of threshold voltage and ensuring the reliability of the memory.
Drawings
Fig. 1 is a flowchart illustrating a method for programming a memory according to a first embodiment of the present invention.
Fig. 2 is a flowchart illustrating an implementation of a memory programming method according to a first embodiment of the invention.
Fig. 3 is a schematic circuit diagram illustrating a NAND flash memory used in a memory programming method according to an embodiment of the present invention.
FIG. 4 is a diagram illustrating the relationship between the cell count and the threshold voltage in the conventional ISPP process according to an embodiment of the present invention.
FIG. 5 is a diagram illustrating a relationship between a cell count and a threshold voltage in a memory programming method according to a first embodiment of the present invention.
FIG. 6 is a graph showing the variation of word line voltage with time during multiple programming and verifying processes in a memory programming method according to one embodiment of the present invention.
FIG. 7 is a graph showing the relationship between the word line voltage and the applied bit line voltage across each memory cell over time in a memory programming method according to one embodiment of the present invention.
FIG. 8 is a graph showing the variation of word line voltage with time during multiple programming and verifying processes in a memory programming method according to a second embodiment of the present invention.
FIG. 9 is a graph showing the relationship between the word line voltage and the bit line voltage applied to each memory cell over time in a memory programming method according to a second embodiment of the present invention.
Fig. 10 is a flowchart illustrating an implementation of a memory programming method according to a third embodiment of the present invention.
FIG. 11 is a graph showing the variation of word line voltage with time during multiple programming and verifying processes in a memory programming method according to a third embodiment of the present invention.
Fig. 12 is a diagram illustrating a connection relationship between components in an electronic device according to a fifth embodiment of the present invention.
Description of the element reference numerals
101-110 Steps 101-110
111 slow cell interval
112 fast cell interval
113 passing cell interval
114 programmed cell interval
115 comparison interval
201 to 213 Steps 201 to 213
301 processor
302 instruction memory
S1-S6 steps 1) -6)
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 12. It should be noted that the drawings provided in the present embodiment are only schematic and illustrate the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
Example one
Referring to fig. 1 to 7, the present embodiment provides a memory programming method, including the following steps:
1) programming a memory cell to be programmed in the memory by adopting an initial programming voltage;
2) verifying whether the memory cells are programmed or not, and classifying the memory cells which do not pass the verification according to the programming speed;
3) and respectively programming the memory cells which have different programming speeds and do not pass the verification again by adopting different programming voltages.
In step 1), as shown in S1 of fig. 1 and fig. 2, the memory cell to be programmed in the memory is programmed with an initial program voltage. In the flow chart shown in fig. 2, the programming process is started in step 101, initial setup is performed in step 102, data to be programmed is loaded, the location to be programmed (i.e. the set programming address) is identified, and the programming voltage V is set according to a trim table (i.e. the reference table when setting the programming voltage)pgmSet to the initial programming voltage Vpgm_initAnd the pulse count PC (pulse count)t) is set to 0 and then a first programming is performed in step 103. In this embodiment, the pulse count PC is set to increase PC by 1 every time programming is performed, and a maximum pulse count pcmax (pulse count maximum) is set, and it is determined whether PC reaches a set value pcmax in step 105. When it is determined that PC reaches PCMAX, the programming is ended in step 110. Initial programming voltage Vpgm_initThe memory cell verification method is a preset value set according to the actual situation of the memory, and under the preset value, the problem that the threshold voltage distribution is wide due to the fact that the single-time programming voltage is too high can be avoided, and enough programming voltage can be ensured to enable part of memory cells to pass verification.
Fig. 3 is a schematic circuit diagram of the NAND flash memory employed in the present embodiment. The programming and verifying process for the memory cell includes: when programming a page (page) corresponding to a word line WLsel to be programmed, a program voltage V is applied to the word line WLselpgmEach memory cell in the page is programmed according to its corresponding bit line voltage. For example, when the bit line BL1 is applied with a voltage of 0V, the bit line BL2 is applied with a voltage of the power supply voltage VddAt this time, the memory cell corresponding to the bit line BL1 is programmed, and the memory cell corresponding to the bit line BL2 is not programmed. In the verify process after programming, a verify voltage is applied to the word line WLsel to verify the magnitude of the threshold voltage of each memory cell and determine whether it passes the verify. It should be noted that the programming method of the present invention is not limited to the NAND flash memory circuit structure shown in fig. 3, but can also be applied to any other possible NAND flash memory circuit structure, such as a structure in which a word line connects a plurality of pages, or other memory types that need to change the memory state through a verification process, such as NOR flash memory.
In step 2), as shown in S2 of fig. 1 and fig. 2 to 5, it is verified whether the memory cell is programmed, and the memory cells that fail to be verified are classified according to the programming speed. In the flowchart shown in fig. 2, after the first programming is completed in step 103, whether the programming of the memory cell is completed is verified in step 104, and the memory cells that fail to be verified are programmedAnd (5) classifying according to the stroke speed. Optionally, the method of verifying and classifying includes: verifying the programmed memory cell by adopting a programming pass verification voltage and at least one programming speed verification voltage; determining the memory cells verified by the program-pass verification voltage as the memory cells verified by the verification voltage, and determining the memory cells not verified by the program-pass verification voltage as the memory cells not verified by the verification voltage; and classifying the programming speed of the memory cells which do not pass the verification according to whether the programming speed verification voltage verification is passed or not. In this embodiment, the program pass verify voltage is VvryAnd the programming speed verification voltage is one, i.e., Vvry1. Will pass the programming speed verification voltage Vvry1The memory cells that fail verification are determined as fast cells, and fail the programming speed verification voltage Vvry1The memory cells that are not verified are determined to be slow cells. Specifically, in step 104, when the threshold voltage V of the memory cell is higher than the threshold voltage Vth<Vvry1If so, determining the memory cell as a slow cell; when the threshold voltage V of the memory cellth>Vvry1Then, the storage unit is judged as a fast unit; when the threshold voltage V of the memory cellth>VvryAnd a passing unit for judging the storage unit as passing the verification.
FIG. 4 shows the cell count and threshold voltage V of the conventional ISPP processthWherein the upper is the memory cell count versus threshold voltage V during programmingthThe lower part is the memory cell count and the threshold voltage V after the programming is finishedthA graph of the relationship (c). As can be seen from the figure, in the ISPP process, after one pulse programming voltage is applied, the threshold voltage V of some memory cells will be generatedthGreater than the program pass verify voltage VvryAnd the threshold voltage V of another part of the memory cellsthStill less than the program pass verify voltage Vvry(ii) a Programming by increasing pulse programming voltage multiple timesThen, finally, all the threshold voltages V of the memory cells in the settingthAre both greater than the program pass verify voltage VvryThereby completing the programming process. Although the ISPP process reduces the threshold voltage V after programming to a certain extentthBut in MLC or even TLC or QLC NAND flash applications, it is still desirable to be able to further reduce the threshold voltage VthThe interval distribution range of (2).
Analyzing the above programming process, it can be seen that the existing ISPP process passes the verification voltage V only through the programmingvryAnd distinguishing whether the memory cells pass the verification, and programming the memory cells which do not pass the verification by the pulse programming voltage after increment in the subsequent programming process. This results in the memory cell being programmed at the same pulse programming voltage regardless of the programming speed. Wherein the memory cell with the faster programming speed can obtain a higher threshold voltage, so that the programmed threshold voltage VthFalls within a wide range. In this regard, the programming method of the present invention is advantageous in that the program speed verifying voltage V is used after one-time programming processvry1Classifying the memory cells which do not pass the verification according to the programming speed of the memory cells, and respectively programming the memory cells which do not pass the verification and have different programming speeds again by adopting different programming voltages in the subsequent programming process.
As shown in FIG. 5, the cell count and the threshold voltage V in the programming process of this embodimentthWherein the upper is the memory cell count versus threshold voltage V during programmingthThe lower part is the memory cell count and the threshold voltage V after the programming is finishedthA graph of the relationship (c). As can be seen from FIG. 5, during programming, the verify voltage V is verified by introducing the program speedvry1And classifying the memory cells which fail to be verified according to the programming speed of the memory cells. In FIG. 5, the voltage V is verified by the programming speedvry1And the program pass verify voltage VvrySetting the threshold voltage V of the memory cellthDivided into a slow cell interval 111, a fast cell interval 112, and a pass cell interval 113. In the subsequent reprogramming process, different programming voltages are applied to the memory cells in the slow cell interval 111 and the fast cell interval 112, respectively, so that the programmed threshold voltage V can be finally obtainedthThe distribution interval of (2) is greatly reduced. As shown in FIG. 5, the programmed cell interval 114 is the threshold voltage V after the programming process of the present embodimentthThe distribution interval of (a) is significantly smaller than the comparison interval 115 obtained by the ISPP process in the prior art. It should be noted that only one kind of the program speed verifying voltage V is used in the present embodimentvry1The memory cells that fail verification are divided into fast cells and slow cells, and in other embodiments of the present invention, the number of the programming speed verification voltages may be increased and the programming speed verification voltages of different sizes may be set to further divide the memory cells that fail verification by the programming speed. For example, introducing Vvry1And Vvry2Two programming speed verify voltages divide the memory cell into a slow cell, a medium cell, and a fast cell. In the subsequent reprogramming process, different programming voltages are applied to the slow speed unit, the medium speed unit and the fast speed unit respectively to further increase the reduced threshold voltage V of the inventionthThe effect of the distribution interval.
FIG. 6 is a graph showing the variation of word line voltage with time during multiple programming and verifying operations in the present embodiment. Wherein, VpgmIs the programming voltage, VpassIs the bit line conduction voltage. VstepIs the increment of the programming voltage at a time, i.e. Δ V in the figure1、ΔV2、ΔV3An incremental difference therebetween. Alternatively, in the present embodiment, Δ V1/T1、ΔV2/T2、ΔV3/T3And Δ V/TselwlThe ratio of the voltage to the pulse width is equal and is a settable constant, so that the duration of the programming voltage is prolonged along with the increase of the voltage, and the voltage rise time can be prevented from influencing the effective duration of the programming voltage when the pulse duration is shorter. As can also be seen in FIG. 6, the programming voltage is pulsed at each passThen, the verification voltage V is passed through the programmingvryThe programming status of each memory cell is verified. Wherein the programming speed verification voltage V is also passed after the first programming processvry1The programming speed of the memory cell is classified. That is, in step 104 of FIG. 2, when the threshold voltage V of the memory cell is reachedth<Vvry1If so, determining the memory cell as a slow cell; when the threshold voltage V of the memory cellth>Vvry1Then, the storage unit is judged as a fast unit; when the threshold voltage V of the memory cellth>VvryThen, the storage means is determined as a pass means.
It should be noted that, in this embodiment, the memory cells that fail to be verified are only divided according to the programming speed after the first programming, but in other embodiments of the present invention, the programming speed of the memory cells may be further classified after each subsequent programming, and the programming process may be performed according to the new classification result in the next programming process.
In step 3), as shown in S3 of fig. 1 and fig. 3, the memory cells that have not passed the verification and have different programming speeds are re-programmed with different programming voltages.
As an example, the different programming voltages include the programming voltage having a duration. Optionally, the different programming voltages include a first programming voltage and a second programming voltage, the first programming voltage having a duration less than the second programming voltage; and reprogramming the fast unit by adopting the first programming voltage, and reprogramming the slow unit by adopting the second programming voltage.
As an example, a method of generating the first and second programming voltages includes: and applying word line voltage pulses to word lines of the fast unit and the slow unit, wherein the word line voltage pulses are divided into a first time interval and a second time interval which are connected in a front-back mode in duration, a high level is applied to a bit line of the fast unit in the first time interval, the bit line is grounded in the second time interval, and the bit line of the slow unit is grounded in the first time interval and the second time interval.
Specifically, as shown in FIG. 7, the word line voltage applied to word line WLsel is plotted against the bit line voltage applied to each memory cell over time during programming. As can be seen in fig. 7, the bit line voltage applied to the slow cells is different from that applied to the fast cells. As can be seen in connection with step 106 of FIG. 2, the slow cells remain at the 0V bit line voltage throughout the programming process, which results in the word line voltage ViThe slow cells can always be programmed; while the fast cells are Δ T before the programming processnThe bit line voltage is maintained at a set value V during the timefast_BLThis suppresses the word line voltage ViAt Δ TnProgramming of fast cells in time, i.e. the effective duration of the first programming voltage is Δ Ti-ΔTnLess than the duration of the second programming voltage Δ Ti. Wherein, Delta TnAnd Vfast_BLAll are adjustable parameters, which can be adjusted according to the actual situation to adjust the condition difference of the programming voltage between the fast unit and the slow unit. In addition, the bit line voltage of the pass cell determined to pass the verification during the verification is set to the power supply voltage V throughout the programming processddTo mask the effect of the programming process on memory cells that have passed verification.
As an example, as shown in S4 to S6 of fig. 1, after the memory cells which have different programming speeds and are not verified are programmed again with different programming voltages, the method further includes the following steps:
4) verifying whether the memory cell completes programming again;
5) respectively programming the memory cells which have different programming speeds and do not pass the verification again by adopting different programming voltages;
6) and circularly executing the steps 4) to 5) until the count of the storage units passing the verification is larger than a set value.
Referring to step 107 of FIG. 2, after the determination and classification of the memory cells are completed in step 106, the programming voltage is increasedThe voltage and pulse width are programmed again. After the programming process is performed, the program pass verify voltage V is used againvryThe programming status of each memory cell is verified. In step 108, the verification process is judged, and if the number of memory cells which fail to be verified is less than the set allowable number, the programming can be ended; otherwise, step 109 is executed to continue increasing the programming voltage, increasing the pulse count PC, and jumping to step 105 to determine whether PC reaches PC MAX to start the next programming cycle. It can be seen that in this embodiment, there are two trigger nodes for determining the end of programming, one is to determine whether the pulse count PC reaches PC MAX in step 105, and the other is to determine whether the number of memory cells that fail to be verified is less than the set allowable number in step 108. The memory cell can be further prevented from being programmed by adopting an excessively high programming voltage through the node arrangement, so that a narrower threshold voltage V is ensured after programmingthAnd (4) distribution intervals.
Example two
Referring to fig. 8 to 9, the present embodiment provides a memory programming method. Compared with the method in the first embodiment, the difference of the present embodiment is that: in this embodiment, the different programming voltages include the programming voltages having different voltage values and durations.
As an example, the different programming voltages include a third programming voltage and a fourth programming voltage, the third programming voltage has a duration less than the fourth programming voltage, and the third programming voltage has a voltage value less than the fourth programming voltage; and reprogramming the fast unit by adopting the third programming voltage, and reprogramming the slow unit by adopting the fourth programming voltage. In this embodiment, the voltage value of the third programming voltage is smaller than the voltage value of the fourth programming voltage by introducing a word line voltage varying with a time interval and adjusting a bit line voltage at a corresponding time interval.
For example, FIG. 8 is a graph of the word line voltage as a function of time during multiple programming and verifying operations in the present embodiment, and FIG. 9 is a graph of the word line voltage applied to word line WLsel as a function of time with respect to the bit line voltage applied to each memory cell. The method of generating the third and fourth programming voltages includes: the word line voltage pulse is divided into a first time interval and a second time interval which are connected in the front and back direction in duration, the voltage value of the word line voltage pulse in the first time interval is higher than that of the word line voltage pulse in the second time interval, the bit line of the fast unit applies high level in the first time interval and is grounded in the second time interval, and the bit line of the slow unit is grounded in the first time interval and the second time interval.
In particular, as can be seen from fig. 8, the subsequent multi-pulse program voltages have varying voltage values except for the program voltage applied during the first programming. The variation of the voltage value is applied separately according to the fast cell and the slow cell. As can be seen from FIG. 9, in the first comparative example, FIG. 7, in this example, the word line voltage is at Δ Ti1And Δ Ti2The voltage values at different time intervals are different. For a fast cell, the effective programming time Δ T isi-ΔTnThe word line voltage is lower Vi2(ii) a For the slow cell, it is in the time interval Δ Ti1Can obtain higher word line voltage Vi1To be programmed. Compared with the first embodiment, the present embodiment further distinguishes the programming conditions of the fast cells and the slow cells by introducing the programming voltages with different voltage values, and reduces the influence of the high programming voltage on the fast cells during programming, so as to ensure that a narrower threshold voltage V is obtained after programmingthAnd (4) distribution intervals. Optionally, in this embodiment, the word line voltage duration Δ Ti1And Δ Ti2And word line voltage Vi1And Vi2The value of (A) can be flexibly adjusted according to the actual situation so as to correspond to the respective suitable programming conditions of the fast unit and the slow unit.
Other embodiments of this embodiment are the same as the first embodiment, and are not described herein again.
EXAMPLE III
Referring to fig. 10 to 11, the present embodiment provides a memory programming method. Compared with the method in the second embodiment, the difference of the present embodiment is that: before the fast unit and the slow unit are distinguished, a plurality of programming and verifying processes are executed, after the gradually increased programming voltage is increased to a certain degree, the memory unit is divided into the fast unit and the slow unit to be programmed, and the programming speed is classified and judged in each verifying process.
As an example, in step 2), before classifying the memory cells which fail to be verified according to the programming speed, the method further includes the step of performing the programming and verifying processes for the memory cells which fail to be verified for a specified number of times. The advantage of the scheme in this embodiment is that the programming and verifying processes are performed several times before the programming speed of the memory cells is differentiated. Since the programming voltage is small in the initial stage of programming and its influence on the final threshold voltage distribution range is limited, it is helpful to increase the programming speed to program without distinguishing the programming speed in this stage. And when the programming voltage reaches a set value, distinguishing the programming speed of the memory unit, and applying different programming voltages to the fast unit and the slow unit respectively to ensure that a narrower threshold voltage distribution interval is obtained after programming.
For example, please refer to fig. 10 for a flowchart of the embodiment. In FIG. 10, programming begins at step 201, initial setup is performed at step 202, data to be programmed is loaded, the location to be programmed is identified (i.e., the programming address is set), and the programming voltage V is applied according to a trim tablepgmSet to the initial programming voltage Vpgm_initAnd the initial value of the pulse count PC is set to 0. In step 203, a pulse count PC (pulse count) is determined, and once the pulse count PC MAX (pulse count maximum) is reached, the programming is determined to be finished. Otherwise, go to step 204 to increase the programming voltage VpgmAnd pulse width and start programming. After the programming is completed, the PC is judged again in step 205. In thatIn this embodiment, a preset determination parameter pcmk (pulse count mark) is introduced to represent the number of times of executing the programming process before the programming speed differentiation is performed. For example, in the present embodiment, if PCMK is set to 2, 2 times of programming processes without program speed differentiation are performed before the program speed differentiation is performed. If the PC does not reach the PCMK set in step 205, the process proceeds to step 206, where V is passed onlyvryVerifying whether the storage unit passes the verification; if PC reaches the set PCMK, step 207 is proceeded to when the threshold voltage V of the memory cellth<Vvry1If so, determining the memory cell as a slow cell; when the threshold voltage V of the memory cellth>Vvry1Then, the storage unit is judged as a fast unit; when the threshold voltage V of the memory cellth>Vvry1Then, the memory cell is determined as a fast cell. If the non-verified cell count is less than the set threshold number in step 208, the programming can be terminated directly, otherwise step 210 is entered to further increase the programming voltage VpgmAnd adds 1 to PC. In step 211, it is determined again whether PC reaches PCMK, and if it does not reach PCMK, the corresponding programming voltage that does not distinguish the programming speed is used for programming in step 212; otherwise, in step 213, different programming voltages are applied for the fast and slow cells. And then jumping to step 203 to judge the PC, and performing the next round of circulation until the programming is finished.
FIG. 11 is a graph showing the variation of word line voltage with time during multiple programming and verifying operations in the present embodiment. As described above, in this embodiment, with PCMK set to 2, programming without programming speed differentiation is performed 2 times before programming with program speed differentiation. After the second programming is finished, verifying the voltage V by adopting the programming speedvry1And the program pass verify voltage VvryAfter passing verification and programming speed discrimination are respectively carried out, and the memory cells are divided into fast cells and slow cells, different programming voltages are applied in the subsequent programming process. Note that in this embodiment, the PCMK is set to 2 onlyTo facilitate the illustration of the embodiment, the specific value of PCMK may be flexibly set according to actual needs. In the embodiment, by introducing the PCMK parameter, whether the pulse count PC reaches PCMK is determined in the programming process, and in the initial stage of programming, that is, when the programming voltage is low, programming without distinguishing the programming speed is performed; and when the pulse count PC reaches PCMK, i.e., the program voltage is high, the program for distinguishing the program speed starts. This not only ensures a narrower threshold voltage distribution interval after programming, but also avoids unnecessary programming speed differentiation, increasing the execution speed of the programming process.
Other embodiments of this embodiment are the same as the embodiment, and are not described herein again.
Example four
The embodiment provides a memory programming device, comprising:
the initial programming module is used for programming a memory cell to be programmed in the memory by adopting an initial programming voltage;
the verification module is used for verifying whether the programming of the memory unit is finished and classifying the memory units which do not pass the verification according to the programming speed;
and the reprogramming module is used for respectively reprogramming the memory cells which have different programming speeds and do not pass the verification by adopting different programming voltages.
As an example, the memory programming device provided in this embodiment can be used for implementing any one of the memory programming methods in embodiments one to three. The functions of the initial programming module, the verifying module and the reprogramming module may also be adjusted accordingly according to different embodiments of the memory programming method.
As an example, the verification module includes a program-pass verification unit verifying the memory cells with a program-pass verification voltage, determining the memory cells verified by the program-pass verification voltage as the memory cells verified, and determining the memory cells not verified by the program-pass verification voltage as the memory cells not verified; the programming speed verification unit classifies the programming speed of the memory cells which do not pass the verification by adopting at least one programming speed verification voltage. Specifically, the program speed verifying unit may set one of the program speed verifying voltages, determine the memory cells that have not been verified by the program speed verifying voltage as fast cells, and determine the memory cells that have not been verified by the program speed verifying voltage as slow cells. By distinguishing the fast cells from the slow cells, different programming voltages can be applied to the memory cells with different speeds when the reprogramming module performs reprogramming so as to ensure that a narrower threshold voltage distribution interval is obtained after programming.
As an example, the reprogramming module includes:
a re-verifying unit for re-verifying whether the memory cell is programmed;
a reprogramming unit for respectively reprogramming the memory cells which have different programming speeds and have not passed the verification by using different programming voltages;
and the circulation judging unit is used for controlling the reprogramming unit and the re-verifying unit to circularly execute the re-programming and re-verifying processes until the count of the storage unit passing the verification is greater than a set value.
After the reprogramming module executes one-time reprogramming, the reprogramming condition of the memory unit is verified again, different programming voltages are adopted to respectively reprogram the memory units which have different programming speeds and do not pass the verification, and the verifying and programming processes are repeatedly executed until the count of the memory units which pass the verification is larger than a set value.
EXAMPLE five
As shown in fig. 12, the present embodiment provides an electronic device, which may include a processor 301 and an instruction memory 302, wherein the processor 301 and the instruction memory 302 may be connected to each other through a bus or other means through a communication interface. Specifically, the processor 301 may be any available device with information processing function, such as a central processing unit or a digital signal processor, etc., for implementing the memory programming method according to embodiments one to three; the instruction memory 302 is connected to the processor 301, and may be any available storage medium for storing instructions executable by the processor 301.
EXAMPLE six
The present embodiment provides a computer-readable storage medium having a computer program stored thereon, characterized in that: the computer program, when executed by a processor, implements the memory programming method of embodiments one through three.
As an example, it can be understood by those skilled in the art that all or part of the processes in the methods of the embodiments described above can be implemented by instructing the related hardware through a computer program, and the program can be stored in a computer readable storage medium, and when executed, the program can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic Disk, an optical Disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a Flash Memory (Flash Memory), a Hard Disk (Hard Disk Drive, HDD), a Solid-State Drive (SSD), or the like; the storage medium may also comprise a combination of memories of the kind described above.
In summary, the present invention provides a memory programming method, a memory programming apparatus, an electronic device, and a readable storage medium, where the memory programming method includes the following steps: 1) programming a memory cell to be programmed in the memory by adopting an initial programming voltage; 2) verifying whether the memory cells are programmed or not, and classifying the memory cells which do not pass the verification according to the programming speed; 3) and respectively programming the memory cells which have different programming speeds and do not pass the verification again by adopting different programming voltages. The invention classifies the programming speed of the memory cells in the verification process after programming by introducing a new memory programming method, a new memory programming device, electronic equipment and a readable storage medium, and different programming voltages are applied to the memory cells with different programming speeds when reprogramming, thereby further reducing the interval range of threshold voltage and ensuring the reliability of the memory.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.
Claims (19)
1. A method for programming a memory, comprising the steps of:
1) programming a memory cell to be programmed in the memory by adopting an initial programming voltage;
2) verifying whether the memory cells are programmed or not, and classifying the memory cells which do not pass the verification according to the programming speed;
3) and respectively programming the memory cells which have different programming speeds and do not pass the verification again by adopting different programming voltages.
2. The memory programming method according to claim 1, wherein: in step 2), verifying whether the memory cells are programmed, and classifying the memory cells which do not pass the verification according to the programming speed comprises the following steps: verifying the programmed memory cell by adopting a programming pass verification voltage and at least one programming speed verification voltage; determining the memory cells verified by the program-pass verification voltage as the memory cells verified by the verification voltage, and determining the memory cells not verified by the program-pass verification voltage as the memory cells not verified by the verification voltage; and classifying the programming speed of the memory cells which do not pass the verification according to whether the programming speed verification voltage verification is passed or not.
3. The memory programming method according to claim 2, wherein: the programming speed verifying voltage is one of a type that the memory cell that is not verified by the programming speed verifying voltage is determined as a fast cell and a type that is not verified by the programming speed verifying voltage is determined as a slow cell.
4. The memory programming method according to claim 3, wherein: different ones of the programming voltages include the programming voltages having different voltage values and/or durations.
5. The memory programming method according to claim 4, wherein: the different programming voltages include a first programming voltage and a second programming voltage, the first programming voltage having a duration less than the second programming voltage; and reprogramming the fast unit by adopting the first programming voltage, and reprogramming the slow unit by adopting the second programming voltage.
6. The memory programming method according to claim 5, wherein: the method of generating the first and second programming voltages includes: and applying word line voltage pulses to word lines of the fast unit and the slow unit, wherein the word line voltage pulses are divided into a first time interval and a second time interval which are connected in a front-back mode in duration, a high level is applied to a bit line of the fast unit in the first time interval, the bit line is grounded in the second time interval, and the bit line of the slow unit is grounded in the first time interval and the second time interval.
7. The memory programming method according to claim 4, wherein: the different programming voltages include a third programming voltage and a fourth programming voltage, the third programming voltage has a duration less than the fourth programming voltage, and the third programming voltage has a voltage value less than the fourth programming voltage; and reprogramming the fast unit by adopting the third programming voltage, and reprogramming the slow unit by adopting the fourth programming voltage.
8. The memory programming method according to claim 7, wherein: the method of generating the third and fourth programming voltages includes: the word line voltage pulse is divided into a first time interval and a second time interval which are connected in the front and back direction in duration, the voltage value of the word line voltage pulse in the first time interval is higher than that of the word line voltage pulse in the second time interval, the bit line of the fast unit applies high level in the first time interval and is grounded in the second time interval, and the bit line of the slow unit is grounded in the first time interval and the second time interval.
9. The memory programming method according to claim 1, wherein: after the memory cells which are not verified and have different programming speeds are respectively programmed again by adopting different programming voltages, the method further comprises the following steps:
4) verifying whether the memory cell completes programming again;
5) respectively programming the memory cells which have different programming speeds and do not pass the verification again by adopting different programming voltages;
6) and circularly executing the steps 4) to 5) until the count of the storage units passing the verification is larger than a set value.
10. The memory programming method according to claim 9, wherein: in step 4), the method further comprises a process of reclassifying the memory cells which are not verified according to the programming speed.
11. The memory programming method according to claim 9, wherein: in step 3), the voltage value of the programming voltage is higher than the voltage value of the initial programming voltage; in step 6), each time step 4) to step 5) are executed in a loop, the voltage value of the program voltage in step 5) is higher than the voltage value of the program voltage in step 5) in the previous loop.
12. The memory programming method according to claim 11, wherein: in step 6), the ratio of the voltage value of the programming voltage to the duration of the programming voltage in step 5) is a fixed value every time step 4) to step 5) are executed in a loop.
13. The memory programming method according to claim 1, wherein: in step 2), before classifying the memory cells which fail to be verified according to the programming speed, the method further comprises the step of executing the programming and verifying processes of the memory cells which fail to be verified for a specified number of times.
14. The memory programming method according to claim 1, wherein: the memory includes a NAND flash memory.
15. A memory programming device, characterized by: the method comprises the following steps:
the initial programming module is used for programming a memory cell to be programmed in the memory by adopting an initial programming voltage;
the verification module is used for verifying whether the programming of the memory unit is finished and classifying the memory units which do not pass the verification according to the programming speed;
and the reprogramming module is used for respectively reprogramming the memory cells which have different programming speeds and do not pass the verification by adopting different programming voltages.
16. The memory programming device according to claim 15, wherein: the verification module includes a program-pass verification unit verifying the memory cells using a program-pass verification voltage, determining the memory cells verified by the program-pass verification voltage as the memory cells verified by the program-pass verification voltage, and determining the memory cells not verified by the program-pass verification voltage as the memory cells not verified by the program-pass verification voltage; the programming speed verification unit classifies the programming speed of the memory cells which do not pass the verification by adopting at least one programming speed verification voltage.
17. The memory programming device according to claim 15, wherein: the reprogramming module includes:
a re-verifying unit for re-verifying whether the memory cell is programmed;
a reprogramming unit for respectively reprogramming the memory cells which have different programming speeds and have not passed the verification by using different programming voltages;
and the circulation judging unit is used for controlling the reprogramming unit and the re-verifying unit to circularly execute the re-programming and re-verifying processes until the count of the storage unit passing the verification is greater than a set value.
18. An electronic device, characterized in that: the method comprises the following steps:
a processor for implementing the memory programming method of any of claims 1-14;
an instruction memory coupled to the processor for storing instructions executable by the processor.
19. A computer-readable storage medium having stored thereon a computer program, characterized in that: the computer program, when executed by a processor, implements the memory programming method of any of claims 1-14.
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