KR20140024723A - Semiconductor memory device and operating method thereof - Google Patents

Semiconductor memory device and operating method thereof Download PDF

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Publication number
KR20140024723A
KR20140024723A KR1020120091201A KR20120091201A KR20140024723A KR 20140024723 A KR20140024723 A KR 20140024723A KR 1020120091201 A KR1020120091201 A KR 1020120091201A KR 20120091201 A KR20120091201 A KR 20120091201A KR 20140024723 A KR20140024723 A KR 20140024723A
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South Korea
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voltage
cells
fast
verification
program
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KR1020120091201A
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Korean (ko)
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임종순
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에스케이하이닉스 주식회사
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Publication of KR20140024723A publication Critical patent/KR20140024723A/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5628—Programming or writing circuits; Data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3454—Arrangements for verifying correct programming or for detecting overprogrammed cells
    • G11C16/3459—Circuits or methods to verify correct programming of nonvolatile memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/562—Multilevel memory programming aspects
    • G11C2211/5621—Multilevel programming verification

Abstract

A semiconductor memory device includes: a memory array including first memory cells for data storage and second memory cells for storing information of fast cells which have a threshold voltage increasing more rapidly than normal cells; and adjacent circuits which execute the main program loop including the main program command and the main program verification operation command in the first cells, and execute the main program loop in order to get the threshold voltage of the fast cells larger than that of normal cells based on the information of the fast cells while executing the main program verification operation command. [Reference numerals] (310) Check fast cell information; (322) Conduct a pre-program operation; (324) Generate a memory cell which is Vt >= Vpv1?; (332) Conduct a main program operation; (334) Conduct a verification operation of a normal cell based on Vpv1, Conduct a verification operation of a fast cell based on Vpv2(竊�pv1); (336) All normal cells Vt >= Vpv1, All fast cells Vt >= Vpv2?; (AA) Start; (BB,DD) No; (CC,EE) Yes; (FF) End

Description

Semiconductor memory device and operating method thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and an operation method thereof, and more particularly, to a semiconductor memory device performing a program operation and a verify operation and a method thereof.

In the semiconductor memory device, in the program verifying operation, the remaining bit lines except for the bit lines connected to the programmed cells are discharged from the precharge level to the ground through the cell source lines. At this time, the voltage of the source line is increased due to the resistance of the source line, which increases the body bias of the memory cell that is already programmed. Such noise of the source line reduces the sensing current of the cell and makes the threshold voltage of the memory cell to be verified higher than the actual threshold voltage. Although the threshold voltage of the actual cell is lower than the verification level due to the reduced sensing current, the verification level may pass to the program inhibit state by passing the verification level.

When the read operation is performed after the program operation is completed, there is no noise of the source line unlike when performing the program verification. Therefore, a relatively large sensing current flows as compared with the verification operation. Accordingly, an under program phenomenon occurs in which a cell having passed the verification step but having a threshold voltage lower than the actual verification level is determined not to be programmed in the reading step.

Due to this under program phenomenon, a problem arises in that the threshold voltage distribution of the memory cells becomes wider. As the density of memory cells increases, the interference between the memory cells increases and the cycling and retention margins decrease. This widens the threshold voltage distribution of the memory cells.

Therefore, it is necessary to narrow the width of the threshold voltage distribution of the memory cells.

The embodiment of the present invention can improve the characteristics of the threshold voltage distribution of the memory cells.

A method of operating a semiconductor memory device may include performing a main program loop including a main program operation and a main program verifying operation on memory cells, wherein the memory cells are provided with information of fast cells in which a threshold voltage increases faster than normal cells. Accordingly, the main program loop is implemented such that the threshold voltages of the fast cells are greater than those of the normal cells.

In example embodiments, in order to allow the threshold voltages of the fast cells to be greater than those of the normal cells, during the main program verify operation, the normal cells may perform a verify operation based on a first verify voltage and perform the verify operation. In this case, the verification operation is performed based on the second verification voltage higher than the first verification voltage.

In another embodiment, in order to make the threshold voltages of the fast cells larger than the normal cells, during the main program operation, a program inhibit voltage is applied to a bit line of the normal cells having a threshold voltage greater than or equal to a first verification voltage. A voltage lower than the program inhibit voltage is applied to a bit line of fast cells whose voltage is greater than or equal to the first verification voltage.

In another embodiment, in order to allow the threshold voltages of the fast cells to be greater than those of the normal cells, during the main program verifying operation, the verifying operation is performed based on first and second verifying voltages of the normal cells. The verification operation is performed on the fast cells based on second and third verification voltages. During the main program operation, a program inhibit voltage is applied to bit lines of normal cells having a threshold voltage greater than or equal to the second verification voltage. And applying a first voltage lower than the program inhibit voltage to the bit lines of the normal cells having a threshold voltage greater than or equal to the first verification voltage and less than the second verification voltage, and bit lines of fast cells having a threshold voltage greater than or equal to the third verification voltage. The program inhibit voltage is applied to the threshold voltage, and a threshold voltage is greater than or equal to the second verification voltage and less than the third verification voltage. Bit lines of the fast cell, and applies a second voltage lower than the program inhibit voltage.

In another embodiment, in order to increase the threshold voltages of the fast cells than the normal cells, during the main program operation, a program inhibit voltage is applied to the bit lines of the normal cells whose threshold voltage is greater than or equal to a second verification voltage. The first voltage lower than the program inhibit voltage is applied to the bit lines of the normal cells having the threshold voltage greater than or equal to the first verification voltage and less than the second verification voltage, and the bit lines of the fast cells having the threshold voltage greater than or equal to the second verification voltage. A second voltage lower than the program inhibit voltage is applied.

The semiconductor memory device includes a memory array including first memory cells for storing data and second memory cells for storing information of fast cells whose threshold voltage increases faster than normal cells of the memory cells; And performing a main program loop including a main program operation and a main program verify operation on the first memory cells, wherein during the main program verify operation, threshold voltages of the fast cells are higher than those of the normal cells according to the information of the fast cells. Peripheral circuitry that implements the main program loop to be larger.

In example embodiments, the peripheral circuit performs the verify operation on the basis of the first verify voltage for the normal cells during the main program verifying operation so that the threshold voltages of the fast cells are greater than the normal cells. The fast cells perform a verification operation based on the second verification voltage higher than the first verification voltage.

In another exemplary embodiment, the peripheral circuit may include a program prohibition voltage on bit lines of normal cells having a threshold voltage greater than or equal to a first verification voltage during the main program operation, so that the threshold voltages of the fast cells are greater than those of the normal cells. Is applied and a voltage lower than the program inhibit voltage is applied to the bit lines of the fast cells whose threshold voltage is greater than or equal to the first verification voltage.

In another exemplary embodiment, the peripheral circuit may be configured based on first and second verify voltages for the normal cells in the main program verify operation to increase the threshold voltages of the fast cells than the normal cells. The verification operation is performed, and the verification operation is performed on the fast cells based on second and third verification voltages. During the main program operation, program is prohibited in bit lines of normal cells having a threshold voltage greater than or equal to the second verification voltage. A fast voltage is applied, a first voltage lower than the program inhibit voltage is applied to the bit lines of the normal cells whose threshold voltage is greater than or equal to the first verification voltage and less than the second verification voltage, and the threshold voltage is greater than or equal to the third verification voltage. The program inhibit voltage is applied to a bit line of cells, and a threshold voltage is greater than or equal to the second verify voltage. 3 the verify voltage lower than the bit line of the fast cell, and applies a second voltage lower than the program inhibit voltage.

In another exemplary embodiment, the peripheral circuit prohibits program in the bit lines of the normal cells in which the threshold voltage is greater than or equal to the second verify voltage during the main program operation so that the threshold voltages of the fast cells are greater than those of the normal cells. A fast cell applying a voltage, applying a first voltage lower than the program inhibit voltage to a bit line of normal cells having a threshold voltage greater than or equal to a first verification voltage and less than the second verification voltage, and having a threshold voltage greater than or equal to the second verification voltage The second voltage lower than the program inhibit voltage is applied to the bit lines.

According to an exemplary embodiment of the present invention, an underprogram phenomenon of fast cells generated during a program verifying operation may be minimized by increasing the threshold voltages of the fast cells above the threshold voltages of the normal cells. Thus, the width of the threshold voltage distribution of the memory cells can be narrowed.

1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present invention.
2 is a conceptual diagram illustrating a method of operating a semiconductor memory device according to a first embodiment of the present invention.
3 is a flowchart for describing a method of operating the semiconductor memory device of FIG. 2.
4 is a flowchart for explaining a method for storing fast cell information.
5 is a conceptual diagram for describing a method of operating a semiconductor memory device according to a second exemplary embodiment of the present invention.
6 is a flowchart for describing a method of operating the semiconductor memory device of FIG. 5.
7 is a flowchart illustrating a method of operating a semiconductor memory device according to a third embodiment of the present invention.
8 is a flowchart illustrating a method of operating a semiconductor memory device according to a fourth embodiment of the present invention.
FIG. 9 is a diagram illustrating a change in threshold voltage distribution of memory cells when a method of operating a semiconductor memory device according to an exemplary embodiment of the present invention is used.

Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. However, the present invention is not limited to the embodiments described below, but may be implemented in various forms, and the scope of the present invention is not limited to the embodiments described below. It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.

1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 1, a semiconductor memory device according to an embodiment of the present invention includes a memory array 110 including main cells and flag cells, and peripheral circuits 120, 130, and 140. The peripheral circuit includes operation circuits 130 and 140 configured to perform program and verify operations of the main cells and flag cells, and control circuit 120 configured to control the operation circuits 130 and 140. In the case of a NAND flash memory device, the operation circuit includes a voltage supply circuit 130 and a page buffer 140.

The memory cells are divided into main cells and flag cells, which store general data in the main cells and state information of the semiconductor memory device in the flag cells. In an embodiment of the present invention, information of fast cells is stored in flag cells. Although described as a flag cell, information of fast cells may be stored in all memory cells except memory cells that store general data such as spare cells or redundancy cells.

The control circuit 120 outputs an internal command signal for performing a program operation or a verify operation in response to a command signal input through an input / output circuit from an external device, and controls the page buffer 140 according to the type of operation. The buffer control signals PB_SIGNALS and the voltage control signals VGSIGNALS for controlling the voltage supply circuit 130 are output.

The voltage supply circuit 130 selects the operating voltages (eg, Vpgm, Vpass, Vpv1 to Vpv3) necessary for the program operation and the verify operation of the memory cells in response to the voltage control signals VGSIGNALS of the control circuit 120. The cells feed into the connected word line. Such a voltage supply circuit may include a voltage generator circuit and a row decoder (not shown).

In response to the page buffer control signals PB_SIGNALS of the control circuit 120, the page buffer 140 selectively precharges the bit lines BL according to the input data for storing data in the memory cells. In order to read data from the memory cells, voltages of the bit lines BL are sensed.

For example, when program data (eg, '0' data) is input to the page buffer for storage in a memory cell, in a program operation, the page buffer is assigned to a program allowable voltage (eg, in the bit line of the memory cell where the program data is stored). Ground voltage). As a result, the threshold voltage of the memory cell is increased by the program voltage Vpgm applied to the word line) and the program permission voltage applied to the bit line in the program operation. When erase data (eg, '1' data) is input to the page buffer for storage in the memory cell, in a program operation, the page buffer may include a program prohibition voltage (eg, a power supply voltage) on a bit line of the memory cell in which the erase data is stored. ) Is applied. As a result, even if the program voltage Vpgm is applied to the word line in the program operation, the threshold voltage of the memory cell does not increase due to the program inhibit voltage applied to the bit line. As the threshold voltages are different from each other, different data can be stored in the memory cell.

In the verify operation, the page buffer 140 precharges all selected bit lines and discharges all unselected bit lines. When the verification voltages Vpv1 to Vpv3 are applied to the selected word line from the voltage supply circuit 130, the bit lines of the memory cells in which the data program is completed maintain the precharge state, and the memory lines of the memory cells in which the data program is not completed. The bit lines are discharged. The page buffer 140 senses a voltage change of the bit lines BL and latches data of memory cells corresponding to the sensing result.

In an embodiment of the present invention, in order to store information about fast cells whose threshold voltages increase faster than normal cells among the main cells, the control circuit 120 may perform a test program operation and a test program verification operation. 130 and the page buffer 140. Among the main cells, memory cells whose threshold voltage is greater than or equal to the verification voltage may be determined as fast cells.

As an embodiment, it is also possible to perform the test program operation and the test program verification operation a plurality of times and to determine the fast cell according to the result of the test operation of the plurality of test programs.

As a first embodiment, when the control circuit 120 performs the main program verify operation according to the fast cell information CELLINFO input from the page buffer 140, the normal cells of the main cells are based on the first verify voltage Vpv1. The verification operation is performed and the fast cells among the main cells control the voltage supply circuit 130 and the page buffer 140 to perform the verification operation based on the second verification voltage Vpv2 higher than the first verification voltage Vpv1. . In detail, the voltage supply circuit 130 and the page buffer 140 are controlled by outputting the voltage control signals VGSIGNALS and the page buffer control signals PBSIGNALS.

Therefore, since the threshold voltages of the fast cells are increased by the program operation than the normal cells, the threshold voltages of the fast cells may be prevented from being programmed due to the source line resistance.

On the other hand, since the verification operation is performed based on the first verification voltage Vpv1 and the second verification voltage Vpv2, the verification operation is performed more than when the verification operation is performed based only on the first verification voltage Vpv1. The time can be long.

To solve this problem, the control circuit 120 repeatedly performs the preprogram operation and the preprogram verify operation based on the first verify voltage Vpv1 in the main cells, and the threshold voltage of the main cells is the first verify voltage Vpv1. When the above-described memory cell occurs (hereinafter, referred to as a 1-bit pass time point), the voltage supply circuit 130 and the page buffer 140 are controlled to perform the main program operation and the main program verification operation.

As a second embodiment, the control circuit 120 performs a main program verification operation on the normal cells and the fast cells with the first verification voltage Vpv1 and then, according to the information CELLINFO of the fast cells during the next main program operation. The program inhibit voltage is applied to the bit lines of the normal cells having the threshold voltage greater than or equal to the first verify voltage Vpv1 and the voltage lower than the program inhibit voltage is applied to the bit lines of the fast cells whose threshold voltage is greater than or equal to the first verify voltage Vpv1. The supply circuit 130 and the page buffer 140 are controlled.

Accordingly, in the case of fast cells, even when the threshold voltage is greater than or equal to the verification voltage, the threshold voltage may be further increased by the program operation by applying a voltage lower than the program inhibit voltage to the bit line.

Meanwhile, the control circuit 120 controls the voltage supply circuit 130 and the page buffer 140 to perform such an operation after the memory cell having the threshold voltage greater than or equal to the first verification voltage Vpv1 is generated.

In a third embodiment, the control circuit 120 performs a verification operation on the basis of the first and second verification voltages Vpv1 and Vpv2 based on the information CELLINFO of the fast cells during the program verify operation. The fast cells control the voltage supply circuit 130 and the page buffer 140 to perform the verify operation based on the second and third verify voltages Vpv2 and Vpv3. In the next program operation, the control circuit 120 applies a program prohibition voltage to the bit lines of the normal cells whose threshold voltage is greater than or equal to the second verification voltage Vpv2, and the threshold voltage is greater than or equal to the first verification voltage Vpv1 and is verified by the second verification operation. The first voltage lower than the program inhibit voltage is applied to the bit lines of the normal cells that are less than the voltage Vpv2, and the program inhibit voltage is applied to the bit lines of the fast cells whose threshold voltage is greater than or equal to the third verify voltage Vpv3. The voltage supply circuit 130 and the page buffer 140 are controlled to apply a second voltage lower than the program inhibit voltage to the bit lines of the fast cells that are greater than or equal to the second verification voltage Vpv2 and less than the third verification voltage Vpv3.

As a fourth exemplary embodiment, the control circuit 120 applies a program inhibit voltage to bit lines of normal cells having a threshold voltage greater than or equal to the second verification voltage Vpv2 according to the information CELLINFO of the fast cells during a program operation. The first voltage lower than the program prohibition voltage is applied to the bit lines of the normal cells that are greater than or equal to the first verification voltage Vpv1 and less than the second verification voltage Vpv2, and the fast voltages of which the threshold voltage is greater than or equal to the second verification voltage Vpv2. A second voltage lower than the program inhibit voltage is applied to the bit line, and a third voltage lower than the second voltage is applied to the bit lines of the fast cells having a threshold voltage greater than or equal to the first verification voltage Vpv1 and less than the second verification voltage Vpv2. The voltage supply circuit 130 and the page buffer 140 are controlled to be applied.

The third embodiment and the fourth embodiment apply a double verify operation, which will be described in detail later.

2 is a conceptual diagram illustrating a method of operating a semiconductor memory device according to a first embodiment of the present invention, and FIG. 3 is a flowchart illustrating a method of operating the semiconductor memory device of FIG. 2.

Referring to FIG. 2, a program operation is performed by an incremental step pulse programming (ISPP) method before a 1-bit pass, but a verification operation is performed based on the same verification voltage for normal cells and fast cells. The verification voltage is denoted as the third verification voltage Vpv3, and the third verification voltage Vpv3 is the verification voltage of the highest voltage level during the 2-bit MLC program operation and the verification operation.

After one bit pass, the verify operation is performed based on the third verify voltage Vpv3 for the normal cells and the verify operation is performed based on the voltage Vpv3 * higher than the third verify voltage for the fast cells.

Extending this concept, the general verification operation is performed on other verification voltages during the MLC program operation (that is, the verification operation is performed with the same verification voltage for the normal cells and the fast cells), and the highest verification voltage (the nth In the case of performing the verify operation using the verify voltage, Vpv3 in the case of 2 bits, the verify operation is performed based on the n th verify voltage for the normal cells after the 1 bit pass, and a voltage higher than the n th verify voltage is applied for the fast cells. Verification can be performed as a reference.

This will be described in more detail.

In the method of operating a semiconductor memory device according to the first embodiment of the present invention, first, information of fast cells whose threshold voltage increases faster than normal cells is checked (310). Fast cell information may be stored in flag cells among memory cells. Therefore, a read operation is performed to read fast cell information from flag cells. A method of storing fast cell information will be described again with reference to FIG. 4.

Next, a preprogram loop 320 including a preprogram operation and a preprogram verify operation based on the first verify voltage Pv1 is performed on the memory cells. This is to further reduce the time required for the verify operation by performing the verify operation on the fast cells after the 1-bit pass time with a different verify voltage than the normal cells.

The preprogram operation is performed (322), and the preprogram verify operation is performed using the first verify voltage Vpv1 to determine whether a memory cell having a threshold voltage Vt greater than or equal to the first verify voltage Vpv1 is generated (324). When the memory cell having the threshold voltage Vt equal to or greater than the first verification voltage Vpv1 does not occur, the program voltage is increased by the step voltage (326), and then the preprogram operation is performed again.

When a memory cell having a threshold voltage Vt equal to or greater than the first verification voltage Vpv1 occurs, the main program operation includes a main program verification operation based on the first verification voltage Vpv1 and the second verification voltage Vpv2. The main program loop 330 is executed.

The main program operation is performed (332), and the verification operation is performed based on the first verification voltage Vpv1 for the normal cells according to the information of the fast cells, and the second higher than the first verification voltage Vpv1 for the fast cells. The verification operation is performed based on the verification voltage Vpv2 (334). If the threshold voltages of all the normal cells are greater than or equal to the first verification voltage Vpv1 and the threshold voltages of all the fast cells are the second verification voltage Vpv2 (336), the operation is terminated when the threshold voltages are greater than or equal to the threshold voltage. When there is a normal cell lower than the first verify voltage Vpv1 or a fast cell whose threshold voltage is lower than the second verify voltage Vpv2, the program voltage is increased by the step voltage (338), and the main program operation is performed again.

Therefore, since the threshold voltages of the fast cells increase more by the program operation than the normal cells, the threshold voltages of the fast cells may be prevented from being programmed due to the source line resistance.

4 is a flowchart for explaining a method for storing fast cell information.

Referring to FIG. 4, a test operation is performed on the memory cells (410), and information about fast cells whose threshold voltage increases faster than normal cells among the memory cells is stored (420).

For the test operation, first, a test program operation is performed on the memory cells (412). In operation 414, the verification operation is performed based on the preset verification voltage. Memory cells whose threshold voltage is greater than or equal to the verify voltage among the main cells are identified as fast cells and store fast cell information in the flag cell (420). Memory cells whose threshold voltage is less than the verify voltage are identified as normal cells.

In an embodiment, the fast cell may be determined after performing a test program operation and a test program verification operation a plurality of times during the test operation.

5 is a conceptual diagram illustrating a method of operating a semiconductor memory device according to a second embodiment of the present invention, and FIG. 6 is a flowchart illustrating a method of operating the semiconductor memory device of FIG. 5.

Referring to FIG. 5, after performing a verification operation on the normal cells and the fast cells with the same verification voltage PV3, a program prohibition voltage (eg, Vcc) is applied to the bit lines of the normal cells whose threshold voltage is greater than or equal to the verification voltage. A voltage lower than the program prohibition voltage is applied to the bit lines of the fast cells whose voltage is greater than or equal to the verify voltage. Therefore, the threshold voltage may be increased for the fast cells by the next program operation.

Referring to FIG. 6, first, a check 310 of fast cell information of FIG. 3 and a 320 of a preprogram loop are performed. In an embodiment, step 320 may be omitted.

Next, a main program loop including a main program operation and a main program verify operation based on the first verify voltage Vpv1 is performed to the memory cells.

In operation 620, it is checked whether the threshold voltage Vt of all the memory cells is greater than or equal to the first verification voltage Vpv1 (630). If abnormal, the operation ends. When a memory cell having a threshold voltage Vt less than the first verification voltage Vpv1 exists, a program prohibition voltage (eg, Vcc) is applied to bit lines of normal cells having the threshold voltage Vt greater than or equal to the first verification voltage Vpv1. A voltage lower than the program inhibit voltage is applied to the bit lines of the fast cells having the threshold voltage Vt equal to or greater than the first verification voltage Vpv1 (640). After the program voltage is increased by the step voltage (650), the main program operation is performed again.

Accordingly, in the case of fast cells, even when the threshold voltage rises above the verification voltage, the threshold voltage may be increased by the program operation by applying a voltage lower than the program inhibit voltage to the bit line.

7 is a flowchart illustrating a method of operating a semiconductor memory device according to a third embodiment of the present invention.

Referring to FIG. 7, after a 1-bit pass point (ie, after step 320), a main program operation is performed on memory cells and a main program verification operation based on the first to third verification voltages Vpv1 to Vpv3. Run the main program loop it contains.

That is, the main program operation is performed (710), the verification operation is performed based on the first and second verification voltages Vpv1 and Vpv2 for the normal cells according to the information of the fast cells, and the second and the second for the fast cells. 3 The verification operation is performed based on the verification voltages Vpv2 and Vpv3 (720).

If the threshold voltages of all the normal cells are greater than or equal to the second verification voltage Vpv2 and the threshold voltages of all the fast cells are the third verification voltage Vpv3 (730), the operation is terminated when the threshold voltages are greater than or equal to the threshold voltage. In the case where a normal cell lower than the second verify voltage Vpv2 or a fast cell whose threshold voltage is lower than the third verify voltage Vpv3 exists, the bit line voltage is set as follows in the next program operation.

The program inhibit voltage (eg, Vcc) is applied to the bit lines of the normal cells having the threshold voltage greater than or equal to the second verification voltage Vpv2, and the threshold voltage is greater than the first verification voltage Vpv1 and less than the second verification voltage Vpv2. The first voltage lower than the program inhibit voltage is applied to the bit lines of the cells, the program inhibit voltage is applied to the bit lines of the fast cells having a threshold voltage greater than or equal to the third verify voltage Vpv3, and the threshold voltage is the second verify voltage Vpv2. ) And a second voltage lower than the program inhibit voltage is applied to the bit lines of the fast cells that are greater than or equal to and less than the third verification voltage Vpv3 (740).

Then, the program voltage is increased by the step voltage (750), and the main program operation is performed again.

A method of operating the semiconductor memory device according to the third embodiment of the present invention and the method of operating the semiconductor memory device according to the fourth embodiment to be described with reference to FIG. 8 use a double verify operation.

The double verification operation is a method of additionally performing a verification operation based on a second verification voltage lower than the first verification voltage in a general verification operation. As a result of performing the verification operation based on the second verification voltage, the threshold voltage is greater than or equal to the second verification voltage. The memory cells set the bit line voltage to a voltage lower than the program inhibit voltage during the next program operation. As a result, the width of the threshold voltage distribution of the memory cells can be narrowed.

Therefore, according to the third embodiment of the present invention, in addition to the effect of the first embodiment, the width of threshold voltage distribution of the memory cells may be additionally reduced.

8 is a flowchart illustrating a method of operating a semiconductor memory device according to a fourth embodiment of the present invention.

Referring to FIG. 8, after a 1-bit pass point (after step 320), the memory cells include a main program operation and a main program verify operation based on the first and second verify voltages Vpv1 and Vpv2. Run the main program loop.

That is, the main program operation is performed in operation 810, and the verification operation is performed based on the first and second verification voltages Vpv1 and Vpv2 for the normal cells and the fast cells in operation 820.

If the threshold voltages of all the memory cells are greater than or equal to the second verification voltage Vpv2 (830), the operation is terminated when the threshold voltages are greater than or equal to the second verification voltage Vpv2. In the next program operation, set the bit line voltage as follows:

The program inhibit voltage (eg, Vcc) is applied to the bit lines of the normal cells having the threshold voltage greater than or equal to the second verification voltage Vpv2, and the threshold voltage is greater than the first verification voltage Vpv1 and less than the second verification voltage Vpv2. A first voltage lower than the program inhibit voltage is applied to the bit lines of the cells, and a second voltage lower than the program inhibit voltage is applied to the bit lines of fast cells having a threshold voltage greater than or equal to the second verification voltage Vpv2 (840). In addition, a third voltage lower than the second voltage may be applied to the bit lines of the fast cells having a threshold voltage greater than or equal to the first verification voltage Vpv1 and less than the second verification voltage Vpv2.

Then, the program voltage is increased by the step voltage (850), and the main program operation is performed again.

Therefore, according to the fourth embodiment of the present invention, in addition to the effect of the second embodiment, the width of threshold voltage distribution of the memory cells may be additionally reduced.

FIG. 9 is a diagram illustrating a change in threshold voltage distribution of memory cells when a method of operating a semiconductor memory device according to an exemplary embodiment of the present invention is used.

Referring to FIG. 9, the threshold voltage distribution (dotted line) of the memory cells in the case of using the method of operating the semiconductor memory device according to the exemplary embodiment of the present invention is higher than the threshold voltage distribution (solid line) of the memory cells in the other case. It can be seen that the width of is narrower by A.

The embodiments of the present invention described above are not only implemented by the apparatus and method but may be implemented through a program for realizing the function corresponding to the configuration of the embodiment of the present invention or a recording medium on which the program is recorded, The embodiments can be easily implemented by those skilled in the art from the description of the embodiments described above.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, It belongs to the scope of right.

110: memory array
120: control circuit
130: voltage supply circuit
140: page buffer

Claims (25)

Implementing a main program loop comprising a main program operation and a main program verify operation on the memory cells,
And executing the main program loop such that the threshold voltages of the fast cells are greater than the normal cells according to information of the fast cells in which the threshold voltages of the memory cells increase faster than those of the normal cells.
The method of claim 1, wherein the threshold voltages of the fast cells are greater than those of the normal cells.
In the main program verifying operation, the verifying operation is performed based on a first verifying voltage for the normal cells, and the verifying operation is performed based on the second verifying voltage higher than the first verifying voltage for the fast cells. Method of operation of a semiconductor memory device.
The method of claim 1, wherein the threshold voltages of the fast cells are greater than those of the normal cells.
In the main program operation, a program inhibit voltage is applied to a bit line of normal cells having a threshold voltage greater than or equal to a first verify voltage, and a voltage lower than the program inhibit voltage is applied to a bit line of fast cells whose threshold voltage is greater than or equal to the first verify voltage. An operating method of an applied semiconductor memory device.
The method of claim 1, wherein the threshold voltages of the fast cells are greater than those of the normal cells.
In the main program verifying operation, a verifying operation is performed based on first and second verifying voltages with respect to the normal cells, and a verifying operation is performed with reference to second and third verifying voltages with respect to the fast cells.
In the main program operation, a program inhibit voltage is applied to the bit lines of the normal cells whose threshold voltage is greater than or equal to the second verification voltage, and bit lines of the normal cells whose threshold voltage is greater than or equal to the first verification voltage and less than the second verification voltage. Applies a first voltage lower than the program inhibit voltage, applies the program inhibit voltage to bit lines of fast cells having a threshold voltage equal to or greater than the third verify voltage, and applies a threshold voltage equal to or greater than the second verify voltage. And applying a second voltage lower than the program inhibit voltage to bit lines of fast cells that are less than a verification voltage.
The method of claim 1, wherein the threshold voltages of the fast cells are greater than those of the normal cells.
In the main program operation, a program inhibit voltage is applied to the bit lines of the normal cells whose threshold voltage is greater than or equal to the second verify voltage, and the bit lines of the normal cells whose threshold voltage is greater than or equal to the first verify voltage and less than the second verify voltage. And applying a first voltage lower than a program inhibit voltage and applying a second voltage lower than the program inhibit voltage to a bit line of fast cells having a threshold voltage equal to or greater than the second verify voltage.
6. The method according to any one of claims 2 to 5,
Before performing the main program loop, performing a preprogram loop on the memory cells including a preprogram operation and a preprogram verify operation based on the first verify voltage;
And executing the main program loop when a memory cell having a threshold voltage equal to or greater than the first verification voltage is generated.
The method according to claim 6,
And performing a test operation on the memory cells to confirm the stored information of the fast cells before performing the preprogram loop.
8. The method of claim 7, wherein the performing of the test operation to store fast cell information
Performing a test program operation and a test program verification operation on the memory cells; And
And identifying and storing memory cells having a threshold voltage equal to or greater than a test program verification voltage as a fast cell as a result of the test program verification operation.
The method of claim 8, wherein the fast cell is determined after the test program operation and the test program verification operation are performed a plurality of times.
The method of claim 8, wherein the information of the fast cells
A method of operating a semiconductor memory device stored in a spare cell, a redundancy cell, or a flag cell.
The method of claim 3, wherein the first verification voltage is
A method of operating a semiconductor memory device, the verification voltage having the highest magnitude among verification voltages during a 2-bit MLC program operation.
6. The method of claim 4, wherein, in the main program operation, a third voltage lower than the second voltage is applied to a bit line of fast cells having a threshold voltage greater than or equal to the first verification voltage and less than the second verification voltage. A method of operating a semiconductor memory device.
A memory array including first memory cells for storing data and second memory cells for storing information of fast cells whose threshold voltage increases faster than normal cells of the memory cells; And
Implement a main program loop including a main program operation and a main program verify operation to the first memory cells, wherein during the main program verify operation, threshold voltages of the fast cells are higher than those of the normal cells according to the information of the fast cells. And a peripheral circuit which performs the main program loop to increase.
The circuit of claim 13, wherein the peripheral circuit is
In order to increase the threshold voltage of the fast cells than the normal cells,
In the main program verifying operation, the verifying operation is performed based on a first verifying voltage for the normal cells, and the verifying operation is performed based on the second verifying voltage higher than the first verifying voltage for the fast cells. Semiconductor memory device.
The circuit of claim 13, wherein the peripheral circuit is
In order to increase the threshold voltage of the fast cells than the normal cells,
In the main program operation, a program inhibit voltage is applied to a bit line of normal cells having a threshold voltage greater than or equal to a first verify voltage, and a voltage lower than the program inhibit voltage is applied to a bit line of fast cells whose threshold voltage is greater than or equal to the first verify voltage. A semiconductor memory device to be applied.
The circuit of claim 13, wherein the peripheral circuit is
In order to increase the threshold voltage of the fast cells than the normal cells,
In the main program verifying operation, a verifying operation is performed based on first and second verifying voltages with respect to the normal cells, and a verifying operation is performed with reference to second and third verifying voltages with respect to the fast cells.
In the main program operation, a program inhibit voltage is applied to the bit lines of the normal cells whose threshold voltage is greater than or equal to the second verification voltage, and bit lines of the normal cells whose threshold voltage is greater than or equal to the first verification voltage and less than the second verification voltage. Applies a first voltage lower than the program inhibit voltage, applies the program inhibit voltage to bit lines of fast cells having a threshold voltage equal to or greater than the third verify voltage, and applies a threshold voltage equal to or greater than the second verify voltage. And applying a second voltage lower than the program inhibit voltage to bit lines of fast cells that are less than a verification voltage.
The circuit of claim 13, wherein the peripheral circuit is
In order to increase the threshold voltage of the fast cells than the normal cells,
In the main program operation, a program inhibit voltage is applied to the bit lines of the normal cells whose threshold voltage is greater than or equal to the second verify voltage, and the bit lines of the normal cells whose threshold voltage is greater than or equal to the first verify voltage and less than the second verify voltage. And applying a first voltage lower than a program prohibition voltage and applying a second voltage lower than the program prohibition voltage to bit lines of fast cells having a threshold voltage greater than or equal to the second verification voltage.
18. The method according to any one of claims 14 to 17,
The peripheral circuit
Before the main program loop, the memory cells are subjected to a preprogram loop including a preprogram operation and a preprogram verify operation based on the first verify voltage.
And performing a main program loop when a memory cell having a threshold voltage equal to or greater than the first verification voltage is generated.
19. The circuit of claim 18, wherein the peripheral circuit is
And performing a test operation on the memory cells to confirm the stored information of the fast cells before performing the preprogram loop.
20. The circuit of claim 19, wherein the peripheral circuit is
When storing the fast cell information by performing the test operation,
And performing a test program operation and a test program verification operation on the memory cells, and identifying and storing the memory cells having a threshold voltage equal to or more than a test program verification voltage as fast cells.
The circuit of claim 20, wherein the peripheral circuit is
And determining the fast cell after performing the test program operation and the test program verification operation a plurality of times.
The method of claim 13, wherein the second memory cells
A semiconductor memory device including spare cells, redundancy cells, or flag cells.
The peripheral circuit of claim 15, wherein the peripheral circuit is
And applying a verification voltage having the highest magnitude among verification voltages during a 2-bit MLC program operation as the first verification voltage.
18. The circuit of claim 16 or 17, wherein the peripheral circuit is
And applying a third voltage lower than the second voltage to bit lines of fast cells having a threshold voltage greater than or equal to the first verification voltage and less than the second verification voltage during the main program operation.
The peripheral circuit includes a voltage supply configured to supply a verification voltage to the memory cells,
The voltage supply unit is configured to supply a first verify voltage to the normal cells and a second verify voltage higher than the first verify voltage to the fast cells during the main program verify operation.
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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160116899A (en) * 2015-03-31 2016-10-10 에스케이하이닉스 주식회사 Semiconductor memory device including plurality of memory cells and operating method thereof
KR20170032110A (en) * 2015-09-14 2017-03-22 에스케이하이닉스 주식회사 Semiconductor memory device and operating method thereof
KR20170052034A (en) * 2015-11-03 2017-05-12 에스케이하이닉스 주식회사 Semiconductor memory device and operating method thereof
KR20170104839A (en) * 2016-03-08 2017-09-18 에스케이하이닉스 주식회사 Semiconductor memory device and operating method thereof
US9905304B2 (en) 2015-09-03 2018-02-27 SK Hynix Inc. Memory system and program operation method based on program speed information
CN114267399A (en) * 2020-09-16 2022-04-01 爱思开海力士有限公司 Memory device and operating method thereof

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20160116899A (en) * 2015-03-31 2016-10-10 에스케이하이닉스 주식회사 Semiconductor memory device including plurality of memory cells and operating method thereof
US9905304B2 (en) 2015-09-03 2018-02-27 SK Hynix Inc. Memory system and program operation method based on program speed information
KR20170032110A (en) * 2015-09-14 2017-03-22 에스케이하이닉스 주식회사 Semiconductor memory device and operating method thereof
KR20170052034A (en) * 2015-11-03 2017-05-12 에스케이하이닉스 주식회사 Semiconductor memory device and operating method thereof
KR20170104839A (en) * 2016-03-08 2017-09-18 에스케이하이닉스 주식회사 Semiconductor memory device and operating method thereof
CN114267399A (en) * 2020-09-16 2022-04-01 爱思开海力士有限公司 Memory device and operating method thereof

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