TWI635499B - Method for programming non-volatile memory and memory system - Google Patents

Abstract

A method of programming non-volatile memory and a memory system. Each memory cell of a plurality of memory cells of the non-volatile memory has at least 2 bits of data. This method includes the following steps. At least one programming pulse is provided to program a target memory cell of the plurality of memory cells. At least one programming verify pulse is provided to verify if the target memory cell is programmed successfully. Determine whether the threshold voltage of the target memory cell is greater than or equal to the program verify voltage. When the threshold voltage of the target memory cell is greater than or equal to the program verify voltage, the target memory cell is set to be successfully programmed. Next, a repeated verification procedure is performed on the successfully programmed memory cells. The re-verification procedure includes determining whether the threshold voltage of the target memory cell is greater than or equal to the re-verification voltage.

Description

Method for programming non-volatile memory and memory system

This invention relates to a non-volatile memory, and more particularly to a method and memory system for programming a non-volatile memory.

In recent years, non-volatile memory has been widely used in various electronic devices such as personal computers, notebook computers, smart phones, and tablets. Non-volatile memory includes a memory cell array. The volume of non-volatile memory is getting smaller and smaller, and more bits are stored in a memory cell to increase the density of the memory. Multi-level cell (MLC) technology is used to increase memory density.

According to quantum mechanics, the smaller the volume of memory, the greater the influence of quantum in memory. The noise fluctuation when reading the memory cells of the memory will affect the reliability of the memory reading.

Therefore, there is a need for a method of programming non-volatile memory and a memory system to reduce the effects of noise fluctuations when reading memory cells of a memory.

The present invention relates to a method of programming a non-volatile memory and a memory system. Through the present invention, a re-verification pulse is applied to the memory cells of the programmed non-volatile memory, and a reprogramming pulse is applied to a portion of the target memory cells in the programmed memory cell to program the target memory cells and improve these The threshold voltage of the target memory cell. The critical voltage distribution including these target memory cells will be shortened and become tighter, which can reduce the influence of noise fluctuations when reading the memory cells of the memory.

According to one aspect of the invention, a method of programming non-volatile memory during programming is presented. The volatile memory includes a plurality of memory cells. Each of the memory cells of each of the memory cells stores at least 2 bits of data. The method includes the following steps. At least one programming pulse is provided to program a target memory cell of the memory cells. At least one programming verify pulse is applied to the target memory cell. In the case that a threshold voltage of the target memory cell is greater than or equal to a program verify voltage, the target memory cell is set to be successfully programmed. And in the case that the target memory cell is set to be successfully programmed, performing a re-verification operation on the target memory cell, the re-verification operation including applying at least one re-verification pulse to the target memory cell.

In accordance with another aspect of the invention, a method of programming non-volatile memory during programming is presented. The volatile memory includes a plurality of memory cells. Each of the memory cells of each of the memory cells stores at least 2 bits of data. The method includes the following steps. At least one programming pulse is provided. At least one programming verify pulse is provided. Enable a programming success signal. And providing at least one re-authentication pulse after enabling the programming success signal.

In order to better understand the above and other aspects of the present invention, the following detailed description of the embodiments and the accompanying drawings

20‧‧‧ memory system

202‧‧‧ Controller

204‧‧‧Non-volatile memory array

S302~S324‧‧‧ Process steps

400, 418‧‧‧ voltage level

402‧‧‧Programming pulse

404‧‧‧Program verification pulse

406‧‧‧Programming success signal

408‧‧‧Enable re-verification operation signal

410‧‧‧Revalidation pulse

412‧‧‧Reprogramming pulse

414‧‧‧Complete the programming verification signal

PV, PV1, PV2, PV3‧‧‧ programming verification voltage

Vt‧‧‧ threshold voltage

W1, W2, W3, W1', W2', W3'‧‧‧ memory window

FIG. 1A is a schematic diagram showing a threshold voltage distribution of a multi-level memory cell according to an embodiment of the invention.

FIG. 1B is a schematic diagram showing a threshold voltage distribution of a multi-level memory cell according to an embodiment of the invention.

FIG. 1C is a schematic diagram showing noise fluctuations when reading a memory cell according to an embodiment of the invention.

2 is a block diagram of a memory system in accordance with an embodiment of the present invention.

3 is a flow chart of a method of programming non-volatile memory in accordance with an embodiment of the present invention.

FIG. 4 is a diagram showing waveforms of signals according to an embodiment of the invention.

The various embodiments are described in detail below, however, the examples are intended to be illustrative only and not to limit the scope of the invention. Further, the drawings in the embodiments omits some of the elements to clearly show the technical features of the present invention. The same reference numerals will be used in the drawings to refer to the same or the like.

Please refer to FIG. 1A , which illustrates a schematic diagram of a threshold voltage distribution of a multi-level memory cell according to an embodiment of the invention. In this example, as shown in FIG. 1A, each memory cell of a memory array stores 2 bits of data, and each multi-level storage The unit has four logical states, namely "11", "10", "00" and "01", to indicate that each memory cell has 2 bits of data. In this example, the verify voltage PV1 is programmed to determine the low boundary of the threshold voltage distribution of the logic state "10." Similarly, the program verify voltages PV2 and PV3 are used to determine the low boundary of the threshold voltage distribution of the logic states "00" and "01", respectively. The area between the high boundary of the threshold voltage distribution of the logic state "11" and the low boundary of the threshold voltage distribution of the logic state "10" is defined as a memory window W1. The area between the high boundary of the threshold voltage distribution of the logic state "10" and the low boundary of the threshold voltage distribution of the logic state "00" is defined as the memory window W2. The area between the high boundary of the threshold voltage distribution of the logic state "00" and the low boundary of the threshold voltage distribution of the logic state "01" is defined as the memory window W3.

Please refer to FIG. 1B , which illustrates a schematic diagram of a threshold voltage distribution of a multi-level memory cell according to an embodiment of the invention. Because of the random telegraph noise (RTN) characteristic of the memory cell, the threshold voltage distribution of the logic state "10" has a "tail" distribution lower than the program verification voltage PV1, and the logic states "00" and "01" The threshold voltage distribution also has a "tail" distribution below the programmed verify voltages PV2 and PV3, respectively. The noise variation of the memory cell causes the threshold voltage distribution to have such an extra tail distribution, and the "tail" of each threshold voltage distribution is shaded. The "tail" of the threshold voltage distribution narrows the memory windows W1, W2, and W3. The widths of the memory windows W1', W2', and W3' in Fig. 1B are smaller than the widths of the memory windows W1, W2, and W3 in Fig. 1A, respectively. The memory window W1' is a high boundary of the threshold voltage distribution of the logic state "11" in the 1B diagram and a logic state having a "tail" The region between the low boundaries of the critical voltage distribution of "10". The memory window W2' is an area between the high boundary of the threshold voltage distribution of the logic state "10" in the first diagram BB and the low boundary of the threshold voltage distribution of the logic state "00" having the "tail". The memory window W3' is an area between the high boundary of the threshold voltage distribution of the logic state "00" in the first diagram BB and the low boundary of the threshold voltage distribution of the logic state "01" having the "tail".

FIG. 1C is a schematic diagram showing the noise variation in the memory cell of the "tail" portion of the threshold voltage distribution in FIG. 1B according to an embodiment of the present invention. When the memory cell is read for the first time, the threshold voltage of the memory cell is smaller than the program verify voltage PV, but when the memory cell is read for the tenth time, the threshold voltage of the memory cell is greater than the program verify voltage PV. That is, the threshold voltage of the memory cell located in the "tail" portion is sometimes smaller than the program verify voltage PV, and sometimes greater than the program verify voltage PV. There is a great change in the threshold voltage of the memory cell, and noise fluctuations can be observed in the electrical characteristics of the memory cell. The noise variation affects the width of the memory window.

2 is a block diagram of a memory system 20 in accordance with an embodiment of the present invention. The memory system includes a controller 202 and a non-volatile memory array 204. The non-volatile memory array 204 includes a plurality of memory blocks, and each memory block includes a plurality of memory pages. Each memory page includes a plurality of memory cells. For example, the non-volatile memory array 204 is a read-only memory (ROM), a programmable read-only memory (PROM), and an electrically rewritable read-only memory ( Modem alterable read only memory, EAROM), erased programmable read only Erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM) or any type of two-dimensional and three-dimensional flash memory.

The controller 202 is coupled to the non-volatile memory array 204. For example, the controller 202 can be, for example, by using a wafer, a circuit block within the wafer, a firmware circuit, a circuit board containing a plurality of electronic components and wires, or a storage medium storing a complex array of code. The implementation can also be implemented by executing a corresponding software, firmware or program by an electronic device such as a computer system, an embedded system, a handheld device, or a server. The controller 202 is configured to control the operation mode of the non-volatile memory array 204 in response to a partial external command from an interface (not shown in FIG. 2) via a bus. For example, the interface is an input/out interface. The operation mode is one of the programming (write) mode, the read mode, and the erase mode.

Controller 202 provides at least one programming pulse to program the memory cells of non-volatile memory array 204 and provides at least one program verify pulse to verify that the programmed memory cell is programming successful. For example, in FIGS. 1A and 1B, the program verify voltage PV3 is used to verify whether the memory cell that should be programmed to the logic state "01" is programmed successfully. The program verify voltage PV2 is used to verify that the memory cell that should be programmed to logic state "00" is programmed successfully. The program verify voltage PV1 is used to verify that the memory cell that should be programmed to the logic state "10" is programmed successfully.

Each memory cell of the non-volatile memory array 204 stores 2-bit data, and each memory cell has four logic states as an example, such as FIG. 1A and FIG. 1B. Shown. In a programming operation, when a memory cell that should be programmed into a logic state "10" is programmed to a logic state "11", the memory cell is set to be unsuccessful in programming or programming failure. Similarly, when a memory cell that should be programmed to logic state "00" is programmed to logic state "11" or logic state "10", this memory cell is set to be unsuccessful in programming. When a memory cell that should be programmed to logic state "01" is programmed to logic state "11", logic state "10", or logic state "00", this memory cell is set to be unsuccessful in programming.

Referring to FIG. 3, a flow chart of a method of programming non-volatile memory in accordance with an embodiment of the present invention is shown. A flowchart of a method of programming non-volatile memory illustrated in FIG. 3 can be applied to the memory system 20 as shown in FIG. In order to clearly explain the operation of the above various elements and the method of programming the non-volatile memory of the embodiment of the present invention, the following will be described in detail with reference to the flowchart of FIG. However, those skilled in the art to which the present invention pertains can understand that the method of the embodiment of the present invention is not limited to the memory system 20 of FIG. 2, nor is it limited to the steps of the flowchart of FIG. order.

Please refer to Figures 2, 3 and 4. FIG. 4 is a diagram showing waveforms of signals according to an embodiment of the invention. According to an embodiment of the present invention, in step S302, the controller 202 receives a program operation instruction from an interface to change the operation mode of the non-volatile memory array 204 to the programming mode, and starts a program verify operation. The program verify operation includes programming a target memory cell of the memory cell of the non-volatile memory array 204 and verifying whether the target memory cell is successfully programmed. The operations of the following steps S304 to S324 are all performed during the programming operation.

In step S304, the controller 202 provides at least one programming pulse (for example, the pulse 402 of FIG. 4) to program the target memory cell of the memory cell of the non-volatile memory array 204, and then, in step S306, the controller 202 provides at least one. A verify pulse (e.g., pulse 404 of FIG. 4) is programmed to the target memory cell to verify that the programmed target memory cell was successfully programmed. That is, at least one program verify pulse is applied to the target memory cell to verify that the programmed target memory cell is successfully programmed. Next, in step S308, the controller 202 determines whether the threshold voltage of the target memory cell is greater than or equal to a program verify voltage PV. In an embodiment of the invention, controller 202 may provide an erase pulse to erase memory cells of volatile memory array 204 prior to providing at least one programming voltage to program the target memory cell.

When the threshold voltage of the target memory cell is less than the program verification voltage PV (the determination result of step S308 is NO), step S310 is performed. In step S310, the controller 202 verifies whether the number of times at least one programming voltage (eg, the pulse 402 of FIG. 4) is provided is equal to a programmed number of times. When the number of times at least one programming voltage is supplied is less than the number of programming, step S304 is performed again. When the number of times at least one programming voltage is supplied is equal to the number of programming, step S312 is performed. In step S312, the controller 202 sets the target memory cell to be unsuccessful in programming.

When the threshold voltage of the target memory cell is greater than or equal to the program verify voltage PV (YES in step S308), step S314 is performed. In step S314, the controller 202 enables a programming success signal (such as the signal 406 of FIG. 4) to set the target memory cell to be successfully programmed. That is, in the case where the threshold voltage of the target memory cell is greater than or equal to the program verify voltage, the target memory cell is set to be programmed. Gong. After step S314, in step S316, the controller 202 enables a re-authentication operation on the target memory cell. The re-verification operation includes applying at least one re-verification pulse to the target memory cell to determine whether the threshold voltage of the target memory cell is greater than or equal to the re-verification voltage. In step S318, the controller provides at least one re-verification pulse (for example, pulse 410 of FIG. 4) to the target memory cell to determine whether the threshold voltage of the target memory cell is greater than or equal to a program verify voltage. In step S320, the controller 202 determines whether the threshold voltage of the target memory cell is greater than or equal to the program verify voltage.

When the threshold voltage of the target memory cell is greater than or equal to the program verify voltage (YES in step S320), step S322 is performed. At step S322, the controller 202 verifies whether the number of times at least one re-verification pulse (e.g., the pulse 410 of FIG. 4) is provided is equal to the number of re-verifications. When the number of times at least one re-verification pulse is supplied is less than the number of re-verifications (the determination result of step S322 is NO), step S318 is performed again. When the number of times at least one re-verification pulse is supplied is equal to the number of re-verifications (YES in step S322), the flow is ended and the controller 202 ends the programming operation of the non-volatile memory array 204.

When the threshold voltage of the target memory cell is less than the re-verification voltage (the determination result of step S320 is NO), step S324 is performed. At step S324, controller 202 provides a reprogramming pulse (e.g., pulse 412 of FIG. 4) to program the target memory cell. Further, the re-verification operation further includes providing a reprogramming pulse to program the target memory cell if the threshold voltage of the target memory cell is less than the re-verification voltage. Wherein the amplitude of the reprogramming pulse is greater than the amplitude of the at least one programming pulse. That is, the reprogramming pulse has a difference ΔV with at least one programming pulse. In this embodiment, The amplitude of the verify pulse is equal to the amplitude of the program verify pulse. In other embodiments of the invention, the amplitude of the re-verification pulse may be greater or less than the amplitude of the programming verify pulse.

In the present invention, the number of re-verifications may be a positive integer, such as 1, 2, 5, and the like. For example, the number of revalidation is set to 5 times. When the target memory cell of the non-volatile memory array 204 is set to be programmed successfully, the controller 202 provides a re-verification pulse to the target memory cell to determine whether the threshold voltage of the target memory cell is greater than or equal to the re-verification voltage. This is the first time a re-verification pulse is provided. When the threshold voltage of the target memory cell is greater than or equal to the re-verification voltage, the controller 202 again provides a re-verification pulse to the target memory cell, and determines whether the threshold voltage of the target memory cell is greater than or equal to the re-verification voltage. This provides a second re-verification pulse. After providing the re-verification pulse to the target memory cell twice, when the threshold voltage of the target memory cell is less than the re-verification voltage, the controller 202 provides a reprogramming pulse to the target memory cell to program the target memory cell, and raises the threshold voltage of the target memory cell. . In this example, the re-verification pulse is only provided twice, not 5 times the number of re-verifications. That is, after providing the re-verification pulse to the target memory cell and determining that the threshold voltage of the target memory cell is less than the re-verification voltage, regardless of whether the number of times of providing the re-verification pulse is equal to the number of re-verifications 5, the controller 202 provides a re-programming pulse to The target memory cell programs the target memory cell and raises its threshold voltage, and ends the entire process.

In summary, when the threshold voltage of the target memory cell is greater than or equal to the re-verification voltage, and the re-verification frequency is greater than 1, the controller 202 continues to provide the re-verification voltage to verify whether the threshold voltage of the target memory cell is greater than or equal to the re-verification voltage until The threshold voltage of the target memory cell is judged to be less than the re-verification voltage, or the number of times the re-verification voltage is supplied is equal to the number of re-verifications.

Figure 4 is a diagram showing signal waveforms in accordance with an embodiment of the present invention. Please refer to Figures 2, 3 and 4. When the controller 202 receives a programming mode command from an interface, the signal PGM_MODE is enabled, for example, the PGM_MODE signal is changed to the high voltage level 400. Controller 202 provides at least one programming pulse 402 of the PGM_PULSE signal to program a target memory cell of the memory cell of non-volatile memory array 204. After providing at least one programming pulse 402, the controller 202 provides at least one programming verify pulse 404 of PGM_VERIFY_PULSE to the target memory cell to verify whether the target memory cell was successfully programmed. When the target memory cell is not programmed successfully, the controller continues to provide at least one programming pulse 402 to program the target memory cell and at least one program verify pulse 404 to verify that the target memory cell is successfully programmed.

When the target memory cell is successfully programmed, a PV_PASS signal provided by controller 202 is enabled (e.g., pulse 406). The EN_POST_VERIFY signal provided by controller 202 is then enabled (e.g., pulse 408) to perform a re-verification operation. After the PV_PASS signal and the EN_POST_VERIFY signal are enabled, the controller 202 provides at least one re-verification pulse 410 of the POST_VERIFY signal to the target memory cell to verify whether the threshold voltage of the target memory cell is greater than or equal to the re-verification voltage. That is, after pulse 406 and pulse 408, at least one re-verification pulse 410 is provided. When it is determined that the threshold voltage of the target memory cell is less than the re-verification voltage, the controller 202 provides a reprogramming pulse 412 of the POST_PGM signal to program non-volatile The memory cell array 204 targets the memory cell and increases the threshold voltage of the target memory cell. The amplitude of the reprogramming pulse 412 is greater than the amplitude of the programming pulse 402.

Pulse 414 of the PV_DONE signal is then provided by controller 202 to indicate the end of a plurality of verification operations including the program verify operation and the re-verification operation. Finally, the programming operation of the non-volatile memory array 204 is ended, and the PGM_MODE signal is disabled, for example, the PGM_MODE signal is changed to the low voltage level 418.

In various embodiments of the present invention, after the target memory cell of the non-volatile memory array is set to be successfully programmed, a re-verification operation is performed on the target memory cell. That is to say, after the target memory cell is set to be programmed successfully, a re-verification pulse is provided. When the threshold voltage of the target memory cell is less than the re-verification voltage, a reprogramming pulse is provided to program the target memory cell and increase the threshold voltage of the target memory cell. As such, the threshold voltage of the increased target memory cell can be stably higher than the low boundary of the threshold voltage distribution where the target memory cell is located. It can shorten the "tail" of the threshold voltage distribution and make the threshold voltage distribution tighter. The width of the memory window between the threshold voltage distributions can also be increased to reduce the influence of noise fluctuations when reading the target memory cells.

In conclusion, the present invention has been disclosed in the above embodiments, but it is not intended to limit the present invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

Claims (8)

A method of programming a non-volatile memory during programming, the volatile memory comprising a plurality of memory cells, each of the memory cells storing at least 2 bits of data, the method comprising: providing at least a programming pulse to program a target memory cell of the memory cells; applying at least one program verify pulse to the target memory cell; setting the target if a threshold voltage of the target memory cell is greater than or equal to a program verify voltage The memory cell is successfully programmed; and in the case where the target memory cell is set to be programmed successfully, performing a repeated verification operation on the target memory cell, the re-verification operation including applying at least one re-verification pulse to the target memory cell, wherein the at least one The amplitude of the repeatedly verified pulse is equal to the amplitude of the at least one program verify pulse. The method of claim 1, wherein the re-verifying operation further comprises: providing a reprogramming pulse to program the target memory cell if the threshold voltage of the target memory cell is less than a re-verification voltage. The method of claim 2, wherein the amplitude of the reprogramming pulse is greater than the amplitude of the at least one programming pulse. The method of claim 1, further comprising: erasing the memory cells before providing the at least one programming pulse. A method of programming a non-volatile memory during programming, the volatile memory comprising a plurality of memory cells, each of the memory cells storing at least 2 bits of data, the method comprising: providing at least a programming pulse; providing at least one programming verifying pulse; enabling a programming success signal; and providing at least one re-verification pulse after the programming success signal is enabled, wherein the amplitude of the at least one re-verification pulse is equal to the at least one programming verification pulse amplitude. The method of claim 5, further comprising: providing a reprogramming pulse after providing the at least one re-verification pulse; and enabling a verification completion signal after providing the at least one re-verification pulse. The method of claim 6, further comprising: providing a consistent re-verification operation signal after enabling the programming success signal and before providing the at least one re-verification pulse. The method of claim 6, wherein the amplitude of the reprogramming pulse is greater than the amplitude of the at least one programming pulse.