CN110619378A

CN110619378A - Dynamic clock adjustment technology on RFID chip

Info

Publication number: CN110619378A
Application number: CN201910858242.7A
Authority: CN
Inventors: 孙晓霞; 张建伟
Original assignee: Shanghai Mingsi Microelectronics Co Ltd
Current assignee: Shanghai Mingsi Microelectronics Co Ltd
Priority date: 2019-09-12
Filing date: 2019-09-12
Publication date: 2019-12-27
Anticipated expiration: 2039-09-12
Also published as: CN110619378B

Abstract

The invention provides a dynamic clock adjustment technology on an RFID chip. The digital circuit design part in the label uses a counter to calculate the count value used by the delimiter 12.5us by using the delimiter of the command issued by the card reader and the output clock of the analog design as sampling clocks. According to the different counting values, the digital circuit generates a corresponding adjusting value (osc _ trim) to the analog circuit. The problem of overlarge clock frequency deviation of the returned data of the label is solved, the requirement of a card reader for identifying and reading a frequency range is met, and the implementation cost of the solution is low.

Description

Dynamic clock adjustment technology on RFID chip

Technical Field

The invention belongs to the field of integrated circuit chip design, and particularly belongs to the field of ultrahigh frequency radio frequency identification chips.

Background

The RFID system can be divided into low frequency (30 KHz-300 KHz), high frequency (3 MHz-30 MHz), ultrahigh frequency (300 MHz-915 MHz) and microwave (more than 1 GHz) according to the working frequency. The Ultra-High radio frequency Identification (UHF RFID) is the most advanced automatic Identification technology in the world at present, and is rapidly popularized and applied in recent years. The method has the advantages of long identification distance, high identification accuracy, strong anti-interference capability, high identification speed and the like.

The invention researches the digital baseband design of a UHF RFID label chip with the frequency of 860-960MHz and based on ISO/IEC18000-6C protocol. According to the standard, the digital design of the UHF RFID card is divided into five major parts: a receiving PIE decoding circuit, a return M0 coding or Miller subcarrier coding circuit, a BLF clock generating circuit, a random number generating circuit and an error detection 16-bit CRC checking circuit. In the process of coding and decoding, the ultrahigh frequency digital circuit design has higher requirements on the accuracy of an input 1.28MHz clock, if the error is large, a prepared BLF clock cannot be generated, and a card reader cannot identify M0 codes or Miller subcarrier codes generated by an electronic tag. However, due to factors such as ambient temperature, the analog circuit in the electronic tag is inevitably disturbed greatly, so that a high-precision reference clock cannot be generated, which brings great trouble to the design of the digital circuit.

Disclosure of Invention

The invention provides a new idea for solving the problem of clock deviation from the perspective of digital circuit design.

The "ISO/IEC 18000-6C Standard protocol" introduces the basic concepts required by the present invention. The protocol specifies that the communication process from the reader to the tag is downlink communication, which is abbreviated as R ═ T. The communication process from the tag to the card reader is uplink communication, which is abbreviated as T ═ R.

Before the reader starts all R ═ T communications, the reader needs to send a preamble (as shown in fig. 1) or frame sync (as shown in fig. 2) signal. The preamble consists of a fixed length delimiter (12.5us +/-5%), data 0(Tari), R ═ T calibration (RTcal) symbol, and T ═ R calibration (TRcal) symbol. Frame synchronization is equal to preamble minus TRcal section.

The invention uses the fixed time length of the delimiter 12.5us to judge whether the clock which is currently supplied to the digital circuit by the analog circuit meets the requirement of 1.28 MHz. The range in which the clock frequency detectable by the digital circuit can be adjusted is: 0.08MHz to 2.48 MHz. If the input analog clock is in the range of 0.08MHz to 1.28MHz, the clock of the analog circuit needs to be adjusted fast, and the control time is in the range of 0.879us to 1.662 us; if the input analog clock is in the range of 1.28MHz to 2.48MHz, the analog circuit clock is required to be slowed down, and the control time is 0.879us to 5 us. The clock adjustment is a stepwise adjustment process, each time requiring a gradual progression based on the last adjustment. The problem of overlarge clock frequency deviation of the returned data of the label is solved, the requirement of a card reader for identifying and reading a frequency range is met, and the implementation cost of the solution is low.

Drawings

Fig. 1 illustrates a preamble transmitted to a tag by a reader as specified by the ISO/IEC18000-6C standard protocol.

Fig. 2 illustrates the frame synchronization that the reader sends to the tag as specified by the ISO/IEC18000-6C standard protocol.

Fig. 3 illustrates a clock dynamic adjustment diagram.

Fig. 4 illustrates a clock frequency dynamic adjustment look-up table as applied in the present invention.

Fig. 5 illustrates the meaning of a 6-bit tuning parameter sent by a digital logic circuit to an analog circuit.

Fig. 6 illustrates a calculation method for dynamic adjustment of clock, which is provided by taking 1.28MHz as an example, and combining fig. 5.

Detailed Description

In the present invention, as shown in fig. 3, the digital circuit design uses the output clock of the analog design as the sampling clock, and uses a 5-bit counter to calculate the count value used by the delimiter 12.5 us. According to the different counting values, the digital circuit generates a corresponding adjusting value (osc _ trim) to the analog circuit. Fig. 4 depicts the relationship of the input clock frequency osc _ clk, the count value, the adjustment value, and the adjustment ratio. The analog circuit, upon receiving the osc _ trim adjustment value, makes the corresponding adjustment, outputting the new clock frequency osc _ clk shown in fig. 3. By analogy, the digital circuit, upon receiving a new reader command, again detects osc _ clk, makes a corresponding adjustment, and progressively brings the analog output clock close to or equal to the ideal frequency of 1.28 MHz.

Fig. 5 defines the specific meaning of the osc _ trim parameter, and each bit corresponds to a different dynamic adjustment amplitude, which can be used in superposition. Fig. 6 is an exemplary illustration of a 1.28MHz digital input clock. As can be seen from FIG. 6, when osc _ trim is 0x000000, the analog circuit makes no clock adjustment; when the soc _ trim is 0x100001, the 5 th bit represents an increase of 6.25%, the 1 st bit represents a decrease of 100%, and it should be noted that the default value of an adjustment is increased by 100%, so that the final analog adjustment amplitude is increased by 6.25% based on the original input clock frequency.

The dynamic clock adjustment in a lookup table mode is adopted, complex algorithm operation is not needed, the implementation mode is simple, and less logic resources are occupied.

While the present invention has been described in detail with respect to the preferred embodiments thereof, it will be apparent that various modifications and alternatives thereto will become apparent to those skilled in the art upon reading the foregoing description. The above description and drawings are only examples of the practice of the invention, and it should be understood that the above description is not to be taken as limiting the invention.

Claims

1. A dynamic clock adjustment technology on an RFID chip is characterized in that whether a clock currently supplied to a digital circuit by an analog circuit meets the requirement of 1.28MHz is judged by using a fixed time length of a delimiter of 12.5 us.

2. The dynamic clock adjustment technique on an RFID chip of claim 1, wherein the range within which the clock frequency detectable by the digital circuit is adjustable is: 0.08MHz to 2.48 MHz.

3. The dynamic clock scaling technique on an RFID chip of claim 1, wherein if the input analog clock is in the range of 0.08MHz to 1.28MHz, the analog circuit clock is required to be adjusted fast, the control time is in the range of 0.879us to 1.662 us; if the input analog clock is in the range of 1.28MHz to 2.48MHz, the analog circuit clock is required to be slowed down, and the control time is 0.879us to 5 us.

4. The dynamic clock adjustment technique on an RFID chip of claim 1, wherein the digital circuit design uses the output clock of the analog design as a sampling clock and a 5-bit counter to calculate the count value used by the delimiter 12.5 us.

5. A technique for dynamic clock adjustment on an RFID chip as claimed in claim 1, characterized in that the digital circuit generates a corresponding adjustment value (osc _ trim) to the analog circuit on the basis of different count values.

6. The dynamic clock adjustment technique on an RFID chip of claim 1, wherein the relationship between the input clock frequency osc _ clk, the count value, the adjustment value and the adjustment ratio is described with reference to fig. 4.

7. The dynamic clock adjustment technique on an RFID chip of claim 1, wherein the analog circuit, upon receiving the osc _ trim adjustment value, makes a corresponding adjustment to output the new clock frequency osc _ clk shown in fig. 3.

8. The dynamic clock adjustment technique on an RFID chip of claim 1, wherein the digital circuit, upon receiving a new reader command, again detects osc _ clk, makes a corresponding adjustment, and progressively brings the analog output clock close to or equal to the desired frequency of 1.28 MHz.

9. The dynamic clock adjustment technique on an RFID chip according to claim 1, wherein the dynamic clock adjustment in a lookup table manner is adopted without complex arithmetic operations, and is simple in implementation manner and occupies less logic resources.