CN110615123A - Pulse type over-discharge protection and recovery control circuit of satellite-borne storage battery - Google Patents
Pulse type over-discharge protection and recovery control circuit of satellite-borne storage battery Download PDFInfo
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- CN110615123A CN110615123A CN201910949972.8A CN201910949972A CN110615123A CN 110615123 A CN110615123 A CN 110615123A CN 201910949972 A CN201910949972 A CN 201910949972A CN 110615123 A CN110615123 A CN 110615123A
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B64—AIRCRAFT; AVIATION; COSMONAUTICS
- B64G—COSMONAUTICS; VEHICLES OR EQUIPMENT THEREFOR
- B64G1/00—Cosmonautic vehicles
- B64G1/22—Parts of, or equipment specially adapted for fitting in or to, cosmonautic vehicles
- B64G1/42—Arrangements or adaptations of power supply systems
- B64G1/428—Power distribution and management
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Abstract
The invention provides a pulse type over-discharge protection and recovery control circuit of a satellite-borne storage battery, which comprises an over-discharge protection control circuit, an over-discharge recovery control circuit, a discharge switch control circuit and a storage battery pack, wherein an input positive line of the storage battery pack supplies power to a BUS V _ BUS through the discharge switch control circuit, and output ends of the over-discharge protection control circuit and the over-discharge recovery control circuit are respectively connected with the discharge switch control circuit. The invention has the beneficial effects that: the control mode is simple and reliable, the configuration is flexible, the anti-jamming capability is strong, the discharging switch of the storage battery pack can be switched off when the satellite storage battery pack continuously discharges to the lower voltage limit value, the storage battery pack is prevented from being damaged due to over-discharging, and the discharging switch of the storage battery pack is switched on when the satellite storage battery pack continuously charges to the upper voltage limit value, so that power supply to the bus is recovered.
Description
Technical Field
The invention relates to an over-discharge protection and recovery control circuit, in particular to a pulse type over-discharge protection and recovery control circuit of a satellite-borne storage battery.
Background
The satellite storage battery pack has the main function that when the output power of the satellite main energy solar battery array cannot meet the power requirement of the satellite, or in an earth shadow area, the storage battery pack supplies power to other electric equipment of the satellite.
Due to the high voltage and high specific energy of the lithium ion battery pack, the lithium ion battery pack is widely applied to spacecrafts. During the in-orbit operation of the satellite, the storage battery pack may be continuously discharged due to abnormal conditions, and the storage battery pack is damaged due to over-discharge, so that the storage battery pack cannot normally work even if the satellite state is improved, and therefore, a storage battery pack over-discharge protection circuit needs to be designed.
When the satellite state is improved, the solar cell array can have enough output power to charge the storage battery pack, the voltage of the storage battery pack can be continuously increased, when the voltage of the storage battery pack is increased to a certain value, the storage battery pack has enough energy to meet the power requirement of a satellite load, and at the moment, the discharge switch can be switched on, so that the storage battery pack supplies power to the satellite.
Because relay overcurrent ability is relatively poor, take place the adhesion trouble easily, the size is great moreover, leads to using very inconvenient, because MOS pipe's overcurrent ability is strong, convenient design delay start function moreover, the discharge switch of satellite begins to use MOS pipe to replace the relay. However, the on and off of the MOS tube needs to be controlled by a continuous high level or a continuous low level, a control signal is generated by a logic chip, if the logic signal is interfered, signal short-time jitter occurs, the MOS tube can be turned off, the storage battery pack cannot supply power to a bus, the power failure of the whole satellite is caused, and the power supply safety of the satellite is influenced.
On the basis, the MOS tube is used as a main power path, the relay is used as a control signal, and the method is a solution with higher safety and reliability, but the control signal of the relay needs a pulse signal, a circuit capable of generating the pulse signal needs to be designed, when the voltage of the storage battery pack is lower, the pulse signal is output to control the relay to be disconnected, and after the action of the relay is finished, the pulse signal disappears, so that the over-discharge protection of the storage battery pack is finished; when the voltage of the storage battery pack is gradually restored to a higher value, another pulse signal is output to control the relay to be switched on, and the pulse signal disappears after the action of the relay is finished.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a pulse type over-discharge protection and recovery control circuit for a satellite-borne storage battery.
The invention provides a satellite-borne storage battery pulse type over-discharge protection and recovery control circuit which comprises an over-discharge protection control circuit, an over-discharge recovery control circuit, a discharge switch control circuit and a storage battery pack, wherein an input positive line of the storage battery pack supplies power to a BUS V _ BUS through the discharge switch control circuit, the output ends of the over-discharge protection control circuit and the over-discharge recovery control circuit are respectively connected with the discharge switch control circuit, the discharge switch control circuit comprises a relay K1, a resistor R9, a MOS tube V1, a diode D1, a resistor R1, a diode D2 and a resistor R19, a grid of the MOS tube V1 is respectively connected with a pin 8 and a pin 5 of the relay K1 through the resistor R9, a source of the MOS tube V1 is connected with the input positive line of the storage battery pack, a drain of the MOS tube V1 is connected with the BUS V _ BUS, and a pin 9 of the relay K1, Pin 4 is grounded, the over-discharge protection control circuit comprises an over-discharge protection logic control circuit and a driving chip Q1, the base of the driving chip Q1 is connected with the output end of the over-discharge protection logic control circuit, the emitter of the driving chip Q1 is grounded, the collector of the driving chip Q1 is connected with pin 7 of the relay K1, the collector of the driving chip Q1 is connected with the anode of the diode D1, the cathode of the diode D1 is connected with the pin 12 of the relay K1 through the resistor R1, the over-discharge recovery control circuit comprises an over-discharge recovery logic control circuit and a driving chip Q2, the base of the driving chip Q2 is connected with the output end of the over-discharge recovery logic control circuit, the emitter of the driving chip Q2 is grounded, the collector of the driving chip Q2 is connected with pin 6 of the relay K1, the collector of the driving chip Q2 is connected with the anode of the diode D2, the cathode of the diode D2 is connected with the pin 1 of the relay K1 through the resistor R19, and the pin 3 and the pin 10 of the relay K1 are respectively connected with a logic chip power supply voltage VCC; when over-discharge protection occurs, the over-discharge protection logic control circuit controls the driving chip Q1 to be switched on, further controls the relay K1 to be switched off, and after the relay K1 acts in place, the over-discharge protection logic control circuit controls the driving chip Q1 to be switched off, and switches off the driving chip at the relay disconnecting end; when the over-discharge is recovered, the over-discharge recovery logic control circuit controls the conduction of the driving chip Q2 and further controls the connection of the relay K1, and after the action of the relay K1 is in place, the over-discharge recovery logic control circuit controls the disconnection of the driving chip Q2 and closes the driving chip at the relay connection end.
As a further improvement of the present invention, the over-discharge protection logic control circuit includes a resistor R6, a resistor R7, a resistor R8, a resistor R12, a resistor R16, a resistor R13, a comparator U2A, and an and gate U1A, one end of the resistor R7 is grounded, the other end of the resistor R7 is connected to the pin 2 of the comparator U2A through the resistor R8, one end of the resistor R6 is connected to a BUS V _ BUS, the other end of the resistor R6 is connected between the resistor R7 and the resistor R8, one end of the resistor R12 is connected to a voltage reference REF, the other end of the resistor R12 is connected to the pin 3 of the comparator U2A through the resistor R13, one end of the resistor R16 is grounded, the other end of the resistor R16 is connected between the resistor R12 and the resistor R13, the pin 1 of the comparator U2A is connected to the pin VCC 1 of the U1A, and the pin 1A of the and the logic chip A is connected to the voltage supply power supply, and a pin 3 of the AND gate U1A is connected with the base electrode of the driving chip Q1.
As a further improvement of the present invention, the over-discharge protection logic control circuit further includes a resistor R14, a resistor C4, and a resistor R17, the pin 3 of the and gate U1A is connected to the base of the driving chip Q1 through the resistor R14, one end of the resistor C4 is connected between the resistor R14 and the base of the driving chip Q1, the other end is grounded, one end of the resistor R17 is connected between the resistor R14 and the base of the driving chip Q1, and the other end is grounded.
As a further improvement of the invention, pin 2 of the AND gate U1A is grounded after being connected with a capacitor C5.
As a further improvement of the invention, in an on-orbit normal working state of the satellite, the relay K1 is in a switch-on state, the pin 9 of the relay K1 is connected with the pin 8, the pin 4 of the relay K1 is connected with the pin 5, namely GND is connected to the resistor R9 through the relay K1, the MOS tube V1 is in a switch-on state, and the storage battery supplies power to the BUS V _ BUS; at this time, the power supply of the BUS V _ BUS is high, the divided voltage value through the resistor R6 and the resistor R7 is higher than the divided voltage value of the reference voltage REF through the resistor R12 and the resistor R16, the output of the comparator U2A is low level, that is, the input of the pin 1 of the and gate U1A is low level, the pin 3 and the pin 10 of the relay K1 are high level, that is, the input of the pin 2 of the and gate U1A is high level, the output of the pin 3 of the and gate U1A is low level, the driving chip Q1 is in an off state, and the relay K1 does not act; with the continuous discharge of the storage battery pack, the BUS voltage continuously decreases, when the divided voltage value of the BUS V _ BUS via the resistor R6 and the resistor R7 is lower than the divided voltage value of the reference voltage REF via the resistor R12 and the resistor R16, the output of the comparator U2A is high level, that is, the input of the pin 1 of the and gate U1A is high level, the output level of the pin 3 of the and gate U1A is changed from low level to high level, the driving chip Q1 is changed from off state to on state, the relay K1 starts to operate, the switch is changed from on state to off state, the MOS transistor V1 is changed to off state, the pin 9 and the pin 4 of the relay K1 are respectively connected to the pin 10 and the pin 3, that is, that the pin 2 of the and gate U1A is changed to low level, the output level of the pin 3 of the and gate U1A is changed from high level to low level, the driving chip Q1 is changed.
As a further improvement of the present invention, the over-discharge recovery logic control circuit includes a resistor R20, a resistor R22, a resistor R23, a resistor R25, a resistor R26, a resistor R28, a comparator U2B and an nor gate U3, one end of the resistor R22 is grounded, the other end of the resistor R22 is connected to the pin 6 of the comparator U2B through the resistor R23, one end of the resistor R20 is connected to a BUS V _ BUS, the other end of the resistor R20 is connected between the resistor R22 and the resistor R23, one end of the resistor R25 is connected to a voltage reference REF, the other end of the resistor R25 is connected to the pin 5 of the comparator U2 26 through the resistor R26, one end of the resistor R26 is grounded, the other end of the resistor R26 is connected between the resistor R26 and the resistor R26, the pin 7 of the comparator U2 26 is connected to the VCC pin 1 of the nor gate U26, and the nor gate U26 is connected to the logic chip 26, pin 4 of the nor gate U3 is connected to the base of the driver chip Q2.
As a further improvement of the present invention, the over-discharge recovery logic control circuit further includes a resistor R27, a resistor C8, and a resistor R29, the pin 4 of the nor gate U3 is connected to the base of the driving chip Q2 through the resistor R27, one end of the resistor C8 is connected between the base of the resistor R27 and the base of the driving chip Q2, the other end of the resistor C85is grounded, one end of the resistor R29 is connected between the base of the resistor R27 and the base of the driving chip Q2, and the other end of the resistor R29 is grounded.
As a further improvement of the invention, pin 2 of the NOR gate U3 is grounded after being connected with a capacitor C7.
As a further improvement of the present invention, when the solar cell array has power output, the voltage of the battery pack is gradually increased, when the divided voltage value of the BUS V _ BUS via the resistor R20 and the resistor R22 is higher than the divided voltage value of the reference voltage REF via the resistor R25 and the resistor R28, the output of the comparator U2B is low level, that is, the pin 1 of the nor gate U3 is low level, and the pin 2 of the nor gate U3 is also low level, the pin 4 of the nor gate U3 outputs high level, the driving chip Q2 is in a conducting state, the relay K1 starts to operate, the disconnection is changed into the connection, the pin 9 and the pin 4 of the relay K1 are respectively connected with the pin 8 and the pin 5, that is, GND is connected to the resistor R9 through the relay K1, and the MOS transistor V1 is changed into the connection state; pin 3 and pin 10 of the relay K1 become high level, that is, pin 2 of the nor gate U3 becomes high level, the output of pin 4 of the nor gate U3 becomes low level, and the driving chip Q2 becomes off state from on, so that the battery pack overdischarge recovery control function is completed.
As a further improvement of the present invention, the discharge switch control circuit further includes a resistor R10, a resistor R15, and a capacitor C3, the resistor R10 is connected between the resistor R9 and the gate of the MOS transistor V1, one end of the resistor R15 is connected between the resistor R9 and the resistor R10, the other end of the resistor R15 is connected to the source of the MOS transistor V1, one end of the capacitor C3 is connected between the resistor R9 and the resistor R10, and the other end of the capacitor C3 is connected to the source of the MOS transistor V1.
The invention has the beneficial effects that: the control mode is simple and reliable, the configuration is flexible, the anti-jamming capability is strong, the discharging switch of the storage battery pack can be switched off when the satellite storage battery pack continuously discharges to the lower voltage limit value, the storage battery pack is prevented from being damaged due to over-discharging, and the discharging switch of the storage battery pack is switched on when the satellite storage battery pack continuously charges to the upper voltage limit value, so that power supply to the bus is recovered.
Drawings
Fig. 1 is a circuit diagram of a pulse type over-discharge protection and recovery control circuit of a satellite-borne storage battery.
Fig. 2 is an over-discharge protection control circuit diagram of a pulse type over-discharge protection and recovery control circuit of a satellite-borne storage battery.
Fig. 3 is an over-discharge recovery control circuit diagram of a pulse type over-discharge protection and recovery control circuit of a satellite-borne storage battery.
Fig. 4 is a discharge switch control circuit diagram of a satellite-borne storage battery pulse type over-discharge protection and recovery control circuit.
Detailed Description
The invention is further described with reference to the following description and embodiments in conjunction with the accompanying drawings.
As shown in fig. 1 to 4, a satellite-borne storage battery pulse type over-discharge protection and recovery control circuit comprises an over-discharge protection control circuit 101, an over-discharge recovery control circuit 102, a discharge switch control circuit 103 and a storage battery pack 104, wherein an input positive line of the storage battery pack 104 supplies power to a BUS V _ BUS through the discharge switch control circuit 103, output ends of the over-discharge protection control circuit 101 and the over-discharge recovery control circuit 102 are respectively connected with the discharge switch control circuit 103, the discharge switch control circuit 103 comprises a relay K1, a resistor R9, a MOS transistor V1, a diode D1, a resistor R1, a diode D2 and a resistor R19, a gate of the MOS transistor V1 is respectively connected with a pin 8 and a pin 5 of the relay K1 through the resistor R9, a source of the MOS transistor V1 is connected with the input positive line of the storage battery pack, a drain of the MOS transistor V1 is connected with the V _ BUS, the pin 9 and the pin 4 of the relay K1 are grounded, the over-discharge protection control circuit 101 comprises an over-discharge protection logic control circuit and a driving chip Q1, the base of the driving chip Q1 is connected with the output end of the over-discharge protection logic control circuit, the emitter of the driving chip Q1 is grounded, the collector of the driving chip Q1 is connected with the pin 7 of the relay K1, the collector of the driving chip Q1 is connected with the anode of the diode D1, the cathode of the diode D1 is connected with the pin 12 of the relay K1 through the resistor R1, the over-discharge recovery control circuit 102 comprises an over-discharge recovery logic control circuit and a driving chip Q2, the base of the driving chip Q2 is connected with the output end of the over-discharge recovery logic control circuit, the emitter of the driving chip Q2 is grounded, the collector of the driving chip Q2 is connected with the pin 6 of the relay K1, the collector of the driving chip Q2 is connected to the anode of the diode D2, the cathode of the diode D2 is connected to the pin 1 of the relay K1 through the resistor R19, and the pin 3 and the pin 10 of the relay K1 are respectively connected to a logic chip supply voltage VCC; when over-discharge protection occurs, the over-discharge protection logic control circuit controls the driving chip Q1 to be switched on, further controls the relay K1 to be switched off, and after the relay K1 acts in place, the over-discharge protection logic control circuit controls the driving chip Q1 to be switched off, and switches off the driving chip at the relay disconnecting end; when the over-discharge is recovered, the over-discharge recovery logic control circuit controls the conduction of the driving chip Q2 and further controls the connection of the relay K1, and after the action of the relay K1 is in place, the over-discharge recovery logic control circuit controls the disconnection of the driving chip Q2 and closes the driving chip at the relay connection end.
As shown in fig. 1 to 4, the over-discharge protection logic control circuit 101 includes a resistor R6, a resistor R7, a resistor R8, a resistor R12, a resistor R16, a resistor R13, a comparator U2A, and an and gate U1A, one end of the resistor R7 is grounded, the other end of the resistor R7 is connected to the pin 2 of the comparator U2A through the resistor R8, one end of the resistor R6 is connected to the BUS V _ BUS, the other end of the resistor R6 is connected between the resistor R7 and the resistor R8, one end of the resistor R12 is connected to the voltage reference REF, the other end of the resistor R12 is connected to the pin 3 of the comparator U2A through the resistor R13, one end of the resistor R16 is grounded, the other end of the resistor R16 is connected between the resistor R12 and the resistor R13, the pin 1 of the comparator U2A is connected to the VCC 1 of the U1A, and the pin 1A of the and the logic chip is connected to the voltage reference chip, and a pin 3 of the AND gate U1A is connected with the base electrode of the driving chip Q1.
As shown in fig. 1 to 4, the over-discharge protection logic control circuit 101 further includes a resistor R14, a resistor C4, and a resistor R17, the pin 3 of the and gate U1A is connected to the base of the driver chip Q1 through the resistor R14, one end of the resistor C4 is connected between the bases of the resistor R14 and the driver chip Q1, the other end of the resistor C85is grounded, one end of the resistor R17 is connected between the bases of the resistor R14 and the driver chip Q1, and the other end of the resistor R17 is grounded.
As shown in fig. 1 to 4, pin 2 of the and gate U1A is grounded after being connected to the capacitor C5.
As shown in fig. 1 to 4, the overdischarge recovery logic control circuit 102 includes a resistor R20, a resistor R22, a resistor R23, a resistor R25, a resistor R26, a resistor R28, a comparator U2B and an nor gate U3, one end of the resistor R22 is grounded, the other end of the resistor R22 is connected to the pin 6 of the comparator U2B through the resistor R23, one end of the resistor R20 is connected to a BUS V _ BUS, the other end of the resistor R20 is connected between the resistor R22 and the resistor R23, one end of the resistor R25 is connected to a voltage reference REF, the other end of the resistor R25 is connected to the pin 5 of the comparator U2 26 through the resistor R26, one end of the resistor R26 is grounded, the other end of the resistor R26 is connected between the resistor R26 and the resistor R26, the pin 7 of the comparator U2 26 is connected to the VCC 1 of the nor gate U26, and the nor gate U26 is connected to the power supply voltage chip, pin 4 of the nor gate U3 is connected to the base of the driver chip Q2.
As shown in fig. 1 to 4, the over-discharge recovery logic control circuit 102 further includes a resistor R27, a resistor C8, and a resistor R29, the pin 4 of the nor gate U3 is connected to the base of the driving chip Q2 through the resistor R27, one end of the resistor C8 is connected between the bases of the resistor R27 and the driving chip Q2, the other end is grounded, one end of the resistor R29 is connected between the bases of the resistor R27 and the driving chip Q2, and the other end is grounded.
As shown in fig. 1 to 4, pin 2 of the nor gate U3 is grounded after being connected to the capacitor C7.
As shown in fig. 1 to 4, in the normal operating state of the satellite in orbit, the relay K1 is in the on state, the pin 9 of the relay K1 is connected with the pin 8, the pin 4 of the relay K1 is connected with the pin 5, that is, GND is connected to the resistor R9 through the relay K1, the MOS transistor V1 is in the on state, and the battery pack supplies power to the BUS V _ BUS; at this time, the power supply of the BUS V _ BUS is high, the divided voltage value through the resistor R6 and the resistor R7 is higher than the divided voltage value of the reference voltage REF through the resistor R12 and the resistor R16, the output of the comparator U2A is low level, that is, the input of the pin 1 of the and gate U1A is low level, the pin 3 and the pin 10 of the relay K1 are high level, that is, the input of the pin 2 of the and gate U1A is high level, the output of the pin 3 of the and gate U1A is low level, the driving chip Q1 is in an off state, and the relay K1 does not act; with the continuous discharge of the storage battery pack, the BUS voltage continuously decreases, when the divided voltage value of the BUS V _ BUS via the resistor R6 and the resistor R7 is lower than the divided voltage value of the reference voltage REF via the resistor R12 and the resistor R16, the output of the comparator U2A is high level, that is, the input of the pin 1 of the and gate U1A is high level, the output level of the pin 3 of the and gate U1A is changed from low level to high level, the driving chip Q1 is changed from off state to on state, the relay K1 starts to operate, the switch is changed from on state to off state, the MOS transistor V1 is changed to off state, the pin 9 and the pin 4 of the relay K1 are respectively connected to the pin 10 and the pin 3, that is, that the pin 2 of the and gate U1A is changed to low level, the output level of the pin 3 of the and gate U1A is changed from high level to low level, the driving chip Q1 is changed.
As shown in fig. 1 to 4, when the solar cell array has power output, the battery pack voltage gradually increases, when the divided voltage value of the BUS V _ BUS via the resistor R20 and the resistor R22 is higher than the divided voltage value of the reference voltage REF via the resistor R25 and the resistor R28, the output of the comparator U2B is low, that is, the pin 1 of the nor gate U3 is low, and the pin 2 of the nor gate U3 is also low, the pin 4 of the nor gate U3 outputs high, the driver chip Q2 is in a conducting state, the relay K1 starts to operate, the disconnection is changed into the connection, the pin 9 and the pin 4 of the relay K1 are respectively connected with the pin 8 and the pin 5, that is, GND is connected to the resistor R9 through the relay K1, and the MOS transistor V1 is changed into the connection state; pin 3 and pin 10 of the relay K1 become high level, that is, pin 2 of the nor gate U3 becomes high level, the output of pin 4 of the nor gate U3 becomes low level, and the driving chip Q2 becomes off state from on, so that the battery pack overdischarge recovery control function is completed.
As shown in fig. 1 to 4, the discharge switch control circuit 103 further includes a resistor R10, a resistor R15, and a capacitor C3, the resistor R10 is connected between the gates of the resistor R9 and the MOS transistor V1, one end of the resistor R15 is connected between the resistor R9 and the resistor R10, the other end of the resistor R15 is connected to the source of the MOS transistor V1, one end of the capacitor C3 is connected between the resistor R9 and the resistor R10, and the other end of the capacitor C3 is connected to the source of the MOS transistor V1.
As shown in fig. 1 to 4, the MOS transistor V1 is preferably a PMOS transistor.
As shown in fig. 1 to 4, BAT + is a positive input line of the storage battery pack, GND is a return input line of the storage battery pack, V _ BUS is an output voltage of the positive electrode of the storage battery pack after being discharged through a discharge switch, REF _5V1 is a voltage reference, and VCC is a supply voltage of the logic chip.
The invention provides a pulse type over-discharge protection and recovery control circuit of a satellite-borne storage battery, which has the following characteristics:
(1) the logic control circuit consists of the comparator, the AND gate, the NOR gate and the relay, and the circuit is simple and flexible to configure;
(2) when over-discharge protection occurs, the AND gate outputs a signal to control the relay driving chip to be switched on and further to control the relay to be switched off, and the AND gate outputs a low-level signal to switch off the relay disconnection end driving chip after the relay acts in place;
(3) when the over-discharge is recovered, the NOR gate outputs a signal to control the relay driving chip to be conducted so as to control the relay to be conducted, and after the relay acts in place, the NOR gate outputs a low-level signal to close the relay conducting end driving chip;
(4) the relay controls the conduction and the disconnection of the PMOS tube, the circuit is reliable, the influence of signal jitter or a lower computer cutter is avoided, and the unexpected conduction and the disconnection of the discharge switch are avoided.
The pulse type over-discharge protection and recovery control circuit for the satellite-borne storage battery provided by the invention has the advantages of simple and reliable control mode, flexible configuration and strong anti-interference capability, can cut off a discharge switch of the storage battery when the satellite storage battery continuously discharges to the lower voltage limit value, prevents the storage battery from being damaged due to over-discharge, and can be switched on to recover power supply to a bus when the satellite storage battery continuously charges to the upper voltage limit value.
The invention provides a pulse type over-discharge protection and recovery control circuit of a satellite-borne storage battery, which is suitable for sending a pulse signal when the voltage of a storage battery pack is continuously discharged to be lower than a certain value, forcibly closing a discharge switch to prevent the storage battery pack from being damaged due to over-discharge, and sending another pulse signal to switch on the discharge switch to recover the power supply of the storage battery pack to a bus when the storage battery pack is continuously charged to be certain.
Simplification based on this circuit or improvement to improve the reliability of the circuit are within the scope of protection.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (10)
1. The utility model provides a satellite-borne battery pulse type overdischarge protection and recovery control circuit which characterized in that: the over-discharge protection control circuit comprises an over-discharge protection control circuit, an over-discharge recovery control circuit, a discharge switch control circuit and a storage battery pack, wherein an input positive line of the storage battery pack supplies power to a BUS V _ BUS through the discharge switch control circuit, output ends of the over-discharge protection control circuit and the over-discharge recovery control circuit are respectively connected with the discharge switch control circuit, the discharge switch control circuit comprises a relay K1, a resistor R9, a MOS tube V1, a diode D1, a resistor R1, a diode D2 and a resistor R19, a grid electrode of the MOS tube V1 is respectively connected with a pin 8 and a pin 5 of the relay K1 through the resistor R9, a source electrode of the MOS tube V1 is connected with the input positive line of the storage battery pack, a drain electrode of the MOS tube V1 is connected with the BUS V _ BUS, a pin 9 and a pin 4 of the relay K1 are grounded, the over-discharge protection control circuit comprises an over-discharge protection logic control circuit and a drive chip Q685, the base of the driving chip Q1 is connected to the output terminal of the over-discharge protection logic control circuit, the emitter of the driving chip Q1 is grounded, the collector of the driving chip Q1 is connected to pin 7 of the relay K1, the collector of the driving chip Q1 is connected to the anode of the diode D1, the cathode of the diode D1 is connected to pin 12 of the relay K1 through the resistor R1, the over-discharge recovery control circuit includes an over-discharge recovery logic control circuit and a driving chip Q2, the base of the driving chip Q2 is connected to the output terminal of the over-discharge recovery logic control circuit, the emitter of the driving chip Q2 is grounded, the collector of the driving chip Q2 is connected to pin 6 of the relay K1, the collector of the driving chip Q2 is connected to the anode of the diode D2, and the cathode of the diode D2 is connected to pin 1 of the relay K1 through the resistor R19, pin 3 and pin 10 of the relay K1 are respectively connected with a logic chip power supply voltage VCC; when over-discharge protection occurs, the over-discharge protection logic control circuit controls the driving chip Q1 to be switched on, further controls the relay K1 to be switched off, and after the relay K1 acts in place, the over-discharge protection logic control circuit controls the driving chip Q1 to be switched off, and switches off the driving chip at the relay disconnecting end; when the over-discharge is recovered, the over-discharge recovery logic control circuit controls the conduction of the driving chip Q2 and further controls the connection of the relay K1, and after the action of the relay K1 is in place, the over-discharge recovery logic control circuit controls the disconnection of the driving chip Q2 and closes the driving chip at the relay connection end.
2. The pulse type over-discharge protection and recovery control circuit of the satellite-borne storage battery according to claim 1, characterized in that: the over-discharge protection logic control circuit comprises a resistor R6, a resistor R7, a resistor R8, a resistor R12, a resistor R16, a resistor R13, a comparator U2A and an AND gate U1A, one end of the resistor R7 is grounded, the other end of the resistor R7 is connected with the pin 2 of the comparator U2A through the resistor R8, one end of the resistor R6 is connected with the BUS V _ BUS, the other end of the resistor R6 is connected between the resistor R7 and the resistor R8, one end of the resistor R12 is connected with a voltage reference REF, the other end of the resistor R12 is connected with a pin 3 of the comparator U2A through the resistor R13, one end of the resistor R16 is grounded, the other end of the resistor R16 is connected between the resistor R12 and the resistor R13, pin 1 of the comparator U2A is connected to pin 1 of the and gate U1A, pin 2 of the and gate U1A is connected to a logic chip supply voltage VCC, and pin 3 of the and gate U1A is connected to the base of the driver chip Q1.
3. The pulse type over-discharge protection and recovery control circuit of the satellite-borne storage battery according to claim 2, characterized in that: the over-discharge protection logic control circuit further comprises a resistor R14, a resistor C4 and a resistor R17, a pin 3 of the AND gate U1A is connected with a base electrode of the driving chip Q1 through the resistor R14, one end of the resistor C4 is connected between the resistor R14 and the base electrode of the driving chip Q1, the other end of the resistor C4 is grounded, one end of the resistor R17 is connected between the resistor R14 and the base electrode of the driving chip Q1, and the other end of the resistor R17 is grounded.
4. The pulse type over-discharge protection and recovery control circuit of the satellite-borne storage battery according to claim 2, characterized in that: and the pin 2 of the AND gate U1A is grounded after being connected with a capacitor C5.
5. The pulse type over-discharge protection and recovery control circuit of the satellite-borne storage battery according to claim 2, characterized in that: under the normal operating state of the satellite in orbit, the relay K1 is in a switch-on state, the pin 9 of the relay K1 is connected with the pin 8, the pin 4 of the relay K1 is connected with the pin 5, namely GND is connected to the resistor R9 through the relay K1, the MOS tube V1 is in a conducting state, and the storage battery supplies power to the BUS V _ BUS; at this time, the power supply of the BUS V _ BUS is high, the divided voltage value through the resistor R6 and the resistor R7 is higher than the divided voltage value of the reference voltage REF through the resistor R12 and the resistor R16, the output of the comparator U2A is low level, that is, the input of the pin 1 of the and gate U1A is low level, the pin 3 and the pin 10 of the relay K1 are high level, that is, the input of the pin 2 of the and gate U1A is high level, the output of the pin 3 of the and gate U1A is low level, the driving chip Q1 is in an off state, and the relay K1 does not act; with the continuous discharge of the storage battery pack, the BUS voltage continuously decreases, when the divided voltage value of the BUS V _ BUS via the resistor R6 and the resistor R7 is lower than the divided voltage value of the reference voltage REF via the resistor R12 and the resistor R16, the output of the comparator U2A is high level, that is, the input of the pin 1 of the and gate U1A is high level, the output level of the pin 3 of the and gate U1A is changed from low level to high level, the driving chip Q1 is changed from off state to on state, the relay K1 starts to operate, the switch is changed from on state to off state, the MOS transistor V1 is changed to off state, the pin 9 and the pin 4 of the relay K1 are respectively connected to the pin 10 and the pin 3, that is, that the pin 2 of the and gate U1A is changed to low level, the output level of the pin 3 of the and gate U1A is changed from high level to low level, the driving chip Q1 is changed.
6. The pulse type over-discharge protection and recovery control circuit of the satellite-borne storage battery according to claim 1, characterized in that: the over-discharge recovery logic control circuit comprises a resistor R20, a resistor R22, a resistor R23, a resistor R25, a resistor R26, a resistor R28, a comparator U2B and an OR-NOT gate U3, one end of the resistor R22 is grounded, the other end of the resistor R22 is connected with the pin 6 of the comparator U2B through the resistor R23, one end of the resistor R20 is connected with the BUS V _ BUS, the other end of the resistor R20 is connected between the resistor R22 and the resistor R23, one end of the resistor R25 is connected with a voltage reference REF, the other end of the resistor R25 is connected with a pin 5 of the comparator U2B through the resistor R26, one end of the resistor R28 is grounded, the other end of the resistor R28 is connected between the resistor R25 and the resistor R26, pin 7 of the comparator U2B is connected with pin 1 of the NOR gate U3, pin 2 of the NOR gate U3 is connected with a logic chip supply voltage VCC, and pin 4 of the NOR gate U3 is connected with the base of the driving chip Q2.
7. The pulse type over-discharge protection and recovery control circuit of the satellite-borne storage battery according to claim 6, characterized in that: the over-discharge recovery logic control circuit further comprises a resistor R27, a resistor C8 and a resistor R29, wherein a pin 4 of the NOR gate U3 is connected with the base of the driving chip Q2 through the resistor R27, one end of the resistor C8 is connected between the bases of the resistor R27 and the driving chip Q2, the other end of the resistor C8 is grounded, one end of the resistor R29 is connected between the bases of the resistor R27 and the driving chip Q2, and the other end of the resistor R29 is grounded.
8. The pulse type over-discharge protection and recovery control circuit of the satellite-borne storage battery according to claim 6, characterized in that: pin 2 of the nor gate U3 is grounded after being connected to the capacitor C7.
9. The pulse type over-discharge protection and recovery control circuit of the satellite-borne storage battery according to claim 6, characterized in that: when the solar cell array has power output, the voltage of the storage battery pack is gradually increased, when the divided voltage value of the BUS V _ BUS through the resistor R20 and the resistor R22 is higher than the divided voltage value of the reference voltage REF through the resistor R25 and the resistor R28, the output of the comparator U2B is at a low level, namely the pin 1 of the NOR gate U3 is at a low level, and the pin 2 of the NOR gate U3 is also at a low level, the pin 4 of the NOR gate U3 outputs a high level, the driving chip Q2 is in a conducting state, the relay K1 starts to act and is turned on from off, the pin 9 and the pin 4 of the relay K1 are respectively connected with the pin 8 and the pin 5, namely GND is connected to the resistor R9 through the relay K1, and the MOS tube V1 is turned on; pin 3 and pin 10 of the relay K1 become high level, that is, pin 2 of the nor gate U3 becomes high level, the output of pin 4 of the nor gate U3 becomes low level, and the driving chip Q2 becomes off state from on, so that the battery pack overdischarge recovery control function is completed.
10. The pulse type over-discharge protection and recovery control circuit of the satellite-borne storage battery according to claim 1, characterized in that: the discharge switch control circuit further comprises a resistor R10, a resistor R15 and a capacitor C3, wherein the resistor R10 is connected between the gates of the resistor R9 and the MOS transistor V1, one end of the resistor R15 is connected between the resistor R9 and the resistor R10, the other end of the resistor R15 is connected with the source of the MOS transistor V1, one end of the capacitor C3 is connected between the resistor R9 and the resistor R10, and the other end of the capacitor C3 is connected with the source of the MOS transistor V1.
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| CN201910949972.8A CN110615123B (en) | 2019-10-08 | 2019-10-08 | Pulse type over-discharge protection and recovery control circuit of satellite-borne storage battery |
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| CN110615123B (en) | 2022-07-15 |
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Address after: 518000 whole building of satellite building, 61 Gaoxin South Jiudao, Yuehai street, Nanshan District, Shenzhen City, Guangdong Province Patentee after: Shenzhen Aerospace Dongfanghong Satellite Co.,Ltd. Address before: 518000 whole building of satellite building, 61 Gaoxin South Jiudao, Yuehai street, Nanshan District, Shenzhen City, Guangdong Province Patentee before: AEROSPACE DONGFANGHONG DEVELOPMENT Ltd. |
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