CN110610919A - Lead frame, manufacturing method and packaging structure - Google Patents

Lead frame, manufacturing method and packaging structure Download PDF

Info

Publication number
CN110610919A
CN110610919A CN201910898981.9A CN201910898981A CN110610919A CN 110610919 A CN110610919 A CN 110610919A CN 201910898981 A CN201910898981 A CN 201910898981A CN 110610919 A CN110610919 A CN 110610919A
Authority
CN
China
Prior art keywords
wire
base
package structure
insulating material
lead frame
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201910898981.9A
Other languages
Chinese (zh)
Inventor
石哲
徐志前
欧宪勋
程晓玲
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Moonlight Semiconductor Shanghai Co Ltd
Original Assignee
Sun Moonlight Semiconductor Shanghai Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Moonlight Semiconductor Shanghai Co Ltd filed Critical Sun Moonlight Semiconductor Shanghai Co Ltd
Priority to CN201910898981.9A priority Critical patent/CN110610919A/en
Publication of CN110610919A publication Critical patent/CN110610919A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H01L23/49555—Cross section geometry characterised by bent parts the bent parts being the outer leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

The application relates to a lead frame, a manufacturing method and a packaging structure. In various embodiments, a leadframe is provided, comprising: a base having a first surface and a second surface; a plurality of wire stakes disposed about and separated from the base, each of the plurality of wire stakes having a third surface and a fourth surface; a thermoset insulating material encapsulating the base and the plurality of wire stubs and exposing at least a portion of the third and fourth surfaces, wherein the plurality of wire stubs is positioned around the base from inside to outside.

Description

Lead frame, manufacturing method and packaging structure
Technical Field
The present application relates generally to semiconductor packaging technology, and more particularly to a lead frame, a method of fabricating the same, and a package structure for use in leadless packaging technology.
Background
Within the semiconductor industry, it is often desirable to package a finished integrated circuit Die (Die) to form the final product of an integrated circuit chip, while serving important functions such as chip protection, enhanced electrical heating performance, and ease of assembly of the overall device.
Surface mount packages are commonly used in the art, which include quad Flat No-lead (qfn) packages and quad Flat package (qfp) packages. The QFN packaging structure effectively utilizes the packaging space of the terminal pins, thereby greatly improving the packaging efficiency. Meanwhile, the QFN package structure has short conductive paths between pins and bonding pads, and has low self-inductance and low wiring resistance in the package, so that excellent electrical performance can be provided. In addition, the plastic package body of the QFN package structure is small in size and thin, so that the volume of a CPU (Central processing Unit) can be reduced by 30% -50%. Therefore, the QFN package structure has great advantages compared to the QFP package structure.
However, QFN packages are usually manufactured by a stamping (Pouch) process, and thus cannot further satisfy the fine and dense requirements in terms of pin pitch and I/O pin number.
Disclosure of Invention
In view of the above, the present application provides a lead frame, comprising: a base having a first surface and a second surface; a plurality of wire stakes disposed about and separated from the base, each of the plurality of wire stakes having a third surface and a fourth surface; a thermoset insulating material encapsulating the base and the plurality of wire stubs and exposing at least a portion of the third and fourth surfaces, wherein the plurality of wire stubs is positioned around the base from inside to outside.
An embodiment of the present application provides a lead frame, wherein: the first surface is provided with a metal layer or an organic solderability preservative film; the second surface is provided with a metal layer; or the first surface is provided with a metal layer or an organic solderability preservative film, and the second surface is provided with a metal layer.
An embodiment of the present application provides a lead frame, wherein the plurality of wire stubs are through-type wire stubs.
An embodiment of the present application provides a leadframe, wherein at least one of the plurality of wire stubs includes two segments that partially overlap.
An embodiment of the present application provides a leadframe, wherein the base includes two segments that partially overlap.
An embodiment of the present application provides a package structure, which includes: a chip; a lead frame, comprising: a base having a first surface and a second surface; a plurality of wire stakes disposed about and separated from the base, each of the plurality of wire stakes having a third surface and a fourth surface; a thermoset insulating material encapsulating the base and the plurality of wire stubs and exposing at least a portion of the third and fourth surfaces, wherein the plurality of wire stubs are positioned around the base from the inside-out; a metal wire electrically connecting the chip with at least one of the plurality of wire posts; and the sealing compound at least encapsulates the chip, the metal wire and the third surface.
An embodiment of the present application provides a package structure, wherein: the first surface is provided with a metal layer or an organic solderability preservative film; the second surface is provided with a metal layer; or the first surface is provided with a metal layer or an organic solderability preservative film, and the second surface is provided with a metal layer.
An embodiment of the present application provides a package structure, wherein the plurality of wire piles are through-type wire piles.
An embodiment of the present application provides a package structure, wherein at least one of the plurality of wire posts includes two segments that partially overlap.
An embodiment of the present application provides a package structure, wherein at least one of the plurality of wire posts includes two segments that partially overlap.
An embodiment of the present application provides a package structure, wherein the encapsulant is further configured to encapsulate at least a portion of the thermosetting insulating material.
An embodiment of the present application provides a method of fabricating a lead frame, comprising: performing half-etching on a first surface of a metal sheet; coating a thermosetting insulating material on the first surface; developing the thermosetting insulating material to expose at least a portion of the first surface; performing half etching on a second surface of the metal sheet to form a through hole; coating the thermosetting insulating material on the second surface; and developing the thermosetting insulating material to expose at least a portion of the second surface.
An embodiment of the present application provides a method of fabricating a lead frame, wherein the through-hole is a through-hole.
An embodiment of the present application provides a method of making a leadframe, wherein at least one of the through-holes includes two segments that partially overlap.
Drawings
Fig. 1 shows a top view of a QFN package structure in the prior art.
Fig. 2 shows a side view of a QFN package structure in the prior art.
Fig. 3 shows a side view of a QFN package structure improved from fig. 1 and 2 in the prior art.
Fig. 4 shows a leadless package structure according to an embodiment of the present application.
Fig. 5 shows a leadless package structure according to another embodiment of the present application.
Fig. 6 shows a leadless package structure according to yet another embodiment of the present application.
Fig. 7-12 illustrate the method or process steps for making a lead frame according to the present application.
Fig. 13-18 illustrate another method or process step of the present application for making a lead frame.
Detailed Description
In order that the spirit of the application may be better understood, some preferred embodiments of the application are described below.
In this specification, unless specified or limited otherwise, relative terms such as: terms of "central," "longitudinal," "lateral," "front," "rear," "right," "left," "inner," "outer," "lower," "upper," "horizontal," "vertical," "above," "below," "top," "bottom," and derivatives thereof (e.g., "horizontally," "downwardly," "upwardly," etc.) should be construed to refer to the orientation as then described in the discussion or as shown in the drawing figures. These relative terms are for convenience of description only and do not require that the present application be constructed or operated in a particular orientation.
Various embodiments of the present application are discussed in detail below. While specific implementations are discussed, it should be understood that these implementations are for illustrative purposes only. One skilled in the relevant art will recognize that other components and configurations may be used without departing from the spirit and scope of the present application.
Fig. 1 shows a top view of a QFN package structure in the prior art, which includes a base island 10, a conductive pad 11, a chip 12 and a metal line 13.
Fig. 2 shows a side view of a QFN package structure in the prior art, which includes a base island 10, conductive pads 11, a chip 12, metal lines 13, epoxy 14, and leads 15 extending outward in the conductive pads 11. As part of the lead frame, the base island 10 is generally made of a metallic material, the function of which is: first, acting as a mounting base for the chip 12 in the package; and secondly, providing heat dissipation for the chip 12. With the continuous reduction of the chip size, the length of the wires 15 in the conventional QFN package structure is increased, which leads to the problems of the wires 15, such as collapse, deformation or offset, and further leads to displacement or concave collapse in the whole packaging process.
Fig. 3 shows a side view of a QFN package structure improved from fig. 1 and 2 in the prior art, which includes a leadframe 30, a frame body 31, conductive studs 32, conductive pads 33, a chip 40, metal lines 50, an epoxy 60 and an adhesive 70. The improved QFN package structure shown in fig. 3 is a lead frame structure without a base island under a chip, wherein a plurality of conductive studs 32 penetrate through a frame body 31, a conductive pad 33 can be electrically connected to a chip 40 through a metal wire 50, and the frame body 31 is made of an insulating material. The design without the base island can solve the problem of glue overflow, improve the packaging yield and further reduce the packaging size, but the defect is that the conductive piles 32 are manufactured in a laser drilling mode, so that the processing cost is high and the productivity benefit is poor.
Fig. 4 shows a leadless package structure according to an embodiment of the present application, which includes a lead frame 400, wherein the lead frame 400 further includes: a base 401, a plurality of wire stubs 402, wire contacts 403, pin contacts 404, and a thermoset insulating material 405. Preferably, a thermally conductive metal layer 404' may be disposed under the base 401 to better assist in heat dissipation. However, the thermally conductive metal layer need not be disposed beneath the base 401, but may instead be encapsulated by a thermoset insulating material 405 to insulate the base 401 from the environment. The plurality of wire stubs 402 are spaced apart from each other and are generally disposed around the base 401, but do not contact the base 401. Also, an upper surface of each of the plurality of wire stubs 402 may be connected with the wire contact 403, and a lower surface of each of the plurality of wire stubs 402 may be connected with the pin contact 404. In the embodiment shown in fig. 4, the plurality of wire stubs 402 are divided into two portions, with a portion of the wire stub 402 being adjacent to the base 401, thereby forming an inner layer of wire stubs 402 disposed around the base 401; another portion of the wire stub 402 is distal from the base 401, forming an outer layer of the wire stub 402 disposed around the base 401. However, the plurality of wire stubs 402 is not limited to being arranged around the base 401 from the inside to the outside by the above-mentioned two portions or layers of wire stubs 402, but can be arranged around the base 401 from the inside to the outside by more layers of wire stubs 402. The thermoset insulating material 405 generally entirely encapsulates the base 401 and the plurality of wire stubs 402, but may expose upper surfaces of the plurality of wire stubs 402 and connect with the chip via metal lines through corresponding wire contacts 403, and expose lower surfaces of the plurality of wire stubs 402 and make electrical connections with circuitry external to the package structure through corresponding pin contacts 404. As an example, the thermosetting insulating material 405 may be a green paint.
Still referring to fig. 4, a chip 406 is located over the base 401. As an example, the chip 406 in fig. 4 is a double-layer chip, in which the metal wires 407 are separated into upper and lower layers and connected to the corresponding wire contacts 403 in the lead frame 400. However, the number of layers of the chip 406 in fig. 4 may be a single layer or any other number of layers. The encapsulant 408 encapsulates at least the chip 406, the metal lines 407, and the conductive contacts 403. As an embodiment, the encapsulant 408 may also encapsulate at least a portion of the leadframe 400.
Thus, the lead frame 400, the chip 406, the metal lines 407 and the encapsulant 408 in fig. 4 together form an embodiment of a complete leadless package structure.
Fig. 5 shows a leadless package structure according to another embodiment of the present application. Compared to the leadless package structure of fig. 4, the leadless package structure of fig. 5 further includes an organic solder mask osp (organic solder resist preservatives) layer or a nickel-gold (NiAu) layer between the upper surface of the base 501 and the lower surface of the chip 506. The plurality of wire stubs 502 are separated from each other and are generally disposed about the base 501, but do not contact the base 501. The leadless package structure shown in fig. 5 can be used in the case where the chip needs to dissipate heat quickly, but the manufacturing cost is slightly high.
Thus, the lead frame 500, the chip 506, the metal wire 507 and the molding compound 508 in fig. 5 together form another embodiment of a complete leadless package structure.
Fig. 6 shows a leadless package structure according to yet another embodiment of the present application. In contrast to the leadless package structure of fig. 4, the base 601 of the leadless package structure shown in fig. 6 is entirely encapsulated in the thermosetting insulating material 605, and the lower surface thereof is connected to the heat-conducting metal layer to connect the lead frame 600 with the outside. The plurality of wire stubs 602 are spaced apart from each other and are generally disposed about the base 601, but are not in contact with the base 601. Preferably, the base 601 may have a reduced size, as well as an arbitrary shape other than a rectangle. The leadless package structure shown in fig. 6 can be used in the case where the chip needs to dissipate heat at a medium speed, and the warpage (warpage) of the package structure can be adjusted by the size of the base 601.
To this end, the lead frame 600, the chip 606, the metal lines 607 and the encapsulant 608 in fig. 6 together form another embodiment of the complete leadless package structure.
Fig. 7-12 illustrate the method or process steps for making a lead frame according to the present application. First, in the step shown in fig. 7, a metal sheet 701 to be processed into an inner body of a lead frame is released, and the metal sheet 701 may be, for example, a copper sheet or a copper foil. Next, in the step shown in fig. 8, a half-etching or half-biting process is performed on the upper surface of the metal sheet 801 from above, thereby forming a first plurality of grooves 802 on the upper surface of the metal sheet 801. In the step shown in fig. 9, the upper surface having the first plurality of grooves formed in the step of fig. 8 is coated with a thermosetting insulating material 902, and the coated thermosetting insulating material 902 is developed to expose a portion of the surface 903 where the pin contact is to be formed. Preferably, as shown in fig. 9, a surface 904 below the base where the heat conductive metal layer is to be formed may be further exposed by development. Next, in the step shown in fig. 10, a half-etching or half-biting process is performed again on the lower surface of the metal sheet 1001 from below, so as to form a second plurality of trenches 1002 on the lower surface of the metal sheet 1001, wherein the second plurality of trenches 1002 at least partially overlap with the first plurality of trenches 802 formed in the step of fig. 8, so as to form a via hole. Next, in the step shown in fig. 11, the lower surface having the second plurality of grooves formed in the step of fig. 10 is coated with a thermosetting insulating material 1102, and the coated thermosetting insulating material 1102 is developed to expose a portion of the surface 1103 on which the wire contact is to be formed. Next, in a step shown in fig. 12, wire contacts 1203 are formed on the upper surface of the metal sheet 1201 which is not covered with the thermosetting insulating material 1202. Preferably, the wire contact 1203 may be formed of a nickel-gold (NiAu) material.
It should be noted that the half etching or half biting does not strictly refer to half the depth of the etched or bitten metal sheet, but only needs to ensure that a through hole can be formed in the metal sheet after two times of etching or biting. Moreover, although the grooves in the upper and lower portions of the metal sheet are staggered or partially overlapped after the two half-etching or half-biting processes of fig. 8 and 10 are performed, the grooves without stagger (i.e., completely overlapped), i.e., through grooves or through vias, may be formed by using the two half-etching or half-biting processes. Accordingly, the metal between the through-grooves or through-holes for receiving the thermosetting insulating material may constitute the wire piles; when the groove is a through groove or a through via, the wire pile becomes a through wire pile accordingly. Alternatively, a single etch may be used to form a through trench or through via in a metal sheet at a time. The half-etching or half-biting process allows the overall thickness of the lead frame to be designed as desired, thereby further reducing the package size and resulting in better heat dissipation. Preferably, the overall thickness of the lead frame may be designed with the aid of a carrier process.
Fig. 13-18 illustrate another method or process step of the present application for making a lead frame. Fig. 13-16 are the same as fig. 7-10, except for the steps shown in fig. 17 and 18. In the step shown in fig. 17, when the coated thermosetting insulating material 1802 is developed, a portion of the surface of the metal piece on which the wire contact is to be formed is also exposed, and a surface 1704 above the base is also exposed. Next, in the step shown in fig. 18, an organic solder mask osp (organic solder resist preservatives) layer or a nickel-gold (NiAu) layer 1804 is formed on the exposed portion of the surface above the submount to further enhance the heat dissipation capability of the submount for the chip. Preferably, the wire contact may be formed of a nickel-gold (NiAu) material.
The leadless packaging structure disclosed by the application can be designed more flexibly to meet different heat dissipation requirements of various chips, and the manufacturing process is similar, so that the process can be simplified, and the cost can be reduced. Also, another advantage of the leadless package structure of the present application is that the lead frame structure has better conductivity than the filled via (blind via or PTH through via) architecture of a conventional TFBGA package. Meanwhile, due to the special manufacturing process, the thickness of the substrate or the base of the lead frame can be further reduced. Preferably, the substrate or susceptor in the present application may have a thickness of up to 60-90 μm. In addition, the design of the number of the pins in the QFN package structure can be free from restriction, the I/O number is greatly increased, and the glue overflow problem of the common QFN package structure does not exist in the QFN package structure.
The technical content and the technical features of the present application have been described in the above related embodiments, however, the above embodiments are only examples for implementing the present application. Those skilled in the art may still make various alterations and modifications based on the teachings and disclosures of this application without departing from the spirit of this application. Accordingly, the disclosed embodiments of the present application do not limit the scope of the present application. Rather, modifications and equivalent arrangements included within the spirit and scope of the claims are included within the scope of the present application.

Claims (14)

1. A leadframe, comprising:
a base having a first surface and a second surface;
a plurality of wire stakes disposed about and separated from the base, each of the plurality of wire stakes having a third surface and a fourth surface;
a thermoset insulating material encapsulating the base and the plurality of wire posts and exposing at least a portion of the third surface and the fourth surface,
wherein the plurality of wire stubs is positioned around the base from the inside to the outside.
2. The lead frame of claim 1, wherein:
the first surface is provided with a metal layer or an organic solderability preservative film;
the second surface is provided with a metal layer; or
The first surface has a metal layer or an organic soldermask thereon and the second surface has a metal layer thereon.
3. The lead frame of claim 1, wherein the plurality of wire stubs are through wire stubs.
4. The leadframe recited in claim 1 wherein at least one of the plurality of wire posts includes two segments that partially overlap.
5. The lead frame according to claim 1 wherein the base includes two segments that partially overlap.
6. A package structure, comprising:
a chip;
a lead frame, comprising:
a base having a first surface and a second surface;
a plurality of wire stakes disposed about and separated from the base, each of the plurality of wire stakes having a third surface and a fourth surface;
a thermoset insulating material encapsulating the base and the plurality of wire posts and exposing at least a portion of the third surface and the fourth surface,
wherein the plurality of wire stakes are disposed about the base from the inside out;
a metal wire electrically connecting the chip with at least one of the plurality of wire posts;
and the sealing compound at least encapsulates the chip, the metal wire and the third surface.
7. The package structure of claim 6, wherein:
the first surface is provided with a metal layer or an organic solderability preservative film;
the second surface is provided with a metal layer; or
The first surface has a metal layer or an organic soldermask thereon and the second surface has a metal layer thereon.
8. The package structure of claim 6, wherein the plurality of wire stakes are through wire stakes.
9. The package structure of claim 6, wherein at least one of the plurality of wire posts includes two segments that partially overlap.
10. The package structure of claim 6, wherein at least one of the plurality of wire posts includes two segments that partially overlap.
11. The package structure of claim 6, wherein the encapsulant is further configured to encapsulate at least a portion of the thermosetting insulating material.
12. A method of making a leadframe, comprising:
performing half-etching on a first surface of a metal sheet;
coating a thermosetting insulating material on the first surface;
developing the thermosetting insulating material to expose at least a portion of the first surface;
performing half etching on a second surface of the metal sheet to form a through hole;
coating the thermosetting insulating material on the second surface; and
developing the thermosetting insulating material to expose at least a portion of the second surface.
13. The method of claim 12, wherein the via is a through via.
14. The method of claim 12, wherein at least one of the vias includes two segments that partially overlap.
CN201910898981.9A 2019-09-23 2019-09-23 Lead frame, manufacturing method and packaging structure Pending CN110610919A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201910898981.9A CN110610919A (en) 2019-09-23 2019-09-23 Lead frame, manufacturing method and packaging structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201910898981.9A CN110610919A (en) 2019-09-23 2019-09-23 Lead frame, manufacturing method and packaging structure

Publications (1)

Publication Number Publication Date
CN110610919A true CN110610919A (en) 2019-12-24

Family

ID=68891975

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201910898981.9A Pending CN110610919A (en) 2019-09-23 2019-09-23 Lead frame, manufacturing method and packaging structure

Country Status (1)

Country Link
CN (1) CN110610919A (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090278245A1 (en) * 2008-05-12 2009-11-12 Texas Instruments Inc Packaged electronic devices with face-up die having tsv connection to leads and die pad
CN102117791A (en) * 2010-01-06 2011-07-06 日月光半导体制造股份有限公司 Package structure and manufacturing method thereof, and method of manufacturing leadframe structure
CN102354691A (en) * 2011-11-04 2012-02-15 北京工业大学 Quad flat non-lead (QFN) package with high density and manufacturing method
KR20130023432A (en) * 2011-08-29 2013-03-08 삼성테크윈 주식회사 Lead frame structure for semiconductor packaging, manufacturing method of the same and manufacturing method of semiconductor package by using the same
CN210575932U (en) * 2019-09-23 2020-05-19 日月光半导体(上海)有限公司 Lead frame and packaging structure

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090278245A1 (en) * 2008-05-12 2009-11-12 Texas Instruments Inc Packaged electronic devices with face-up die having tsv connection to leads and die pad
CN102117791A (en) * 2010-01-06 2011-07-06 日月光半导体制造股份有限公司 Package structure and manufacturing method thereof, and method of manufacturing leadframe structure
KR20130023432A (en) * 2011-08-29 2013-03-08 삼성테크윈 주식회사 Lead frame structure for semiconductor packaging, manufacturing method of the same and manufacturing method of semiconductor package by using the same
CN102354691A (en) * 2011-11-04 2012-02-15 北京工业大学 Quad flat non-lead (QFN) package with high density and manufacturing method
CN210575932U (en) * 2019-09-23 2020-05-19 日月光半导体(上海)有限公司 Lead frame and packaging structure

Similar Documents

Publication Publication Date Title
US9130064B2 (en) Method for fabricating leadframe-based semiconductor package with connecting pads top and bottom surfaces of carrier
US7786557B2 (en) QFN Semiconductor package
US7879653B2 (en) Leadless semiconductor package with electroplated layer embedded in encapsulant and the method for manufacturing the same
US11004775B2 (en) SMDS integration on QFN by 3D stacked solution
US7847392B1 (en) Semiconductor device including leadframe with increased I/O
TWI565012B (en) A stack frame for electrical connections and the method to fabricate thereof
US20090278243A1 (en) Stacked type chip package structure and method for fabricating the same
JP2005191240A (en) Semiconductor device and method for manufacturing the same
US8592962B2 (en) Semiconductor device packages with protective layer and related methods
US9607860B2 (en) Electronic package structure and fabrication method thereof
US20060273458A1 (en) Substrate structure of semiconductor package
US7952198B2 (en) BGA package with leads on chip
US20090206459A1 (en) Quad flat non-leaded package structure
US7173341B2 (en) High performance thermally enhanced package and method of fabricating the same
US20100295160A1 (en) Quad flat package structure having exposed heat sink, electronic assembly and manufacturing methods thereof
US20120264257A1 (en) Mold array process method to prevent exposure of substrate peripheries
CN210575932U (en) Lead frame and packaging structure
CN110610919A (en) Lead frame, manufacturing method and packaging structure
CN106158782B (en) Electronic package and manufacturing method thereof
US20180025965A1 (en) WFCQFN (Very-Very Thin Flip Chip Quad Flat No Lead) with Embedded Component on Leadframe and Method Therefor
KR100437821B1 (en) semiconductor package and metod for fabricating the same
KR100473336B1 (en) semiconductor package
KR100324932B1 (en) chip size package
KR20040045696A (en) method for fabricating semiconductor package
KR20010054002A (en) stack type semiconductor package and method for manucture of the same

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination