CN1106079C

CN1106079C - Digital analogue signal/digital signal conversion circuit

Info

Publication number: CN1106079C
Application number: CN 98118628
Authority: CN
Inventors: 陈建州
Original assignee: Amtran Technology Co Ltd
Current assignee: Amtran Technology Co Ltd
Priority date: 1998-08-20
Filing date: 1998-08-20
Publication date: 2003-04-16
Anticipated expiration: 2018-08-20
Also published as: CN1246000A

Abstract

The present invention relates to a digital analog signal/digital signal converting circuit which comprises a time sequence signal synthesizer, three analog/digital converters, a digital subtracter, a CPU and a phase regulator, wherein the time sequence signal synthesizer is respectively connected with the three analog/digital converters. Two analog/digital converters are respectively connected with the digital subtracter. The CPU is respectively connected with the time sequence signal synthesizer, the digital subtracter and the phase regulator. The third analog/digital converter receives digital analog signals, simultaneously receives time sequence signals which are output by the time sequence signal synthesizer and are delayed via a first-stage buffer; the third analog/digital converter also outputs digital signals.

Description

Digital simulation signal/digital signal conversion circuit

The present invention relates to a kind of digital simulation signal/digital signal conversion circuit, particularly a kind of circuit that the digital simulation signal of video signal is converted to the digital image signal that is suitable for liquid crystal display displays.

Development along with PC, and then make some videos (video), audio frequency analog signals such as (audio) form multimedia through computer, treated digital signal must become analog signal through the digital/analog converter reduction, just can be general loud speaker or traditional C RT display and receives.And the analog signal that is reduced is different from original analog signal, is referred to as " digital simulation signal ", as shown in Figure 1.

If the digital simulation signal demand (is referred to accept the device of digital signal by some digital device once more, for example: sampling liquid crystal display (LCD) panel), to convert digital signal to, then must meet some requirements, could accurately take a sample into original digital signal.Below be that example describes with the signal of signal of video signal and LCD panel application.

The LCD panel is a kind of device that only can receiving digital signals, and the signal of video signal of the display card output on the general PC is aforesaid digital simulation signal, therefore when this signal of video signal enters the LCD panel, must use analog/digital converter to take a sample to obtain digital signal.If in sampling process, can't accurately take a sample or take a sample in fuzzy area, then can cause picture distortion or unintelligible.

With reference to figure 2, wherein timing CLK (positive edge action) is not a suitable sampled signal, and distortion (can be with the digital signal b after the interpretation of Fig. 2 below because it not only makes the digital signal generation ₀b ₁b ₂b ₃b ₄b ₅Compare with the digital simulation signal of Fig. 2 top), more produced some indefinite signal areas.

Fig. 3 shows three kinds of different timing CLK1, CLK2, CLK3, and it is desirable timing signal that CLK3 is wherein only arranged, and be described as follows: the operating point of CLK1 is unsatisfactory, because the result of sampling can periodically produce blooming.Hence one can see that, when the frequency of the frequency of timing signal and the raw digital signal of this digital simulation signal is consistent, just can avoid the generation of this periodically fuzzy phenomenon.Though CLK2 meets above-mentioned condition, but because the operating point of most digital and electronic part all has the restriction of settling time (setup time) and retention time (hold time), and for different parts, the requirement of settling time and retention time is not quite similar.The sampling action point of CLK2 just in time is positioned at the edge that signal changes among the figure, therefore for analog/digital converter, the data after the sampling may for change preceding or change after signal, so the sampling action point of CLK2 is still undesirable.

CLK3 is a desirable timing, can take a sample and obtains clear and definite signal because each sampling action point all is positioned at stable state, and not omit any signal, so be good sample program.

The object of the present invention is to provide a kind of A/D conversion circuit that can seek a suitable timing automatically, avoiding signal in transfer process, distortion or produce blurred signal.

For achieving the above object, the present invention takes following scheme:

A kind of digital simulation signal/digital signal conversion circuit of the present invention comprises:

The clock signal synthesizer is accepted a synchronous signal and a frequency index signal, exports a clock signal CLK1;

First analog/digital converter is accepted the clock signal CLK1 of digital simulation signal and clock signal synthesizer output, according to the sampling point of clock signal CLK1 the digital simulation conversion of signals is become one first digital signal;

Second analog/digital converter is accepted the output of digital simulation signal and clock signal synthesizer and the clock signal CLK2 of process two-stage buffer delay, and the sampling point according to postponing clock signal becomes one second digital signal with the digital simulation conversion of signals;

Digital subtractor is accepted first and second digital signal, and the difference ERR that both are subtracted each other exports;

CPU accepts the output signal ERR of digital subtractor, and the output frequency index signal is delivered to the clock signal synthesizer, and exports a phase indication signal;

Phase regulator, accept a horizontal-drive signal with from the phase indication signal of CPU, adjust the phase place of horizontal-drive signal, deliver to the clock signal synthesizer through the horizontal-drive signal of adjusting phase place, as its synchronizing signal;

The 3rd analog/digital converter, the clock signal CLK that accepts the output of digital simulation signal and clock signal synthesizer and postpone through the first-level buffer device exports a digital signal.

Described digital simulation signal/digital signal conversion circuit is characterized in that, also comprises: pre-amplifier, amplify in order to described digital simulation signal is made prime, and then enter described the 3rd analog/digital converter.

Described circuit is characterized in that, described clock signal synthesizer comprises a phase-locked loop and a connected frequency divider.

The simple declaration of accompanying drawing:

Fig. 1: the schematic diagram of digital simulation signal;

Fig. 2: when timing is inappropriate, the bad digital signal schematic representation that is caused;

Fig. 3: the schematic diagram of suitable timing signal;

Fig. 4: the block diagram of digital simulation signal/digital signal conversion circuit of the present invention;

Fig. 5 and Fig. 6: judge the schematic diagram that timing CLK is whether suitable by clock signal CLK1 and CLK2;

Fig. 7: flow chart of the present invention.

Reaching embodiment in conjunction with the accompanying drawings is described in detail as follows:

With reference to figure 4, of the present inventionly can accurately convert the digital simulation signal to digital signal conversion circuit and comprise: clock signal synthesizer 1, analog/digital converter 2, analog/digital converter 3, digital subtractor 4, CPU5, phase regulator 6 and analog/digital converter 7.

Clock signal synthesizer 1 is accepted a synchronous signal and a frequency index signal, according to this synchronizing signal and frequency index signal, exports a clock signal CLK1.

Analog/digital converter 2 is accepted the clock signal CLK1 of digital simulation signal and clock signal synthesizer 1 output, according to the sampling point of clock signal CLK1 the digital simulation conversion of signals is become one first digital signal.

Analog/digital converter 3 is accepted the clock signal CLK2 of digital simulation signal and 1 output of clock signal synthesizer and process two-stage buffer delay, sampling point according to the clock signal CLK2 of this delay becomes one second digital signal with this digital simulation conversion of signals.

Digital subtractor 4 is accepted first and second digital signal, and the difference ERR that both are subtracted each other exports.

CPU 5, accept the output signal ERR of digital subtractor 4, according to signal ERR and output frequency index signal and deliver to clock signal synthesizer 1, and export a phase indication signal.

Phase regulator 6 accept horizontal-drive signal H-Sync with from the phase indication signal of CPU 5, adjust the phase place of horizontal-drive signal H-Sync according to this phase indication signal, to deliver to clock signal synthesizer 1 through the horizontal-drive signal of adjusting phase place, as its synchronizing signal.

Analog/digital converter 7 is accepted digital simulation signal and the clock signal CLK that 1 output of clock signal synthesizer and process first-level buffer device postpone, and exports a digital signal, and this digital signal is the output signal of entire circuit.

With reference to figure 7, the circuit operation mode of Fig. 4 is as follows:

(1) when the output signal ERR of digital subtractor 4 be low value, the digital signal that analog/digital converter 7 is exported is by being asked, otherwise carries out step (2);

(2) CPU 5 sends phase indication signal, and notice phase regulator 6 postpones the phase place of the horizontal-drive signal H-Sync of input, and the phase place of the clock signal CLK1 that clock signal synthesizer 1 exported is delayed, and then carries out step (3);

(3) whether oneself surpasses one-period to the phase delay of inspection clock signal CLK1, does not then carry out step (1) if surpass, otherwise carries out step (4);

(4) CPU 5 sends the frequency index signal, and notice clock signal synthesizer 1 changes the frequency of the clock signal CLK1 of output, gets back to step (1).

In addition, the circuit that accurately converts the digital simulation signal to digital signal of the present invention also can comprise pre-amplifier, amplifies in order to this digital simulation signal is made prime, and then enters analog/digital converter 7.

As shown in Figure 4, horizontal-drive signal H-Sync adjusts after the phase place through phase regulator 6, enter clock signal synthesizer 1 as its synchronizing signal, clock signal synthesizer 1 is with after this synchronizing signal frequency multiplication, the signal that produces is through the first-level buffer device, enter analog/digital converter 7 then as its timing, the digital signal of analog/digital converter 7 outputs is required digital signal.

Frequency divider (remove N) is controlled the size of its N value by CPU5, controls the frequency (frequency=N of timing * (frequency of horizontal-drive signal H-Sync)) of timing by this.In this structure, except controlling the frequency of timing signal, also must control figure formula analog signal and the phase place (being the phase relation of digital simulation signal and timing signal) of timing, so could be accurately with the digital simulation sample of signal to become digital signal.

For above-mentioned purpose, the present invention utilizes following ball bearing made using to change the phase place of digital simulation signal and timing, to reach the purpose of adjustment.

The digital simulation signal is attended by a horizontal-drive signal H-Sync, and horizontal-drive signal has certain phase relation with respect to the digital simulation signal.In addition, for clock signal synthesizer 1, phase place between the clock signal of its output and the synchronizing signal of input also keeps certain, therefore, if change the phase relation of this horizontal-drive signal and digital simulation signal, can change the clock signal of clock signal synthesizer 1 output and the phase relation of digital simulation signal.

As shown in Figure 4, the present invention utilizes CPU 5 to come control phase adjuster 6, with the phase place of adjustment horizontal-drive signal H-Sync, and then changes the clock signal of clock signal synthesizer 1 output and the phase relation of digital simulation signal.

Utilize the clock signal CLK1 of clock signal synthesizer 1 output among Fig. 4, transport to analog/

digital converter

2,3,7 respectively; One the road is directly inputted into analog/digital converter 2; One tunnel process level 2 buffering device becomes CLK2, enters analog/digital converter 3 then; One tunnel buffer through one-level becomes CLK again, enters analog/digital converter 7 then.Be 3ns the time of delay of supposing the first-level buffer device, then CLK1 than CLK fast 3ns, and CLK2 than CLK slow 3ns.As shown in Figure 5, if the centre of the flat region of digital simulation signal is dropped in the sampling working point of timing CLK, then the value that obtains of CLK1 and CLK2 sampling is very approaching, and the output ERR of digital subtractor 4 " is almost 0 ".On the contrary, as shown in Figure 6, if the variation edge of digital simulation signal is dropped in the sampling working point of timing CLK, then the value that obtains of CLK1 and CLK sampling has sizable difference, and the value of ERR is also very big.Therefore, can utilize the output ERR of digital subtractor 4 to judge whether the sampling action point of analog/digital converter 7 is suitable.

Clock signal synthesizer 1 of the present invention comprises a phase-locked loop and a frequency divider.

Compared with prior art the change-over circuit of digital simulation signal/data signal of the present invention has following effect:

1, must not consider Time Created, the maintenance of signal/digital quantizer selected in the circuit Whether the time is variant, because this circuit is as determinating reference with the numerical value after relatively taking a sample;

2. still can work for dynamic digital simulation signal, also can be because of this numeral The formula analog signal is too complicated and its function reduction maybe can't be moved, and can greatly improve automatic adjustment The restriction of scope.

Claims

1, a kind of digital simulation signal/digital signal conversion circuit comprises:

2, digital simulation signal/digital signal conversion circuit according to claim 1 is characterized in that, also comprises: pre-amplifier, amplify in order to described digital simulation signal is made prime, and then enter described the 3rd analog/digital converter.

3, circuit according to claim 1 is characterized in that, described clock signal synthesizer comprises a phase-locked loop and a connected frequency divider.