CN110602667A - Low-power consumption thing networking connectivity chip - Google Patents

Abstract

The invention discloses a low-power consumption Internet of things connectivity chip, which comprises a wireless connectivity module, a CPU (Central processing Unit) subsystem, a memory subsystem, a DMA (direct memory access) subsystem, an accelerator subsystem and a peripheral subsystem, wherein the CPU subsystem is connected with the memory subsystem through a wireless communication network; the wireless connectivity module, the CPU subsystem, the memory subsystem, the DMA subsystem, the accelerator subsystem and the peripheral subsystem are all communicated with the system bus, the system can meet the requirements of numerous market segments, the scale effect is obvious, and the chip cost can meet the requirements of the Internet of things terminal, namely the requirements of low power consumption, low cost, ultra-long standby and the like.

Description

Low-power consumption thing networking connectivity chip

Technical Field

The invention belongs to the technical field of Internet of things system chips, and particularly relates to a low-power-consumption Internet of things connectivity chip.

Background

Since the internet of things was proposed in 1999, the internet of things has gained wide attention and rapid development, and is known as an engine for promoting industry upgrading to advance to the information society. Its english name is: "Internet of things (IoT)". Internet of things is also known internationally as sensor networks, which is another wave of information industry after computers, internet and mobile communication networks. Everything in the world, small to watches and keys and big to automobiles and buildings, can become intelligentized by embedding a micro-induction chip. By means of wireless network technology, people can talk with objects and can communicate between the objects, which is the vision of the internet of things.

In recent years, information strategies related to the internet of things are proposed in major developed countries and regions in the world, the industry looks better at the internet of things, the internet of things is regarded as the next blue sea, and all manufacturers invest a large amount of manpower and material resources to study and arrange in the direction of the internet of things.

The concept of the internet of things is Wide, market segments are numerous, and the appeal of each market to chips and solutions is inconsistent, so that the existing internet of things solution is eight-fold, and from the perspective of communication technology, the solutions can be simply divided into two categories, namely a cellular technical scheme (LPWA, Low Power Wide Area) and a non-cellular technical scheme. The cellular technical scheme is that 2G/3G/4G or even 5G wireless communication technology is utilized to realize the interconnection of everything and the connection of the masses, and mature cellular network infrastructure and ecology are fully utilized; the non-cellular technology is to realize object connection by using short-distance communication technologies such as WIFI and Bluetooth.

Market forecast structure data indicates that the number of nodes connected globally by 2020 will be on the order of 250-500 billion, most of which will be of the cellular technology (LPWA) class. Areas of coverage include personal smart wearable devices, medical, health, and the like.

Each market segment has its own unique requirements that are economically infeasible if a chip or solution is customized for each market segment. As previously analyzed, such terminals require a standby time of months to years, and therefore the chip should have power consumption levels of uW to nW. The requirements of different market segments on the cost are inconsistent, and the cost of the LPWA terminal facing the personal consumption field is controlled within the range of several yuan to dozens of yuan RMB. Sensors, RF, MCU, connectivity technologies (BT, Zigbee, WIFI, 5G-MTC) and the like need to be integrated in a single chip, and great challenges are brought to packaging technologies.

Most of the LPWA chips on the market at present are based on mature LTE chips to perform function deletion and performance reduction, but face a series of problems such as high cost and large power consumption (short standby time).

Other solutions of the internet of things are mostly based on the existing application processor chip, the reduction and allocation of the processor capacity and the enhancement of the segment distance communication technology (BT, Zigbee and WIFI) are performed, and the cellular technology is not supported yet. The sensor and the radio frequency are provided by means of independent matched chips. The main disadvantages of the existing solutions are: (1) the control capability is weak, and the connectivity function is mainly used; (2) the area and the power consumption are high; (3) cost is not an advantage, and profit margins are limited when shipping on a large scale.

Disclosure of Invention

In view of the above, the invention provides a low-power-consumption internet-of-things connectivity chip, which can meet the requirements of numerous market segments, has a significant scale effect, and can meet the requirements of an internet-of-things terminal, namely the requirements of low power consumption, low cost, ultra-long standby and the like.

The technical scheme for realizing the invention is as follows:

a low-power consumption Internet of things connectivity chip comprises a wireless connectivity module, a CPU (Central processing Unit) subsystem, a Memory subsystem, a DMA (direct Memory Access) subsystem, an accelerator subsystem and a peripheral subsystem;

the wireless connectivity module comprises an LPWAN (Low-Power Wide-Area Network) functional module, a WIFI functional module, a Bluetooth functional module and a zigbee functional module;

the CPU subsystem is a single-core or multi-core processor;

the accelerator subsystem realizes algorithm acceleration of FFT, digital filtering and convolution network;

the peripheral subsystem comprises a USB interface module, a CAN interface module, an Ethernet interface module, an I2C interface module, an SPI interface module, an ADC interface module and a DAC interface module;

the wireless connectivity module, the CPU subsystem, the memory subsystem, the DMA subsystem, the accelerator subsystem and the peripheral subsystem are all communicated with a system bus.

Further, the MCU (protocol stack) of the wireless connectivity module is multiplexed with the MCU of the CPU subsystem.

Has the advantages that:

the chip disclosed by the invention is high in integration level, small in area, low in power consumption and wide in application range, the single chip can meet numerous market segments, the scale effect is obvious, and the chip cost can meet the requirements of the Internet of things terminal, namely the requirements of low power consumption, low cost, ultra-long standby and the like.

Drawings

FIG. 1 is a schematic diagram of a chip architecture according to the present invention.

Detailed Description

The invention is described in detail below by way of example with reference to the accompanying drawings.

The invention provides a low-power consumption internet of things connectivity chip, which comprises a wireless connectivity module, a CPU (central processing unit) subsystem, a Memory subsystem, a DMA (direct Memory access) subsystem, an accelerator subsystem and a peripheral subsystem, wherein the CPU subsystem is connected with the Memory subsystem through a network;

the wireless connectivity module comprises an LPWAN (Low-Power Wide-Area Network) functional module, a WIFI functional module, a Bluetooth functional module and a zigbee functional module, and the subsystem is realized by adopting a hardware accelerator structure and can better control the whole Power consumption of the chip.

The CPU subsystem is a single-core or multi-core processor, is positioned as a microcontroller and runs an Android wear or other embedded operating systems. In order to further reduce the area, power consumption and cost of the chip, the MCU of the CPU subsystem and the MCU (protocol stack) of the wireless connectivity module may be multiplexed.

The memory subsystem comprises an Embedded Flash memory (Embedded Flash), an SRAM and an expanded external memory interface.

The DMA subsystem realizes data transmission and transfer between the memories, between the memories and the peripheral equipment and between the peripheral equipment and the memories, saves the intervention of a CPU and reduces the power consumption.

The accelerator subsystem realizes algorithm acceleration of FFT, digital filtering and convolution network; the special algorithm accelerator is customized according to special application scenes such as intelligent agricultural machinery and the like, and the operation and control efficiency can be greatly improved.

The peripheral subsystem comprises a USB interface module, a CAN interface module, an Ethernet interface module, an I2C interface module, an SPI interface module, an ADC interface module and a DAC interface module so as to meet the requirements of insufficient application.

The wireless connectivity module, the CPU subsystem, the memory subsystem, the DMA subsystem, the accelerator subsystem and the peripheral subsystem are all communicated with a system bus.

In summary, the above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (2)

1. A low-power consumption Internet of things connectivity chip is characterized by comprising a wireless connectivity module, a CPU (Central processing Unit) subsystem, a memory subsystem, a DMA (direct memory access) subsystem, an accelerator subsystem and a peripheral subsystem;

the wireless connectivity module comprises an LPWAN functional module, a WIFI functional module, a Bluetooth functional module and a zigbee functional module;

the CPU subsystem is a single-core or multi-core processor;

the accelerator subsystem realizes algorithm acceleration of FFT, digital filtering and convolution network;

the peripheral subsystem comprises a USB interface module, a CAN interface module, an Ethernet interface module, an I2C interface module, an SPI interface module, an ADC interface module and a DAC interface module;

the wireless connectivity module, the CPU subsystem, the memory subsystem, the DMA subsystem, the accelerator subsystem and the peripheral subsystem are all communicated with a system bus.

2. The low-power consumption internet of things connectivity chip of claim 1, wherein the MCU of the wireless connectivity module is multiplexed with the MCU of the CPU subsystem.