CN111416654B

CN111416654B - Satellite virtualization gateway station transmission architecture based on hardware acceleration

Info

Publication number: CN111416654B
Application number: CN202010182499.8A
Authority: CN
Inventors: 王程; 张志丽; 都乐; 王卫东
Original assignee: Beijing University of Posts and Telecommunications; CETC 54 Research Institute
Current assignee: Beijing University of Posts and Telecommunications; CETC 54 Research Institute
Priority date: 2020-03-16
Filing date: 2020-03-16
Publication date: 2021-07-09
Anticipated expiration: 2040-03-16
Also published as: CN111416654A

Abstract

The invention discloses a satellite virtualization gateway station transmission architecture based on hardware acceleration, and belongs to the field of communication signal processing. The architecture comprises a radio frequency unit and a gateway station; the gateway station comprises a clock synchronization unit, a general processing platform and a hardware acceleration platform; the clock synchronization unit is respectively connected with the general processing platform and the hardware acceleration platform; the general processing platform is communicated with the hardware acceleration platform through a PCIe high-speed interface; the general processing platform is connected with the radio frequency unit. PCIe high-speed interfaces include XDMA, MM2S AXIDMA, and S2MM AXIDMA. After the logic circuit is built, the XDMA maps the interrupt into MSI or Legacy interrupt, and the data is transmitted to the hardware acceleration platform for caching through the XDMA; if the MM2S AXIDMA generates an interrupt, reading data from the hardware acceleration platform, and transmitting the data into the interior for processing; if the S2MM AXIDMA interrupts again, the S2MM AXIDMA transfers data to the DDR3 memory over the PCIe high speed interface. The XDMA reads data from the DDR3 memory and sends the data back to the general processing platform to be transmitted to the radio frequency unit. The invention improves the processing capacity and the real-time property.

Description

Satellite virtualization gateway station transmission architecture based on hardware acceleration

Technical Field

The invention belongs to the field of communication signal processing, and particularly relates to a satellite virtualization gateway station transmission architecture based on hardware acceleration, which improves the transmission capability of the whole system.

Background

Satellite communication is an important complement of terrestrial communication networks and has irreplaceable roles in maritime communication, emergency communication and the like. The Geostationary Earth Orbit (GEO) satellite mobile communication system utilizes a Geostationary Earth Orbit (GEO) satellite as a relay, has the characteristics of large capacity, small terminal support, simple network control, seamless coverage and the like, and can be widely applied to industries such as weather, water conservancy, fishery, forestry, military communication and the like. The role of the satellite mobile terminal in providing communication security is more prominent when facing an emergency such as an earthquake, flood, or typhoon.

The GEO satellite mobile communication system mainly comprises a gateway station, a communication satellite and various mobile terminals, wherein the gateway station is a center for system management, exchange and control and is responsible for processing of system signal access, user authentication management, service admission control, data exchange and the like. The research on the satellite mobile communication gateway station technology can accelerate the development period of the corresponding communication satellite, improve the application of new technology in a satellite mobile communication system, accelerate the construction and technology upgrade of the satellite communication system in China and improve the communication guarantee capability of China facing emergency.

With the continuous update of network technology, the diversification of data service types and the continuous popularization of intelligent terminal application, users have made higher requirements on communication service provision capability and network service capability. While meeting the ever-increasing user demands, the development of the mobile communication industry faces the pressure of efficiency, cost and environmental protection, and the establishment of a high-quality mobile communication network with high efficiency, economy and sustainable development becomes the key for improving the core competitiveness. The introduction of the virtualization technology can create good conditions for resource sharing and allocation of the gateway station, so that the user service is processed in a virtual gateway station establishing mode, and the expenditure for building and maintaining the gateway station can be reduced. The reasonable architecture directly determines the investment in aspects of system development, construction, energy consumption, operation and maintenance and the like, and the quality of communication service.

The traditional satellite communication system is a single-beam satellite system, such as a UHF-band satellite communication system, the number of terminals supported by the system is small, complex mobility management cannot be performed, the system resource dimensionality is small, and commercial popularization and promotion cannot be performed. The gateway station of the system adopts an architecture based on independent processing of each channel, the modulation, demodulation, control and interface units of each channel of the system are all carried out through independent channels, the architecture is simple in thought and easy to implement, but network management and monitoring functions are insufficient, and interconnection with other network systems or systems is not flexible enough, and particularly under the condition of a large number of channels, the hardware is large in scale and difficult to maintain.

In the future, a wireless network is subject to coexistence of multiple systems, including 3G, 4G, 5G, Wi-Fi and other unlicensed spectrum access technologies, and the network is more and more complex; secondly, a future mobile network needs to support multiple types of services, and each service has great difference in network performance indexes such as speed, connection number and time delay.

Disclosure of Invention

Aiming at the problems of expansibility, flexibility, controllability and fusion of a wireless heterogeneous network, different requirements on instantaneity, time delay and the like, the invention provides a satellite virtualization gateway station transmission architecture based on hardware acceleration.

The satellite virtualization gateway station transmission architecture based on hardware acceleration comprises a radio frequency unit and a gateway station which are connected; the gateway station comprises a clock synchronization unit, a general processing platform and a hardware acceleration platform;

the clock synchronization unit is respectively connected with the general processing platform and the hardware acceleration platform; the general processing platform is communicated with the hardware acceleration platform through an improved PCIe high-speed interface; meanwhile, the general processing platform is connected with the radio frequency unit. The hardware acceleration platform comprises a DDR3 memory and a physical layer.

The PCIe high-speed interface comprises: XDMA (Xing distributed media architecture), MM2S axidma (memory map to stream) and S2MM axidma (stream to memory map);

the concrete configuration is as follows:

clicking block design in design software vivado to enter a circuit design interface, selecting a DMA Subsystem for PCI Express IP core, namely XDMA, and configuring the XDMA;

the method specifically comprises the following steps:

lane Width: x2 is selected.

Max Link Speed: 5.0GT/s, PCIE2.0, is selected.

Reference Clock: 100MHz, reference clock 100 MHz.

DMA Interface Option: the interface selects the AXI4 interface.

AXI Data Width: the 128bit, AXI4 data bus width is 128 bit.

AXI Clock: the 125M, AXI4 interface clock is 125 MHz.

The interrupt selects an MSI interrupt.

Then, AXI-DMA configuration is carried out, and two AXI-DMAs are selected for the whole structure, wherein one is responsible for S2MM and the other is responsible for MM 2S. The Memory Map Data Width of the two is set to 64, and the Width of an AXI4 interface is increased.

Finally, the address of the XDMA is configured: the address of the PCIe control interface Bar address to the AXI bus is mapped to 0x44a 00000.

After the configuration is completed, the modules are connected in block design to complete the construction of the logic circuit. The S2MM AXI-DMA and the MM2S AXI-DMA respectively reserve one pin so as to be convenient for being connected with a physical layer.

The working principle of the satellite virtualization gateway station transmission architecture based on hardware acceleration is as follows:

step one, after the logic circuit is built, the general processing platform generates data, the XDMA maps the interrupt into MSI or Legacy interrupt, and transmits the data through the PCIe high-speed interface;

step two, further data is transmitted to DDR3 of a hardware acceleration platform for caching through the XDMA;

and step three, judging whether the MM2S AXIDMA generates interruption or not, if so, reading data from the DDR3 of the hardware acceleration platform, transmitting the data into an internal physical layer through a reserved pin for processing, and entering the step four. Otherwise, the data is not processed in the DDR3 memory.

And step four, continuously judging whether the S2MM AXIDMA generates an interrupt, if so, transmitting the data into the DDR3 memory through the PCIe high-speed interface by the S2MM AXIDMA, otherwise, not processing the data in the DDR3 memory.

And step five, the XDMA reads out data from the DDR3 memory and sends the data back to the general processing platform, and the data are further transmitted to the radio frequency unit. .

The invention has the advantages that:

a satellite virtualization gateway station transmission architecture based on hardware acceleration divides a functional module again on the basis that a traditional gateway station uses a general processor to process signals. The physical layer module with high calculation repeatability and complex calculation is placed on a hardware acceleration platform for processing, the module with small calculation amount is reserved in a general processing platform, and a PCIe high-speed interface is used for realizing the connection of the two modules. Therefore, the method has the flexibility of the general processor and the computing advantage of the hardware accelerator, reduces the burden of the general processor, reduces the time for transmitting data across platforms as much as possible, and effectively improves the processing capacity of the system and the real-time performance of the protocol.

Drawings

FIG. 1 is a schematic diagram of a hardware acceleration-based satellite virtualization gateway station transmission architecture according to the present invention;

fig. 2 is an internal structural diagram of a PCIe high-speed interface employed in the satellite virtualization gateway station transmission architecture according to the present invention;

fig. 3 is a flow chart illustrating the operation principle of the satellite virtualization gateway station transmission architecture based on hardware acceleration according to the present invention.

Detailed Description

The present invention will be described in detail with reference to the accompanying drawings.

A satellite virtualization gateway station transmission architecture (The architecture of satellite virtual gateway based on hardware acceleration) solves The differentiated functional requirements of different services through a cloud architecture design of RAN function virtualization, resource clouding and management elasticization, and supports The rapid elastic capacity expansion and deployment capabilities of a network. Meanwhile, aiming at the difference of different functional modules in requirements of real-time performance, time delay and the like, the functional modules are respectively deployed on the general processing platform and the hardware acceleration platform to further release the resources of the general processing platform, reduce the processing time delay of the system and improve the performance-power ratio so as to meet the requirements of the satellite mobile communication system on the processing time delay. The application of virtualization technology in satellite system and gateway station can support various transmission systems, make full and efficient use of resources, bring much convenience to the management, maintenance and capacity expansion of the system and the evolution and upgrade of communication standard, and have important significance to the network architecture design, compatible signal and protocol processing and interconnection and intercommunication with ground network of the next generation satellite mobile communication system.

The satellite virtualization gateway station transmission architecture based on hardware acceleration processes a functional module with higher complexity, such as a link layer, by using a general processing platform. And for functional modules with larger calculation amount and higher requirement on time delay, such as a physical layer, the functional modules are put into a hardware acceleration platform for processing. And then the PCIe high-speed interface is connected with the general processing platform and the hardware acceleration platform to realize the communication of the whole architecture. As shown in fig. 1, comprises a radio frequency unit and a gateway station which are connected; the gateway station comprises a clock synchronization unit, a general processing platform and a hardware acceleration platform;

Data is transmitted by the general purpose processing platform to a physical layer in the hardware acceleration platform for processing through the PCIe high speed interface based on the XDMA. The internal architecture of the PCIe high-speed interface is shown in fig. 2, and includes: XDMA (Xing distributed media architecture), MM2S axidma (memory map to stream) and S2MM axidma (stream to memory map);

the concrete configuration is as follows:

clicking block design in design software vivado to enter a circuit design interface, selecting a DMA Subsystem for PCI Express IP core, namely XDMA, and configuring the XDMA; the IP core is high-performance and configurable SG mode DMA applicable to PCIE2.0 and PCIE3.0, and provides an AXI4 interface or an AXI4-Stream interface which can be selected by a user. The AXI4 interface is typically configured to be added to the system for bus interconnect for large data volumes asynchronous transfer, typically with DDR, and the AXI4-Stream interface is used for low latency data streaming.

The configuration of the XDMA is specifically as follows:

lane Width: x2 is selected.

Max Link Speed: 5.0GT/s, PCIE2.0, is selected.

Reference Clock: 100MHz, reference clock 100 MHz.

DMA Interface Option: the interface selects the AXI4 interface.

AXI Data Width: the 128bit, AXI4 data bus width is 128 bit.

AXI Clock: the 125M, AXI4 interface clock is 125 MHz.

The interrupt selects an MSI interrupt.

Finally, the address of the XDMA is configured: this address is the mapping relation of the PCIe control interface Bar address to the AXI address, and since the AXI-DMA register base address and the user register base address both start with 0x44a00000 in the engineering, the application maps the address of the PCIe control interface Bar address to the AXI bus to 0x44a 00000.

After the configuration is completed, the modules are connected in block design to complete the construction of the logic circuit. And a pin is reserved for each of the S2MM AXI-DMA and the MM2S AXI-DMA, so that a signal processing module of a physical layer can be added conveniently, a complete loop can be formed by the system after the addition, and the generated bit stream file can be used by programming into a hardware acceleration board card.

when the transmission flow begins, MM2S AXIDMA will generate an interrupt to notify the PCIe high-speed interface to perform data transmission, at this time, XDMA will map the user interrupt as MSI or Legacy interrupt, and transmit the data to the program of the general processing platform through the PCIe high-speed interface. The data will enter DDR3 of the hardware processing platform to be buffered, then enter the physical layer module for processing through MM2S AXIDMA, the processed data will be sent back to DDR3 through S2MM AXIDMA, at this time, S2MM AXIDMA will generate interrupt to inform PCIe to go back data, and finally the data will be sent back to the general processing platform from DDR 3.

As shown in fig. 3, the specific steps are as follows:

step one, after the logic circuit is built, the general processing platform generates data, the XDMA maps the interrupt into MSI or Legacy interrupt, and the MSI or Legacy interrupt is transmitted through a PCIe high-speed interface;

and step three, judging whether the MM2S AXIDMA generates interruption or not, if so, reading data from the DDR3 of the hardware acceleration platform, transmitting the data into a physical layer in the hardware acceleration platform through a reserved pin for processing, and entering step four. Otherwise, the data is not processed in the DDR3 memory.

After the whole system is built, an upper computer program of a general processor end transmits data into DDR3 through PCIe IP built by XDMA, at the moment, a drive file XDMA0_ h2c _0(1) is used, the file is a Host to Card channel of the XDMA, namely a write data channel, the data of a Host is transmitted to a hardware acceleration transaction Card, the Host uses "/dev/XDMA 0_ events _ 0" after acquiring AXI-DMA interrupt information, after the interrupt information is transmitted by usr _ irq _ req at one side of the hardware acceleration Card, the XDMA receives interrupt and enters an interrupt function, the interrupt function calls an interrupt lower half part work, the interrupt service program is called in the work, the interrupt service program sets a wake-up condition to 1, and then wake-up the previously-hung read operation. At this time, the data can enter the corresponding processing module for processing, the data is sent back to the DDR3 after being processed, and finally the data is sent back to the general processor end through the XDMA, at this time, a drive file XDMA0_ c2h _0(1) is used, wherein the drive file xdMA Card to Host channel, namely a read data channel, transmits the data of the hard board Card to the Host.

The present invention relates to the problem of signal processing for virtualized gateway stations. On the basis of the traditional gateway station architecture, a hardware acceleration board card is used for signal processing of a physical layer, and the processed signal is transmitted to a server for subsequent signal processing. For the problem of signal processing instantaneity, a PCIe high-speed interface is selected and a satellite virtualization gateway station architecture transmission architecture based on hardware acceleration is provided to improve the transmission capability of the whole system.

Claims

1. A satellite virtualization gateway station transmission architecture based on hardware acceleration is characterized by comprising a radio frequency unit and a gateway station which are connected; the gateway station comprises a clock synchronization unit, a general processing platform and a hardware acceleration platform;

the clock synchronization unit is respectively connected with the general processing platform and the hardware acceleration platform; the general processing platform is communicated with the hardware acceleration platform through an improved PCIe high-speed interface; meanwhile, the general processing platform is connected with the radio frequency unit;

the hardware acceleration platform comprises a DDR3 internal memory and a physical layer;

the PCIe high-speed interface comprises: XDMA, MM2S AXIDMA and S2MM AXIDMA;

the concrete configuration is as follows:

the method specifically comprises the following steps:

lane Width: selecting X2;

max Link Speed: selecting 5.0GT/s, namely PCIE 2.0;

reference Clock: 100MHz, reference clock 100 MHz;

DMA Interface Option: selecting an AXI4 interface as the interface;

AXI Data Width: 128bit, AXI4 data bus width is 128 bit;

AXI Clock: 125M, namely the AXI4 interface clock is 125 MHz;

interrupting and selecting MSI interruption;

then, AXI-DMA configuration is carried out, and two AXI-DMAs are selected for the whole structure, one is in charge of S2MM and the other is in charge of MM 2S; the Memory Map Data Width of the two is set to 64, and the Width of an AXI4 interface is increased;

finally, the address of the XDMA is configured: mapping PCIe control interface Bar address to AXI bus address to 0x44a 00000;

after the configuration is completed, connecting each module in block design to complete the construction of the logic circuit; the S2MM AXI-DMA and the MM2S AXI-DMA respectively reserve one pin so as to be convenient for being connected with a physical layer; after the system is added, a complete loop can be formed, and the generated bit stream file can be used by programming into a hardware acceleration board card.

2. The hardware-accelerated satellite-virtualized gateway station transport architecture of claim 1, wherein the hardware-accelerated satellite-virtualized gateway station transport architecture operates according to the following principle:

step three, judging whether the MM2S AXIDMA generates interruption or not, if so, reading out data from the DDR3 of the hardware acceleration platform, transmitting the data into an internal physical layer through a reserved pin for processing, and entering step four; otherwise, the data is not processed in the DDR3 memory;

step four, continuously judging whether the S2MM AXIDMA generates interruption or not, if so, transmitting the data into a DDR3 memory through a PCIe high-speed interface by the S2MM AXIDMA, otherwise, not processing the data in the DDR3 memory;

and step five, the XDMA reads out data from the DDR3 memory and sends the data back to the general processing platform, and the data are further transmitted to the radio frequency unit.