CN114443322A

CN114443322A - Inter-core communication method, inter-core communication device, electronic equipment and storage medium

Info

Publication number: CN114443322A
Application number: CN202210067920.XA
Authority: CN
Inventors: 王守宽; 李东华; 胡鑫裕
Original assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Current assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Priority date: 2022-01-20
Filing date: 2022-01-20
Publication date: 2022-05-06

Abstract

The embodiment of the application provides an inter-core communication method and device, electronic equipment and a storage medium, wherein the electronic equipment comprises a sending core, N receiving cores, a shared memory and a register set, the register set comprises a first register and N second registers, and the second registers correspond to the receiving cores one to one; the method comprises the following steps: the sending core reads the N first values and writes target data into the shared content according to the second value and the N first values; and triggers an interrupt event. According to the method and the device, the shared memory and the register group jointly form the exclusive hardware channel for the inter-core communication in the message broadcasting mode, so that the sending core realizes inter-core communication behaviors with the N receiving cores through the exclusive hardware channel, the hardware cost is reduced, the number of times of triggering interruption is reduced, the functions of memory multiplexing and interruption multiplexing under the condition of one-to-many transmission are realized, and the inter-core communication efficiency is improved.

Description

Inter-core communication method, inter-core communication device, electronic equipment and storage medium

Technical Field

The present application relates to the field of communications technologies, and in particular, to an inter-core communication method and apparatus, an electronic device, and a storage medium.

Background

With the development of semiconductor technology, the functions of chips are more and more complex. A System on Chip (SoC) Chip includes not only a plurality of cores, but also a plurality of cores are heterogeneous, so that there is a large amount of inter-core communication, and the transmission efficiency and stability are generally strictly required. Therefore, the inter-core communication is an important data channel, and the efficiency of the inter-core communication becomes a main factor influencing the performance of the chip.

Disclosure of Invention

The embodiment of the application provides an inter-core communication method and device, electronic equipment and a storage medium, which can improve inter-core communication efficiency in a message broadcast mode scene and reduce hardware cost.

In a first aspect, an embodiment of the present application provides an inter-core communication method, which is applied to an electronic device, where the electronic device includes a sending core, N receiving cores, a shared memory, and a register group, where the register group includes a first register and N second registers, the second registers are in one-to-one correspondence with the receiving cores, and N is a positive integer; the method comprises the following steps:

the sending core reads N first values, and each first value is the value of a second register;

writing target data into the shared content by the sending core according to a second value and the N first values, wherein the second value is a value of the first register stored by the sending core;

the sending core triggers an interrupt event.

In a second aspect, an embodiment of the present application provides an inter-core communication method, which is applied to an electronic device, where the electronic device includes a sending core, N receiving cores, a shared memory, and a register set, where the register set includes a first register and N second registers, the second registers are in one-to-one correspondence with the receiving cores, and N is a positive integer; the method comprises the following steps:

if an interrupt event is detected, the ith receiving core reads a second value, wherein the second value is the value of the first register, and i is a positive integer less than or equal to N;

and the ith receiving core reads target data from the shared memory according to the second value and a target first value, wherein the target first value is a value of a corresponding second register stored by the ith receiving core.

In a third aspect, an inter-core communication apparatus is provided in an embodiment of the present application, and is applied to an electronic device, where the electronic device includes a sending core, N receiving cores, a shared memory, and a register set, where the register set includes a first register and N second registers, the second registers are in one-to-one correspondence with the receiving cores, and N is a positive integer; the device comprises:

a reading unit for reading N first values, each of which is a value of the second register;

a writing unit, configured to write target data into the shared content according to a second value and the N first values, where the second value is a value of the first register stored by the sending core;

the trigger unit is used for triggering an interrupt event according to a target instruction, wherein the target instruction is an instruction generated aiming at the sending operation of a user.

In a fourth aspect, an embodiment of the present application provides an inter-core communication apparatus, which is applied to an electronic device, where the electronic device includes a sending core, N receiving cores, a shared memory, and a register set, where the register set includes a first register and N second registers, the second registers are in one-to-one correspondence with the receiving cores, and N is a positive integer; the device comprises:

a reading unit, configured to read a second value if an interrupt event is detected, where the second value is a value of the first register;

the reading unit is further configured to read target data from the shared memory according to the second value and a target first value, where the target first value is a value of a corresponding second register stored by the ith receiving core.

In a fifth aspect, an embodiment of the present application provides an electronic device, including a processor, a memory, a communication interface, and one or more programs, where the one or more programs are stored in the memory and configured to be executed by the processor, and the program includes instructions for executing the steps of any of the methods in the first aspect or the second aspect of the embodiment of the present application.

In a sixth aspect, the present application provides a computer-readable storage medium, where the computer-readable storage medium stores a computer program for electronic data exchange, where the computer program makes a computer perform part or all of the steps described in any one of the methods of the first aspect or the second aspect of the present application.

In a seventh aspect, this application provides a computer program product, where the computer program product includes a non-transitory computer-readable storage medium storing a computer program, where the computer program is operable to cause a computer to perform some or all of the steps as described in any of the methods of the first aspect or the second aspect of this application. The computer program product may be a software installation package.

In the embodiment of the application, the method is applied to the electronic equipment, and the electronic equipment comprises a sending core, N receiving cores, a shared memory and a register set, wherein the register set comprises a first register and N second registers, the second registers are in one-to-one correspondence with the receiving cores, and N is a positive integer; the sending core reads N first values, and each first value is the value of a second register; writing target data into the shared content according to a second value and the N first values, wherein the second value is a value of a first register stored by the sending core; and triggers an interrupt event. According to the method and the device, the shared memory and the register group jointly form the exclusive hardware channel for the inter-core communication in the message broadcasting mode, so that the sending core realizes inter-core communication behaviors with the N receiving cores through the exclusive hardware channel, the hardware cost is reduced, the number of times of triggering interruption is reduced, the functions of memory multiplexing and interruption multiplexing under the condition of one-to-many transmission are realized, and the inter-core communication efficiency is improved.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure;

fig. 2a is a schematic view of inter-core communication based on memory sharing according to an embodiment of the present disclosure;

FIG. 2b is a schematic diagram of inter-core communication based on DMA transfer according to an embodiment of the present application;

fig. 3 is a schematic view of an inter-core communication application scenario provided in an embodiment of the present application;

fig. 4 is a schematic structural diagram of an inter-core communication system according to an embodiment of the present application;

FIG. 5 is a schematic structural diagram of a hardware channel according to an embodiment of the present disclosure;

FIG. 6 is a schematic diagram of inter-core communication hardware architecture interaction according to an embodiment of the present disclosure;

fig. 7 is a flowchart illustrating an inter-core communication method according to an embodiment of the present application;

fig. 8 is a schematic diagram of a message format of target data according to an embodiment of the present application;

fig. 9 is a schematic flowchart of another inter-core communication method according to an embodiment of the present application;

fig. 10 is a schematic diagram of an inter-core communication apparatus according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings.

In order to better understand the scheme of the embodiments of the present application, the following first introduces the related terms and concepts that may be involved in the embodiments of the present application.

A multi-core processor is a processor that integrates two or more complete computing engines (cores) into one processor, and the processor can support multiple processors on a system bus, and a bus controller provides all bus control signals and command signals.

The register, the function of which is to store binary codes, is formed by combining flip-flops with storage functions. One flip-flop can store 1-bit binary codes, so a register for storing n-bit binary codes needs to be formed by n flip-flops. Registers can be divided into two broad categories, basic registers and shift registers, according to their functions. The basic registers can only be fed with data in parallel and can only be output in parallel. The data in the shift register can be shifted to the right or left bit by bit in sequence under the action of shift pulses, and the data can be input in parallel and output in parallel, can be input in series and output in series, can be input in parallel and output in series, or can be input in series and output in parallel, so that the method is very flexible and has wide application.

Fig. 1 shows a schematic structural diagram of an electronic device 100. The electronic device 100 may include a processor 110, an external memory interface 120, an internal memory 121, a Universal Serial Bus (USB) interface 130, a charge management module 140, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a sensor module 180, and the like.

It is to be understood that the illustrated structure of the embodiment of the present application does not specifically limit the electronic device 100. In other embodiments of the present application, electronic device 100 may include more or fewer components than shown, or some components may be combined, some components may be split, or a different arrangement of components. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

Processor 110 may include a plurality of processing units, such as: the processor 110 may include an Application Processor (AP), a modem processor, a Graphics Processing Unit (GPU), an Image Signal Processor (ISP), a controller, a video codec, a Digital Signal Processor (DSP), a baseband processor, and/or a neural-Network Processing Unit (NPU), etc. The different processing units may be separate components or may be integrated into multiple processors. The controller can generate an operation control signal according to the instruction operation code and the time sequence signal to complete the control of instruction fetching and instruction execution. In other embodiments, a memory may also be provided in processor 110 for storing instructions and data. Illustratively, the memory in the processor 110 may be a cache memory. The memory may hold instructions or data that have just been used or recycled by the processor 110. If the processor 110 needs to reuse the instruction or data, it can be called directly from the memory. This avoids repeated accesses and reduces the latency of the processor 110, thereby increasing the efficiency with which the electronic device 100 processes data or executes instructions.

In some embodiments, processor 110 may include one or more interfaces. The interface may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit audio (I2S) interface, a Pulse Code Modulation (PCM) interface, a universal asynchronous receiver/transmitter (UART) interface, a Mobile Industry Processor Interface (MIPI), a general-purpose input/output (GPIO) interface, a SIM card interface, a USB interface, and/or the like.

It should be understood that the interface connection relationship between the modules illustrated in the embodiments of the present application is only an illustration, and does not limit the structure of the electronic device 100. In other embodiments of the present application, the electronic device 100 may also adopt different interface connection manners or a combination of multiple interface connection manners in the above embodiments.

The charging management module 140 is configured to receive charging input from a charger. The charger may be a wireless charger or a wired charger. In some wired charging embodiments, the charging management module 140 may receive charging input from a wired charger via the USB interface 130.

The wireless communication function of the electronic device 100 may be implemented by the antenna 1, the antenna 2, the mobile communication module 150, the wireless communication module 160, a modem processor, a baseband processor, and the like.

The

antennas

1 and 2 are used for transmitting and receiving electromagnetic wave signals. Each antenna in the electronic device 100 may be used to cover a single or multiple communication bands. Different antennas can also be multiplexed to improve the utilization of the antennas. For example: the antenna 1 may be multiplexed as a diversity antenna of a wireless local area network. In other embodiments, the antenna may be used in conjunction with a tuning switch.

The mobile communication module 150 may provide a solution including 2G/3G/4G/5G wireless communication applied to the electronic device 100. The mobile communication module 150 may include at least one filter, a switch, a power amplifier, a Low Noise Amplifier (LNA), and the like. The mobile communication module 150 may receive the electromagnetic wave from the antenna 1, filter, amplify, etc. the received electromagnetic wave, and transmit the electromagnetic wave to the modem processor for demodulation. The mobile communication module 150 may also amplify the signal modulated by the modem processor, and convert the signal into electromagnetic wave through the antenna 1 to radiate the electromagnetic wave. In some embodiments, at least some of the functional modules of the mobile communication module 150 may be disposed in the processor 110. In some embodiments, at least some of the functional modules of the mobile communication module 150 may be disposed in the same device as at least some of the modules of the processor 110.

The wireless communication module 160 may provide a solution for wireless communication applied to the electronic device 100, including Wireless Local Area Networks (WLANs) (e.g., wireless fidelity (Wi-Fi) networks), bluetooth (blue tooth, BT), Global Navigation Satellite System (GNSS), Frequency Modulation (FM), Near Field Communication (NFC), Infrared (IR), UWB, and the like. The wireless communication module 160 may be one or more devices integrating at least one communication processing module. The wireless communication module 160 receives electromagnetic waves via the antenna 2, performs frequency modulation and filtering processing on electromagnetic wave signals, and transmits the processed signals to the processor 110. The wireless communication module 160 may also receive a signal to be transmitted from the processor 110, perform frequency modulation and amplification on the signal, and convert the signal into electromagnetic waves through the antenna 2 to radiate the electromagnetic waves.

The external memory interface 120 may be used to connect an external memory card, such as a Micro SD card, to extend the memory capability of the electronic device 100. The external memory card communicates with the processor 110 through the external memory interface 120 to implement a data storage function. For example, files such as music, video, etc. are saved in an external memory card.

Internal memory 121 may be used to store one or more computer programs, including instructions. The processor 110 may execute the above instructions stored in the internal memory 121, so as to enable the electronic device 100 to perform the method for displaying page elements provided in some embodiments of the present application, and various applications, data processing, and the like. The internal memory 121 may include a program storage area and a data storage area. Wherein, the storage program area can store an operating system; the storage program area may also store one or more applications (e.g., gallery, contacts, etc.), and the like. The storage data area may store data (e.g., photos, contacts, etc.) created during use of the electronic device 100, and the like. Further, the internal memory 121 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic disk storage components, flash memory components, Universal Flash Storage (UFS), and the like. In some embodiments, the processor 110 may cause the electronic device 100 to execute the method for displaying page elements provided in the embodiments of the present application and other applications and data processing by executing instructions stored in the internal memory 121 and/or instructions stored in a memory provided in the processor 110.

The sensor module 180 may include a pressure sensor 180A, a gyro sensor 180B, an air pressure sensor 180C, a magnetic sensor 180D, an acceleration sensor 180E, a distance sensor 180F, a proximity light sensor 180G, a fingerprint sensor 180H, a temperature sensor 180J, a touch sensor 180K, an ambient light sensor 180L, a bone conduction sensor 180M, and the like.

With the development of semiconductor technology, the functions of chips in electronic devices are becoming more and more complex. The inside of one SoC chip not only comprises a plurality of cores, but also a plurality of cores are heterogeneous. The processor cores are not designed for mutual communication, a large number of inter-core communication phenomena exist in each module of the Modem chip, such as a protocol stack, a physical layer, a data plane and the like, and the inter-core communication is an essential part of the chip. Therefore, the inter-core communication is an important data channel, and the efficiency of the inter-core communication becomes a main factor influencing the performance of the chip. The inter-core communication solution requires a compact set of software and hardware, and the current solution is mainly performed in a shared memory mode and a DMA (direct memory access) transmission mode. The shared memory manner is to use the shared memory as a medium, and notify the other party by using inter-core interrupt, and the inter-core communication process is shown in fig. 2 a. The DMA transfer method uses DMA transfer as a medium, and notifies the other party by using inter-core interrupt, and the inter-core communication process is shown in fig. 2 b.

As shown in fig. 2a and fig. 2b, in order to implement communication between heterogeneous multiple cores, in an application scenario as shown in fig. 3, that is, in a message broadcast model (a sending core sends message content to N receiving cores), the sending core needs to send the same message multiple times or configure a DMA multiple times, which increases the load of the sending core and increases the time from the message generation to the message reception of the last 1 receiving core. And the current scheme needs to deploy multiple shared memories or multiple channels of DMA, which increases the hardware cost. When the number of the same 1 message needing to be sent to the receiving core is reduced, the deployed hardware generates waste, and the utilization rate of the hardware is reduced.

In order to solve the above problems, the present application provides an inter-core communication method, where N receiving cores, a shared memory, and a register group together form an inter-core communication dedicated hardware channel oriented to a message convergence mode, so that when a core can implement an inter-core communication behavior with the N receiving cores through a specific hardware channel, only one message sending and memory application operation needs to be executed, and one interrupt is triggered, thereby completing one-to-many inter-core communication, and significantly improving inter-core communication efficiency while reducing hardware cost.

Referring to fig. 4, fig. 4 is a schematic structural diagram of an inter-core communication system according to an embodiment of the present disclosure. As shown in fig. 4, the system includes a sending core, N receiving cores, and a hardware channel including a shared memory and a register set. The sending cores are connected with the hardware channels, each receiving core is also connected with the hardware channels, and a memory area (shared memory in the hardware channels) shared by the sending cores and the N receiving cores is established. When the sending core needs to communicate with the N receiving cores, the sending core writes data into the shared memory according to the values of the registers in the register group, and triggers an interrupt event according to the instruction of the user. And after each receiving core detects an interrupt event, reading data from the shared memory and processing the data according to the value of the register in the register group.

As shown in fig. 5, fig. 5 is a schematic structural diagram of a hardware channel provided in an embodiment of the present application. As shown in fig. 5, the shared memory and the register set jointly form the hardware channel in the present application, and the shared memory is a segment of ring buffer for storing the message content. The register set includes a control register for managing writing and/or reading of the shared memory by the sending or receiving core and an interrupt register. The interrupt register is used for recording the interrupt state and triggering interrupt, wherein the interrupt is triggered by the sending core, and the interrupt is cleared by the receiving core. The interrupt register may be bit-operable, and an interrupt register may include N bits, each bit corresponding to an interrupt flag, each interrupt flag corresponding to 1 receiving core. The receiving core may determine whether there is an interrupt event by reading the value of the corresponding bit in the interrupt register.

By way of example, the control registers may include N read pointer registers RPR and a write pointer register WPR. The N read pointer registers RPR are general purpose registers, and each read pointer register is used for storing a read pointer of a receiving core corresponding to a ring buffer in a hardware channel. The write pointer register WPR is a general purpose register that has exclusive access to store the write pointer of the ring buffer within the hardware channel.

In the application, the message content in the shared memory can be managed by the read pointer and the write pointer, and the sending core and/or the receiving core can realize control of the transmission process by reading or writing the value of the read pointer register RPR and/or the write pointer register WPR. When the sending core needs to communicate with the N receiving cores, the sending core may determine whether the shared memory has space to write according to a minimum value of the plurality of read pointers and a write pointer maintained by the sending core, and if so, the sending core writes data that needs to be sent into the shared memory. Wherein the write pointers managing the message content in the shared memory are not maintained by the sending core but are obtained by reading a shared write pointer register WPR, but the N read pointers managing the message content in the shared memory are maintained by the corresponding receiving core. Therefore, after the data is written into the shared memory, the sending core can trigger an interrupt event according to the instruction of the user.

Specifically, as shown in fig. 6, the sending core respectively reads the values of the N read pointer registers RPR, selects the minimum value from the N read pointer registers RPR values, and then calculates the length of the data or the number of the data currently stored in the shared memory according to the minimum value of the read pointer register RPR and the minimum value of the write pointer register WRP, and further calculates the current remaining storage space of the shared memory according to the storage size of the shared memory. Then the sending core judges whether the current residual memory space can be written with the message content. And if the current residual storage space is enough to write the message content of the sending core, the sending core writes the message content into the storage space pointed by the write pointer of the shared memory, updates the write pointer according to the data length or the data quantity of the written message content, and writes the updated write pointer into the write pointer register WPR. And then triggering interruption by the sending core according to the instruction of the user, and writing an interruption mark into a bit corresponding to the receiving core in the interruption register. Each of the N receiving cores detects whether there is an interrupt event in the hardware channel when receiving the check, that is, each receiving core periodically reads the value of a corresponding bit in the interrupt register. When the value of its corresponding bit is an interrupt flag, then an interrupt event is considered to exist. Therefore, each receiving core reads the value of the corresponding read pointer register RPR again, determines the address of the content of the read message and the data length or the data quantity according to the write pointer and the read pointer maintained by the write pointer, further reads the content of the message in the storage space pointed by the corresponding read pointer, and updates the corresponding read pointer register RPR according to the data length or the data quantity of the read content of the message. And finally, each receiving core respectively processes the read message content.

In the embodiment of the application, the message broadcast transmission mechanism is realized through a hardware channel formed by the shared memory and the register group, hardware deployment and software operation such as the shared memory and the register are reduced, transmission efficiency is improved, and hardware cost is reduced. And connection establishment and memory application can be realized once through the hardware channel, and only one interruption is triggered, so that the inter-core communication efficiency of the message broadcasting mode is remarkably improved.

Referring to fig. 7, fig. 7 is a flowchart illustrating an inter-core communication method according to an embodiment of the present application, applied to the inter-core communication system shown in fig. 2 a. As shown in fig. 7, the present inter-core communication method includes the following operations.

S710, the sending core reads N first values, and each first value is the value of the second register.

In the application scenario of the message broadcast mode, when a sending core needs to communicate with N receiving cores, the sending core and the N receiving cores respectively establish connections with a hardware channel, and apply for shared memories of the sending core and the N receiving cores. And then, inter-core communication under the application scene of the message broadcasting mode is realized according to the inter-core communication method provided by the application.

The second register may be the read pointer register RPR. In order to obtain whether a storage space exists in the shared memory at present to store data sent by the sending core, the sending core may read a write pointer for managing message content in the shared memory through the value of the write pointer register WPR, and read a read pointer for managing message content in the shared memory through the value of the read pointer register RPR. That is, the first value is the memory address pointed to by the read pointer of the message content in the shared memory. Therefore, by reading the N first values, the sending core can obtain the address of the shared memory to which data is written.

S720, the sending core writes target data into the shared content according to a second value and the N first values, where the second value is a value of the first register stored by the sending core.

In this embodiment, the first register may be the write pointer register WPR, and the second value is a memory address pointed to by a write pointer of message content in the shared memory. The sending core may check the remaining space of the shared memory by managing a difference between a read pointer and a write pointer of the message content in the shared memory, to determine whether there is a storage space in the shared memory to store the data sent by the sending core. When the shared memory has a space for storing the data sent by the sending core, the sending core can write the target data which needs to be sent into the remaining space of the shared memory.

For example, if the remaining storage space of the shared memory is insufficient to store the data sent by the sending core, the sending core may generate and display a notification message to notify the user that the currently allocated shared content is insufficient to store the data to be sent, and whether to give up sending of the data or reallocate the memory; or the sending core reappears a shared memory shared by the sending core and the N receiving cores or the storage space of the current shared memory is expanded to store data.

Optionally, the writing, by the sending core, target data into the shared content according to the second value and the N first values includes: the sending core selects a minimum first value from the N first values; the sending core calculates a first difference value, wherein the first difference value is a difference value between the storage size of the shared memory and a second difference value, and the second difference value is a difference value between the second value and the minimum first value; if the first difference is smaller than the data length of the target data, the sending core repeatedly reads the N first values; and if the first difference is larger than or equal to the data length of the target data, the sending core writes the target data into a storage space corresponding to the second value in the shared memory.

Because the shared memory comprises N read pointers, and each read pointer is respectively maintained by a corresponding receiving core, in order to correctly calculate the remaining storage memory of the shared memory, a sending core can firstly select a minimum first value from N first values, and then calculate a second difference between a second value and the minimum first value, because the shared memory is a segment of ring buffer, if the second difference is equal to 1, the storage space of the shared memory is represented to store data, and no remaining space exists, and the data of the ith sending core cannot be stored for inter-core communication; when the second difference is greater than 1, it indicates that the data is stored in the shared content. The ith sending core can further calculate the remaining space of the shared memory to judge whether the shared memory can store the data to be sent by the ith sending core.

Specifically, when the second difference is greater than 1, the sending core further calculates a first difference between the storage size of the shared memory and the second difference, where the first difference is the remaining storage space of the shared memory. If the remaining storage space of the shared memory is smaller than the storage space occupied by the target data sent by the sending core, it indicates that the remaining storage space of the shared memory is not enough to store the storage space occupied by the target data, and the sending core may repeatedly read the first value to perform calculation until the remaining storage space of the shared memory is larger than or equal to the storage space occupied by the target data.

Further, if the first difference is greater than or equal to the data length of the target data, that is, when the remaining storage space of the shared memory is greater than or equal to the storage space occupied by the target data, the sending core may write the target data that needs to be sent into the storage space pointed by the write pointer.

Optionally, the method further includes: after writing the target data into the storage space corresponding to the second value in the shared memory, the sending core writes a third value into the first register, where the third value is a sum of the second value and a data length of the target data.

After the first sending core writes the target data into the shared memory, the remaining storage space of the shared memory changes, and in order to enable the sending core to subsequently write the data to be sent into the shared memory, the sending core also needs to update the value of the write pointer register WPR.

Specifically, the sending core updates the write pointer according to the storage space occupied by the target data written into the shared memory this time, specifically, the sum of the second value and the data length of the target data is written into the write pointer register WPR, so that the write pointer managing the message content of the shared memory points to the next storage space behind the target data written by the sending core.

In the embodiment of the application, the write pointer maintained by the sending core and the read pointer maintained by the N receiving cores are used for respectively maintaining one read pointer, so that the sending core can write the data sent to the N receiving cores into the shared memory at one time according to the current write pointer and the read pointer, one-to-many inter-core communication is realized, and the problem that the sending core needs to send the same message for many times or configure the DMA for many times in a message broadcasting mode is solved.

And S730, triggering an interrupt event by the sending core.

In the embodiment of the present application, after the sending core writes the target data into the shared memory, it may trigger an interrupt event according to an actual situation. For example, the sending core triggers an interrupt event according to user settings, system settings, or user selections.

For example, the sending core may trigger an interrupt event according to a target instruction generated by a sending operation of a user, or may directly trigger the interrupt event after the sending core writes all target data into the shared memory, which is not limited in this embodiment of the present application.

The register set further includes a third register, where the third register is the interrupt register, and the interrupt register includes N bits, and each bit corresponds to an interrupt of one receiving core. Based on the value of each bit in the interrupt register, the N receiving cores may determine whether an interrupt event exists.

In the embodiment of the application, different storage contents are allocated to some general purpose registers, and the general purpose registers, the interrupt registers and the shared memory form a special inter-core communication hardware channel facing to a message broadcasting mode, so that the sending core realizes inter-core communication with the N receiving cores through the special hardware channel, thereby reducing the times of sending messages by the sending core, realizing the function of memory multiplexing under the condition of one-to-many transmission, and improving the inter-core communication efficiency.

Optionally, the sending core triggers an interrupt event, including: and the sending core writes interrupt flags into the bit positions corresponding to the N receiving cores in the third register respectively.

Specifically, each bit in the interrupt register corresponds to an interrupt of one receiving core. If the sending core needs to communicate with the receiving core, the bit corresponding to the receiving core in the interrupt register may be written into the interrupt flag to trigger an interrupt event of the receiving core. Therefore, when the sending core needs to perform inter-core communication with the N receiving cores, the bit bits in the interrupt registers corresponding to the N receiving cores can be written into the interrupt flags, so that the sending core can realize the inter-core communication with the N receiving cores by sending data once to trigger one interrupt, the hardware cost is reduced, and the inter-core communication efficiency is improved.

S740, if an interrupt event is detected, reading a second value by the ith receiving core, where the second value is the value of the first register, and i is a positive integer smaller than or equal to N.

Each receiving core can detect whether an interrupt event exists in the hardware channel in real time, and when the receiving core detects the interrupt event, the receiving core enters interrupt service. Specifically, the receiving core calculates available data to be read by the receiving core in the shared memory according to a read pointer for managing the message content of the shared memory and a write pointer for managing the message content of the shared memory, which are maintained by the receiving core, so that the value of the write pointer register WPR of the i-th receiving core obtains a second value.

Optionally, before reading the second value, the method further includes: the ith receiving core reads the value of a target bit in the third register, and judges whether the value of the target bit is an interrupt flag or not, wherein the target bit is a bit corresponding to the ith receiving core; if the value of the target bit is the interrupt flag, the receiving core initializes the target bit.

In this embodiment, after detecting the interrupt event, the ith receiving core may read the write pointer from the write pointer register WPR to perform a data read operation, and clear the interrupt flag corresponding to the ith receiving core. Specifically, the receiving core initializes the write pointer register WPR after reading the value of the write pointer register WPR, so that the ith receiving core can perform next inter-core communication.

And S750, the ith receiving core reads target data from the shared memory according to the second value and a target first value, wherein the target first value is a value of a corresponding second register stored by the ith receiving core.

In this embodiment of the present application, the ith receiving core may determine the size of the data to be read according to a difference between a read pointer for managing the message content of the shared memory and a write pointer for managing the message content of the shared memory, which correspond to the ith receiving core. The target first value is a value of a read pointer register RPR for storing a read pointer corresponding to the ith receiving core, and represents a first address of stored data in the shared memory. The second value is a value of a write pointer register WPR storing a write pointer, and represents a first address of a memory space in the shared memory, where data can be written.

Optionally, the reading, by the ith receiving core, the target data from the shared memory according to the second value and the target first value includes: calculating a third difference value by the ith receiving core, wherein the third difference value is the difference value between the second value and the target first value; the ith receiving core determines the data length of the target data according to the third difference; and the ith receiving core reads the target data with the data length of the third difference from the storage space corresponding to the target first value in the shared memory.

Specifically, the i-th receiving core calculates a difference between the value of the write pointer register WPR and the value of the read pointer register RPR corresponding to the i-th receiving core, and may obtain the data size of the i-th receiving core in the inter-core communication. And the ith receiving core reads the data with the third difference data length from the memory address pointed by the value of the read pointer register RPR in the shared memory.

Optionally, the method further includes: and the ith receiving core writes the second value into a target second register, wherein the target second register is a second register corresponding to the ith receiving core, and the first value is obtained.

Further, after the ith receiving core reads the target data from the shared memory, the read pointer maintained by the ith receiving core may change, and in order to ensure that the next inter-core communication of the ith receiving core is normal, the ith receiving core also needs to update the value of the read pointer register RPR.

Specifically, the ith receiving core updates the storage space pointed by the read pointer according to the storage space occupied by the target data read from the shared memory this time. And writing a second value of the first value of the ith receiving core into a Read Pointer Register (RPR) so that a read pointer for managing the message content of the shared memory corresponding to the ith receiving core points to the next storage space behind the target data.

Optionally, the target data includes a service ID and message content, and the service ID is used to identify a software service ID of the receiving core.

When sending data, the sending core may carry a software service program ID of the receiving core in the target data to indicate which receiving core receives the target data for processing.

For example, as shown in fig. 8, fig. 8 is a schematic diagram of a message format of target data according to an embodiment of the present application. As shown in fig. 8, the target data includes a service id (service id), a message content (User payload), a message length (MU Nums), and a message id (message id). Wherein the Service ID is used for indicating the ID of the receiving kernel software Service program; the User payload is used for indicating message content of inter-core communication; the MU Nums is used to indicate the length of the message; the Message id is used to indicate the Message type of the Message content.

In the embodiment of the present application, if the N receiving cores all detect the interrupt event, the N receiving cores may read the target data in the shared memory at the same time. For example, after the sending core writes the target data into the shared memory, the sending core writes the interrupt flag into the bit in the interrupt register corresponding to the N receiving cores, respectively, to trigger one interrupt. And if the N receiving cores detect the interrupt event, each receiving core reads target data from the shared memory according to the read pointer register RPR maintained by the receiving core and the write pointer register WPR maintained by the sending core, so that the inter-core communication under the application scene of the message broadcasting mode is realized. Specifically, as shown in fig. 9, the sending core reads the values of the N read pointer registers RPR, and checks the remaining storage space in the shared memory according to the value of the minimum read pointer register RPR and the value of the write pointer register WRP maintained by the minimum read pointer register RPR. And when the residual storage space is enough to write the target data of the sending core, the sending core writes the target data into the shared memory, and updates the value of the write pointer register WRP according to the data length or the data quantity of the written target data. And then the sending core writes all the bits of the interrupt registers corresponding to the N receiving cores communicated with the sending core into the interrupt mark to trigger the interrupt event. After each receiving core in the N receiving cores detects an interrupt event by reading the value in the interrupt flag bit, the bit corresponding to the receiving core in the interrupt register is initialized to clear the interrupt. And then each receiving core respectively reads the value of the write pointer register, reads the target data from the shared memory according to the maintained value of the read pointer register RPR and the value of the write pointer register WPR, and updates the corresponding read pointer register RPR according to the read target data.

It can be seen that the inter-core communication method provided in the embodiment of the present application is applied to an electronic device, where the electronic device includes a sending core, N receiving cores, a shared memory, and a register group, where the register group includes a first register and N second registers, the second registers are in one-to-one correspondence with the receiving cores, and N is a positive integer; the sending core reads N first values, and each first value is the value of a second register; the sending core writes target data into the shared content according to a second value and the N first values, wherein the second value is a value of a first register stored by the sending core; and triggers an interrupt event. According to the method and the device, the shared memory and the register group jointly form the exclusive hardware channel for the inter-core communication in the message broadcasting mode, so that the sending core realizes inter-core communication behaviors with the N receiving cores through the exclusive hardware channel, the hardware cost is reduced, the number of times of triggering interruption is reduced, the functions of memory multiplexing and interruption multiplexing under the condition of one-to-many transmission are realized, and the inter-core communication efficiency is improved.

It will be appreciated that the electronic device, in order to implement the above-described functions, comprises corresponding hardware and/or software modules for performing the respective functions. The present application is capable of being implemented in hardware or a combination of hardware and computer software in conjunction with the exemplary algorithm steps described in connection with the embodiments disclosed herein. Whether a function is performed as hardware or computer software drives hardware depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, with the embodiment described in connection with the particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

In this embodiment, the electronic device may be divided into functional modules according to the above method example, for example, each functional module may be divided corresponding to each function, or two or more functions may be integrated into one processing module. The integrated module may be implemented in the form of hardware. It should be noted that the division of the modules in this embodiment is schematic, and is only a logic function division, and there may be another division manner in actual implementation.

In the case of dividing each functional module by corresponding functions, fig. 10 shows a schematic diagram of an inter-core communication apparatus, as shown in fig. 10, the inter-core communication apparatus 1000 is applied to an electronic device, and the inter-core communication apparatus 1000 may include: a read unit 1100, a write unit 1200, and a trigger unit 1300.

Among other things, the reading unit 1100 may be used to support an electronic device to perform the above-described S710, S740, S750, etc., and/or other processes for the techniques described herein.

The writing unit 1200 may be used to support the electronic device to perform the above-described S720, etc., and/or other processes for the techniques described herein.

The trigger unit 1300 may be used to support the electronic device to perform the above-described S730, etc., and/or other processes for the techniques described herein.

It should be noted that all relevant contents of each step related to the above method embodiment may be referred to the functional description of the corresponding functional module, and are not described herein again.

The electronic device provided by the embodiment is used for executing the inter-core communication method, so that the same effect as the implementation method can be achieved.

In case an integrated unit is employed, the electronic device may comprise a processing module, a storage module and a communication module. The processing module may be configured to control and manage actions of the electronic device, for example, may be configured to support the electronic device to execute the steps executed by the reading unit 1100, the writing unit 1200, and the triggering unit 1300. The memory module may be used to support the electronic device in executing stored program codes and data, etc. The communication module can be used for supporting the communication between the electronic equipment and other equipment.

The processing module may be a processor or a controller. Which may implement or execute the various illustrative logical blocks, modules, and circuits described in connection with the disclosure herein. A processor may also be a combination of computing functions, e.g., a combination of one or more microprocessors, a Digital Signal Processing (DSP) and a microprocessor, or the like. The storage module may be a memory. The communication module may specifically be a radio frequency circuit, a bluetooth chip, a Wi-Fi chip, or other devices that interact with other electronic devices.

In an embodiment, when the processing module is a processor and the storage module is a memory, the electronic device according to this embodiment may be a device having the structure shown in fig. 1.

The present embodiment also provides a computer storage medium, where computer instructions are stored in the computer storage medium, and when the computer instructions are run on an electronic device, the electronic device is caused to execute the above related method steps to implement the inter-core communication method in the above embodiments.

The present embodiment also provides a computer program product, which when running on a computer, causes the computer to execute the above related steps to implement the inter-core communication method in the above embodiments.

In addition, embodiments of the present application also provide an apparatus, which may be specifically a chip, a component or a module, and may include a processor and a memory connected to each other; the memory is used for storing computer execution instructions, and when the device runs, the processor can execute the computer execution instructions stored in the memory, so that the chip can execute the inter-core communication method in the above-mentioned method embodiments.

The electronic device, the computer storage medium, the computer program product, or the chip provided in this embodiment are all configured to execute the corresponding method provided above, so that the beneficial effects achieved by the electronic device, the computer storage medium, the computer program product, or the chip may refer to the beneficial effects in the corresponding method provided above, and are not described herein again.

Through the description of the above embodiments, those skilled in the art will understand that, for convenience and simplicity of description, only the division of the above functional modules is used as an example, and in practical applications, the above function distribution may be completed by different functional modules as needed, that is, the internal structure of the device may be divided into different functional modules to complete all or part of the above described functions.

In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, a module or a unit may be divided into only one logic function, and may be implemented in other ways, for example, a plurality of units or components may be combined or integrated into another apparatus, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

Units described as separate parts may or may not be physically separate, and parts displayed as units may be one physical unit or a plurality of physical units, may be located in one place, or may be distributed to a plurality of different places. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a readable storage medium. Based on such understanding, the technical solutions of the embodiments of the present application may be essentially or partially contributed to by the prior art, or all or part of the technical solutions may be embodied in the form of a software product, where the software product is stored in a storage medium and includes several instructions to enable a device (which may be a single chip, a chip, or the like) or a processor (processor) to execute all or part of the steps of the methods of the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. The inter-core communication method is applied to electronic equipment, wherein the electronic equipment comprises a sending core, N receiving cores, a shared memory and a register set, the register set comprises a first register and N second registers, the second registers are in one-to-one correspondence with the receiving cores, and N is a positive integer; the method comprises the following steps:

the sending core triggers an interrupt event.

2. The method of claim 1, wherein writing target data into the shared content by the sending core according to the second value and the N first values comprises:

the sending core selects a minimum first value from the N first values;

the sending core calculates a first difference value, wherein the first difference value is a difference value between the storage size of the shared memory and a second difference value, and the second difference value is a difference value between the second value and the minimum first value;

if the first difference is smaller than the data length of the target data, the sending core repeatedly reads the N first values;

and if the first difference is larger than or equal to the data length of the target data, the sending core writes the target data into a storage space corresponding to the second value in the shared memory.

3. The method of claim 2, further comprising:

after writing the target data into the storage space corresponding to the second value in the shared memory, the sending core writes a third value into the first register, where the third value is a sum of the second value and a data length of the target data.

4. The method of any of claims 1-3, wherein the register bank further comprises a third register comprising N bits, each bit corresponding to a receiving core;

the sending core triggers an interrupt event, including:

and the sending core writes interrupt flags into the bit positions corresponding to the N receiving cores in the third register respectively.

5. The method of any of claims 1-3, wherein the target data comprises a service ID and message content, the service ID identifying a software service ID of a receiving core.

6. The inter-core communication method is applied to electronic equipment, wherein the electronic equipment comprises a sending core, N receiving cores, a shared memory and a register set, the register set comprises a first register and N second registers, the second registers are in one-to-one correspondence with the receiving cores, and N is a positive integer; the method comprises the following steps:

if an interrupt event is detected, the ith receiving core reads a second value, wherein the second value is the value of the first register, and i is a positive integer smaller than or equal to N;

7. The method of claim 6, wherein the register set further comprises a third register comprising N bits, one for each receiving core;

prior to reading the second value, the method further comprises:

reading a value of a target bit in the third register by the ith receiving core, and judging whether the value of the target bit is an interrupt flag or not, wherein the target bit is a bit corresponding to the ith receiving core;

if the value of the target bit is the interrupt flag, the receiving core initializes the target bit.

8. The method according to claim 6 or 7, wherein the reading, by the i-th receiving core, target data from the shared memory according to the second value and the target first value comprises:

calculating a third difference value by the ith receiving core, wherein the third difference value is the difference value between the second value and the target first value;

the ith receiving core determines the data length of the target data according to the third difference;

and the ith receiving core reads the target data with the data length of the third difference from the storage space corresponding to the target first value in the shared memory.

9. The method of claim 8, further comprising:

and the ith receiving core writes the second value into a target second register, wherein the target second register of the first value is a second register corresponding to the ith receiving core.

10. The method of any of claims 6-9, wherein the target data comprises a service ID and message content, the service ID identifying a software service ID of the receiving core.

11. An inter-core communication device is applied to an electronic device, wherein the electronic device comprises a sending core, N receiving cores, a shared memory and a register set, the register set comprises a first register and N second registers, the second registers are in one-to-one correspondence with the receiving cores, and N is a positive integer; the device comprises:

12. An inter-core communication device is applied to an electronic device, wherein the electronic device comprises a sending core, N receiving cores, a shared memory and a register set, the register set comprises a first register and N second registers, the second registers are in one-to-one correspondence with the receiving cores, and N is a positive integer; the device comprises:

13. An electronic device comprising a processor, memory, a communication interface, and one or more programs stored in the memory and configured to be executed by the processor, the programs comprising instructions for performing the steps in the method of any of claims 1-5 or 6-10.

14. A computer-readable storage medium, comprising a computer program stored for electronic data exchange, wherein the computer program causes a computer to perform the method of any one of claims 1-5 or claims 6-10.