CN114490127A

CN114490127A - Inter-core communication method, inter-core communication device, electronic equipment and storage medium

Info

Publication number: CN114490127A
Application number: CN202210069408.9A
Authority: CN
Inventors: 胡鑫裕; 李东华; 王守宽
Original assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Current assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Priority date: 2022-01-20
Filing date: 2022-01-20
Publication date: 2022-05-13

Abstract

An embodiment of the application provides an inter-core communication method, an inter-core communication device, an electronic device and a storage medium, wherein the electronic device comprises a receiving core, N sending cores, a shared memory and a register set, the register set comprises a first register, a second register and a third register, and the method comprises the following steps: the ith sending core reads a first value; writing target data into the shared content according to the second value and the first value; a third value is read from the third register, triggering an interrupt event when the third value satisfies an interrupt triggering condition. According to the method and the device, the shared memory and the register group jointly form the exclusive hardware channel for inter-core communication in the message convergence mode, so that the N generation cores can realize inter-core communication behavior with the receiving core through the exclusive hardware channel, the hardware cost is reduced, the number of times of triggering interruption is reduced, the functions of memory multiplexing and interruption multiplexing under the condition of many-to-one transmission are realized, and the inter-core communication efficiency is improved.

Description

Inter-core communication method, inter-core communication device, electronic equipment and storage medium

Technical Field

The present application relates to the field of communications technologies, and in particular, to an inter-core communication method and apparatus, an electronic device, and a storage medium.

Background

With the development of semiconductor technology, the functions of chips are more and more complex. A System on Chip (SoC) Chip includes not only a plurality of cores, but also a plurality of cores are heterogeneous, so that there is a large amount of inter-core communication, and the transmission efficiency and stability are generally strictly required. Therefore, the inter-core communication is an important data channel, and the efficiency of the inter-core communication becomes a main factor influencing the performance of the chip.

Disclosure of Invention

The embodiment of the application provides an inter-core communication method and device, an electronic device and a storage medium, which can improve inter-core communication efficiency in a message convergence mode scene and reduce hardware cost.

In a first aspect, an embodiment of the present application provides an inter-core communication method, which is applied to an electronic device, where the electronic device includes a receiving core, N sending cores, a shared memory, and a register group, where the register group includes a first register, a second register, and a third register, and N is a positive integer greater than 1; the method comprises the following steps:

reading a first value by an ith sending core, wherein the first value is the value of the second register, and i is a positive integer less than or equal to N;

the ith sending core writes target data into the shared content according to a second value and the first value, wherein the second value is the value of the first register stored by the ith sending core;

the ith sending core reads a third value from the third register, wherein the third value is the length or the number of the written data in the shared memory;

and the ith sending core judges whether an interrupt triggering condition is met or not according to the third value, and triggers an interrupt event when the third value meets the interrupt triggering condition.

In a second aspect, an embodiment of the present application provides an inter-core communication method, which is applied to an electronic device, where the electronic device includes a receiving core, N sending cores, a shared memory, and a register group, where the register group includes a second register, a fourth register, and a fifth register, the fourth register and the fifth register are mirror registers, and N is a positive integer greater than 1; the method comprises the following steps:

if an interrupt event is detected, the receiving core reads a fourth value, and the fourth value is the value of the fifth register;

and the receiving core reads target data from the shared memory according to a first value and the fourth value, wherein the first value is the value of the second register stored by the receiving core.

In a third aspect, an inter-core communication apparatus is provided in an embodiment of the present application, and is applied to an electronic device, where the electronic device includes a receiving core, N sending cores, a shared memory, and a register set, where the register set includes a first register, a second register, and a third register, and N is a positive integer greater than 1; the device comprises:

a reading unit, configured to read a second value and a first value, where the second value is a value of the first register, the first value is a value of the second register, and i is a positive integer smaller than or equal to N;

a write unit, configured to write target data into the shared content using a second value and the first value, where the second value is a value of the first register stored in the ith sending core;

the reading unit is further configured to read a third value from the third register, where the third value is a length or a number of data written in the shared memory;

and the triggering unit is used for judging whether an interruption triggering condition is met or not according to the third value and triggering an interruption event when the third value meets the interruption triggering condition.

In a fourth aspect, an embodiment of the present application provides an inter-core communication apparatus, which is applied to an electronic device, where the electronic device includes a receiving core, N sending cores, a shared memory, and a register set, where the register set includes a second register, a fourth register, and a fifth register, the fourth register and the fifth register are mirror registers, and N is a positive integer greater than 1; the device comprises:

a reading unit, configured to read a fourth value if an interrupt event is detected, where the fourth value is a value of the fifth register;

the reading unit is further configured to read target data from the shared memory according to a first value and the fourth value, where the first value is a value of the second register stored by the receiving core.

In a fifth aspect, an embodiment of the present application provides an electronic device, including a processor, a memory, a communication interface, and one or more programs, where the one or more programs are stored in the memory and configured to be executed by the processor, and the program includes instructions for executing the steps of any of the methods in the first aspect or the second aspect of the embodiment of the present application.

In a sixth aspect, the present application provides a computer-readable storage medium, where the computer-readable storage medium stores a computer program for electronic data exchange, where the computer program makes a computer perform part or all of the steps described in any one of the methods of the first aspect or the second aspect of the present application.

In a seventh aspect, this application provides a computer program product, where the computer program product includes a non-transitory computer-readable storage medium storing a computer program, where the computer program is operable to cause a computer to perform some or all of the steps as described in any of the methods of the first aspect or the second aspect of this application. The computer program product may be a software installation package.

In an embodiment of the present application, an electronic device includes a receiving core, N sending cores, a shared memory, and a register set, where the register set includes a first register, a second register, and a third register, and any sending core in the N sending cores reads a first value, where the first value is a value of the second register; writing target data into the shared content according to a second value and the first value, wherein the second value is a value of a first register stored by the ith sending core; reading a third value from a third register, wherein the third value is the length or the number of the written data in the shared memory; and judging whether the interrupt triggering condition is met or not according to the third value, and triggering an interrupt event when the interrupt triggering condition is met. According to the method and the device, the shared memory and the register group jointly form the exclusive hardware channel for inter-core communication in the message convergence mode, so that the N generation cores can realize inter-core communication behavior with the receiving core through the exclusive hardware channel, the hardware cost is reduced, the number of times of triggering interruption is reduced, the functions of memory multiplexing and interruption multiplexing under the condition of many-to-one transmission are realized, and the inter-core communication efficiency is improved.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

Fig. 1 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure;

fig. 2 is a schematic diagram of inter-core communication based on memory sharing according to an embodiment of the present disclosure;

fig. 3 is a schematic view of an inter-core communication application scenario provided in an embodiment of the present application;

fig. 4 is a schematic structural diagram of an inter-core communication system according to an embodiment of the present application;

FIG. 5 is a schematic structural diagram of a hardware channel provided in an embodiment of the present application;

FIG. 6 is a schematic diagram of inter-core communication hardware architecture interaction according to an embodiment of the present disclosure;

fig. 7 is a flowchart illustrating an inter-core communication method according to an embodiment of the present application;

fig. 8 is a schematic diagram of a message format of target data according to an embodiment of the present application;

fig. 9 is a schematic flowchart of another inter-core communication method according to an embodiment of the present application;

fig. 10 is a schematic diagram of an inter-core communication apparatus according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings.

In order to better understand the scheme of the embodiments of the present application, the following first introduces the related terms and concepts that may be involved in the embodiments of the present application.

The electronic device may be a portable electronic device, such as a cell phone, a tablet computer, a wearable electronic device with wireless communication capabilities (e.g., a smart watch), etc., that also contains other functionality, such as personal digital assistant and/or music player functionality. Exemplary embodiments of the portable electronic device include, but are not limited to, portable electronic devices that carry an IOS system, an Android system, a Microsoft system, or other operating system. The portable electronic device may also be other portable electronic devices such as a Laptop computer (Laptop) or the like. It should also be understood that in other embodiments, the electronic device may not be a portable electronic device, but may be a desktop computer.

A multi-core processor is a processor that integrates two or more complete computing engines (cores) into one processor, and the processor can support multiple processors on a system bus, and a bus controller provides all bus control signals and command signals.

The register, the function of which is to store binary codes, is formed by combining flip-flops with storage functions. One flip-flop can store 1-bit binary codes, so a register for storing n-bit binary codes needs to be formed by n flip-flops. Registers can be divided into two broad categories, basic registers and shift registers, according to their functions. The basic registers can only be fed with data in parallel and can only be output in parallel. The data in the shift register can be shifted to the right or left bit by bit in sequence under the action of shift pulses, and the data can be input in parallel and output in parallel, can be input in series and output in series, can be input in parallel and output in series, or can be input in series and output in parallel, so that the method is very flexible and has wide application.

Fig. 1 shows a schematic structural diagram of an electronic device 100. The electronic device 100 may include a processor 110, an external memory interface 120, an internal memory 121, a Universal Serial Bus (USB) interface 130, a charge management module 140, an antenna 1, an antenna 2, a mobile communication module 150, a wireless communication module 160, an audio module 170, a sensor module 180, and the like.

It is to be understood that the illustrated structure of the embodiment of the present application does not specifically limit the electronic device 100. In other embodiments of the present application, electronic device 100 may include more or fewer components than shown, or some components may be combined, some components may be split, or a different arrangement of components. The illustrated components may be implemented in hardware, software, or a combination of software and hardware.

Processor 110 may include a plurality of processing units, such as: the processor 110 may include an Application Processor (AP), a modem processor, a Graphics Processing Unit (GPU), an Image Signal Processor (ISP), a controller, a video codec, a Digital Signal Processor (DSP), a baseband processor, and/or a neural-Network Processing Unit (NPU), etc. The different processing units may be separate components or may be integrated into multiple processors. The controller can generate an operation control signal according to the instruction operation code and the time sequence signal to complete the control of instruction fetching and instruction execution. In other embodiments, a memory may also be provided in processor 110 for storing instructions and data. Illustratively, the memory in the processor 110 may be a cache memory. The memory may hold instructions or data that have just been used or recycled by the processor 110. If the processor 110 needs to reuse the instruction or data, it can be called directly from the memory. This avoids repeated accesses and reduces the latency of the processor 110, thereby increasing the efficiency with which the electronic device 100 processes data or executes instructions.

In some embodiments, processor 110 may include one or more interfaces. The interface may include an inter-integrated circuit (I2C) interface, an inter-integrated circuit audio (I2S) interface, a Pulse Code Modulation (PCM) interface, a universal asynchronous receiver/transmitter (UART) interface, a Mobile Industry Processor Interface (MIPI), a general-purpose input/output (GPIO) interface, a SIM card interface, a USB interface, and/or the like.

It should be understood that the interface connection relationship between the modules illustrated in the embodiments of the present application is only an illustration, and does not limit the structure of the electronic device 100. In other embodiments of the present application, the electronic device 100 may also adopt different interface connection manners or a combination of multiple interface connection manners in the above embodiments.

The charging management module 140 is configured to receive charging input from a charger. The charger may be a wireless charger or a wired charger. In some wired charging embodiments, the charging management module 140 may receive charging input from a wired charger via the USB interface 130.

The wireless communication function of the electronic device 100 may be implemented by the antenna 1, the antenna 2, the mobile communication module 150, the wireless communication module 160, a modem processor, a baseband processor, and the like.

The

antennas

1 and 2 are used for transmitting and receiving electromagnetic wave signals. Each antenna in the electronic device 100 may be used to cover a single or multiple communication bands. Different antennas can also be multiplexed to improve the utilization of the antennas. For example: the antenna 1 may be multiplexed as a diversity antenna of a wireless local area network. In other embodiments, the antenna may be used in conjunction with a tuning switch.

The mobile communication module 150 may provide a solution including 2G/3G/4G/5G wireless communication applied to the electronic device 100. The mobile communication module 150 may include at least one filter, a switch, a power amplifier, a Low Noise Amplifier (LNA), and the like. The mobile communication module 150 may receive the electromagnetic wave from the antenna 1, filter, amplify, etc. the received electromagnetic wave, and transmit the electromagnetic wave to the modem processor for demodulation. The mobile communication module 150 may also amplify the signal modulated by the modem processor, and convert the signal into electromagnetic wave through the antenna 1 to radiate the electromagnetic wave. In some embodiments, at least some of the functional modules of the mobile communication module 150 may be disposed in the processor 110. In some embodiments, at least some of the functional modules of the mobile communication module 150 may be disposed in the same device as at least some of the modules of the processor 110.

The wireless communication module 160 may provide a solution for wireless communication applied to the electronic device 100, including Wireless Local Area Networks (WLANs) (such as wireless fidelity (Wi-Fi) networks), bluetooth (bluetooth), Global Navigation Satellite System (GNSS), Frequency Modulation (FM), Near Field Communication (NFC), Infrared (IR), UWB, and the like. The wireless communication module 160 may be one or more devices integrating at least one communication processing module. The wireless communication module 160 receives electromagnetic waves via the antenna 2, performs frequency modulation and filtering processing on electromagnetic wave signals, and transmits the processed signals to the processor 110. The wireless communication module 160 may also receive a signal to be transmitted from the processor 110, perform frequency modulation and amplification on the signal, and convert the signal into electromagnetic waves through the antenna 2 to radiate the electromagnetic waves.

The external memory interface 120 may be used to connect an external memory card, such as a Micro SD card, to extend the memory capability of the electronic device 100. The external memory card communicates with the processor 110 through the external memory interface 120 to implement a data storage function. For example, files such as music, video, etc. are saved in an external memory card.

Internal memory 121 may be used to store one or more computer programs, including instructions. The processor 110 may execute the above-mentioned instructions stored in the internal memory 121, so as to enable the electronic device 100 to execute the method for displaying page elements provided in some embodiments of the present application, and various applications and data processing. The internal memory 121 may include a program storage area and a data storage area. Wherein, the storage program area can store an operating system; the storage program area may also store one or more applications (e.g., gallery, contacts, etc.), and the like. The storage data area may store data (e.g., photos, contacts, etc.) created during use of the electronic device 100, and the like. Further, the internal memory 121 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic disk storage components, flash memory components, Universal Flash Storage (UFS), and the like. In some embodiments, the processor 110 may cause the electronic device 100 to execute the method for displaying page elements provided in the embodiments of the present application and other applications and data processing by executing instructions stored in the internal memory 121 and/or instructions stored in a memory provided in the processor 110.

The sensor module 180 may include a pressure sensor 180A, a gyro sensor 180B, an air pressure sensor 180C, a magnetic sensor 180D, an acceleration sensor 180E, a distance sensor 180F, a proximity light sensor 180G, a fingerprint sensor 180H, a temperature sensor 180J, a touch sensor 180K, an ambient light sensor 180L, a bone conduction sensor 180M, and the like.

With the development of semiconductor technology, the functions of chips in electronic devices are becoming more and more complex. The inside of one SoC chip not only comprises a plurality of cores, but also a plurality of cores are heterogeneous. The processor cores are not designed for mutual communication, a large number of inter-core communication phenomena exist in each module of the Modem chip, such as a protocol stack, a physical layer, a data plane and the like, and the inter-core communication is an essential part of the chip. Therefore, the inter-core communication is an important data channel, and the efficiency of the inter-core communication becomes a main factor influencing the performance of the chip. The inter-core communication solution requires a compact set of software and hardware, and the current solution is mainly performed in a form of shared memory, and the shared memory is used as a medium to notify the other party by using inter-core interrupt, and the inter-core communication process is shown in fig. 2.

As shown in fig. 2, in order to implement communication between heterogeneous multi-cores, when a chip is designed, a sending end writes message data into a shared memory, and then sends an interrupt notification to a receiving end, and the receiving end executes a corresponding interrupt handler to enter an address to transfer and read a message, and data transfer is implemented by sharing a memory region. Therefore, in an application scenario as shown in fig. 3, that is, in a message aggregation model (where N sending cores send different message contents to one receiving core), each sending core needs to establish a connection with the receiving core to apply for sharing a memory, and then sends data of each sending core to the receiving core according to a communication method of a one-to-one communication mechanism, so that transmission delay in the application scenario is increased, and thus, requirements on instantaneity and efficiency of inter-core communication cannot be met. And in the case of only one receiving core, frequent triggering of interrupts may cause the receiving core to be heavily loaded, possibly causing interrupts and loss of messages due to untimely system response.

In order to solve the above problems, the present application provides an inter-core communication method, in which a shared memory and a register group jointly form an inter-core communication exclusive hardware channel oriented to a message convergence mode, so that when N sending cores implement inter-core communication with a receiving core through a specific hardware channel, only one connection establishment operation needs to be executed, and one interrupt is triggered, thereby completing many-to-one inter-core communication, and significantly improving inter-core communication efficiency while reducing hardware cost.

Referring to fig. 4, fig. 4 is a schematic structural diagram of an inter-core communication system according to an embodiment of the present disclosure. As shown in fig. 4, the system includes N sending cores, one receiving core, and a hardware channel including a shared memory and a register set. Each sending core is connected with a hardware channel, the receiving core is also connected with the hardware channel, and a memory area (shared memory in the hardware channel) shared by the N sending cores and the receiving core is established. When the N sending cores need to communicate with the receiving core, each sending core writes data into the shared memory according to the value of the register in the register group, and when the total length or the total quantity of the data written by the N sending cores meets a preset condition, the N sending cores trigger only one interrupt to the receiving core through the register. And after the receiving core detects the interrupt event, reading data from the shared memory according to the value of the register in the register group and processing the data.

As shown in fig. 5, fig. 5 is a schematic structural diagram of a hardware channel provided in an embodiment of the present application. As shown in fig. 5, the shared memory and the register set jointly form the hardware channel in the present application, and the shared memory is a segment of ring buffer for storing the message content. The register set includes a control register for managing writing and/or reading of shared memory by a sending core or a receiving core, and an interrupt register for controlling triggering and clearing of interrupt events.

The control registers may include, for example, a read pointer register RPR, a write pointer register WPR, and a length or number of received messages register RLEN/RNUM. The read pointer register RPR is a general register and is used for storing a read pointer of a ring buffer in a hardware channel. Write pointer register WPR is a general purpose register that is exclusively accessed for storing a write pointer for each sending core. The length or number of received messages register RLEN/RNUM is also a general purpose register that has exclusive access to store the length or number of total write messages in a ring buffer within a hardware channel.

For example, the interrupt register may include a write pointer receiving register WPR _ R and a write pointer observation register WPR _ O, which are mirror registers of a double word combination for storing a write pointer of a ring buffer within a hardware channel. Where the write pointer receive register WPR _ R serves as the low field and the write pointer observe register WPR _ O serves as the high field. Writing a value in the low field may trigger an interrupt, while writing a value in the high field may clear the interrupt, while the contents of the low field are automatically copied to the high field. All operations on the write pointer reception register WPR _ R and the write pointer observation register WPR _ O are atomic operations, and therefore, the efficiency and reliability of message transmission can be ensured.

Specifically, when the value of the write pointer register WPR is written into the value of the write pointer reception register WPR _ R, an interrupt signal is generated and sent to the receiving core, the receiving core clears the interrupt by writing to the write pointer observation register WPR _ O after detecting the interrupt signal, and the value of the write pointer reception register WPR _ R is automatically copied to the write pointer observation register WPR _ O, so that the receiving core can read the value of the write pointer register WPR from the write pointer observation register WPR _ O.

Furthermore, the message content in the shared memory can be managed by the read pointer and the write pointer, and the sending core and/or the receiving core can control the transmission process by reading or writing the values of the read pointer register RPR and the write pointer register WPR. Wherein each sending core may know the total length or the total number of sent messages by means of a length or number register RLEN/RNUM of received messages. Therefore, when the sent message meets the condition of the total length or the total number of the messages, the N sending cores trigger an interrupt to the receiving core. Where the write pointer managing the message content in the shared memory is not maintained by the sending core but is obtained by reading a shared write pointer register WPR, but the read pointer managing the message content in the shared memory still needs to be maintained by the receiving core. The sending core may therefore determine whether the interrupt triggering condition is met by reading the length or number register RLEN/RNUM of the received message to retrieve the length or number of messages written.

Specifically, as shown in fig. 6, the i-th sending core of the N sending cores respectively reads the value of the read pointer register RPR, and according to the value of the read pointer register RPR and the value of the write pointer register WRP maintained by the read pointer register RPR, the i-th sending core may calculate the length of data or the number of data currently stored in the shared memory, and further may calculate the current remaining storage space of the shared memory according to the storage size of the shared memory. Then the ith sending core judges whether the current residual memory space can be written with the message content. And if the current remaining storage space is enough to write the message content of the ith sending core, the ith sending core writes the message content into the storage space pointed by the write pointer of the shared memory, updates the write pointer according to the data length or the data quantity of the written message content, and writes the updated write pointer into the write pointer register WPR. And then, the ith sending core reads the value from the length or number register RLEN/RNUM of the received message, acquires the length or number of the message written in the shared memory before the message is written in the message memory, and compares the sum of the value in the length or number register RLEN/RNUM of the received message and the data length or number of the message content written in the ith sending core with the preset data length or number to judge whether the interrupt triggering condition is met currently. If not, the ith sending core writes the latest data length or data quantity into a length or quantity register RLEN/RNUM of the received message for updating, and then the (i + 1) th sending core writes the message content according to the method and judges whether the interruption condition is met or not until the (i) is N or the data length or the data quantity of the written message content meets the interruption condition; if yes, the ith sending core initializes the length or number register RLEN/RNUM of the received message, and writes the value of the write pointer register WPR into the write pointer receive register WPR _ R to trigger the interrupt. When the write pointer receiving register WPR _ R writes the value of the write pointer receiving register WPR _ R, an interrupt signal is generated and sent to the receiving core. Therefore, when the receiving core detects that there is an interrupt event in the hardware channel, that is, the receiving core receives an interrupt signal, the receiving core clears the interrupt by writing to the write pointer observation register WPR _ O, and the value of the write pointer register WPR _ R is automatically copied to the write pointer observation register WPR _ O. The receiving core determines the data length or the number of the content of the read message according to the value of the read pointer register maintained by the receiving core and the value of the write pointer read from the write pointer observation register WPR _ O, reads the content of the read message in the storage space pointed by the read pointer, and updates the read pointer register RPR according to the data length or the data number of the content of the read message. And finally, receiving and checking the read message content for processing.

In the embodiment of the application, a message gathering transmission mechanism is realized through a hardware channel formed by the shared memory and the register group, hardware deployment and software operation such as the shared memory and the register are reduced, transmission efficiency is improved, and hardware cost is reduced. And connection establishment and memory application can be realized once through the hardware channel, and only one interruption is triggered, so that the inter-core communication efficiency of the message convergence mode is remarkably improved.

Referring to fig. 7, fig. 7 is a flowchart illustrating an inter-core communication method according to an embodiment of the present application, applied to the inter-core communication system shown in fig. 2. As shown in fig. 7, the present inter-core communication method includes the following operations.

S710, reading a first value by an ith sending core, wherein the first value is the value of the second register, and i is a positive integer less than or equal to N.

In the application, in an application scenario of a message convergence mode, when N sending cores need to communicate with a receiving core, the N sending cores are respectively connected with a hardware channel, the receiving core is connected with the hardware channel, and a shared memory of the N sending cores and the receiving core is applied. And then, inter-core communication under the application scene of the message convergence mode is realized according to the inter-core communication method provided by the application.

The second register may be the read pointer register RPR. In order to obtain whether a storage space exists in the current shared memory to store data sent by the ith sending core, the ith sending core can read a write pointer for managing message content in the shared memory through the value of the write pointer register WPR and read a read pointer for managing message content in the shared memory through the value of the read pointer register RPR. That is, the first value is the memory address pointed to by the read pointer of the message content in the shared memory. Therefore, by reading the first value, the ith sending core can calculate the current memory remaining space in the shared memory.

S720, the ith sending core writes target data into the shared content according to a second value and the first value, where the second value is a value of the first register stored by the ith sending core.

In this embodiment, the first register may be the write pointer register WPR, and the second value is a memory address pointed to by a write pointer of message content in the shared memory. The ith sending core may check the remaining space of the shared memory by managing a difference between a read pointer and a write pointer of the message content in the shared memory, to determine whether there is a storage space in the shared memory to store the data sent by the ith sending core. When the shared memory has a space for storing the data sent by the ith sending core, the ith sending core can write the target data which needs to be sent into the remaining space of the shared memory.

For example, if the remaining storage space of the shared memory is insufficient to store the data sent by the ith sending core, the ith sending core may generate and display a notification message to notify the user that the currently allocated shared content is insufficient to store the data to be sent, and whether to give up sending of the data or reallocate the memory; or the ith sending core reappears a shared memory shared by the N sending cores and the receiving core or the storage space of the current shared memory is expanded to store data.

Optionally, the writing, by the ith sending core, target data into the shared content according to the second value and the first value includes: the ith sending core calculates a first difference value, wherein the first difference value is a difference value between the storage size of the shared memory and a second difference value, and the second difference value is a difference value between the second value and the first value; if the first difference is smaller than the data length of the target data, the ith sending core repeatedly reads the first value; and if the first difference is greater than or equal to the data length of the target data, the ith sending core writes the target data into a storage space corresponding to the second value in the shared memory.

The ith sending core may calculate a second difference between the second value and the first value, and since the shared memory is a segment of ring buffer, if the second difference is equal to 1, it indicates that the storage spaces of the shared memory all store data, there is no remaining space, and the data of the ith sending core cannot be stored for inter-core communication; when the second difference is greater than 1, it indicates that the data is stored in the shared content. The ith sending core can further calculate the remaining space of the shared memory to judge whether the shared memory can store the data to be sent by the ith sending core.

Specifically, when the second difference is greater than 1, the i-th sending core further calculates a first difference between the storage size of the shared memory and the second difference, where the first difference is the remaining storage space of the shared memory. If the remaining storage space of the shared memory is smaller than the storage space occupied by the target data sent by the ith sending core, the remaining storage space of the shared memory is not enough to store the storage space occupied by the target data, and the ith sending core can repeatedly read the first value for calculation until the remaining storage space of the shared memory is larger than or equal to the storage space occupied by the target data.

Further, if the first difference is greater than or equal to the data length of the target data, that is, when the remaining storage space of the shared memory is greater than or equal to the storage space occupied by the target data, the i-th sending core may write the target data that needs to be sent into the storage space pointed by the write pointer.

Optionally, the method further includes: after writing the target data into the storage space corresponding to the second value in the shared memory, the ith sending core writes a fourth value into the first register, where the fourth value is the sum of the second value and the data length of the target data.

After the ith sending core writes the target data into the shared memory, the remaining storage space of the shared memory changes, and in order to enable the (i + 1) th sending core to write the data to be sent into the shared memory, the ith sending core also needs to update the value of the write pointer register WPR.

Specifically, the ith sending core updates the write pointer according to the storage space occupied by the target data written into the shared memory this time. The ith transmitting core writes the sum of the second value and the data length of the target data into the write pointer register WPR, so that the write pointer managing the message content of the shared memory points to the next storage space after the target data written by the ith transmitting core.

In the embodiment of the application, through the write pointers commonly maintained by the N sending cores, each sending core can write data to be sent into the shared memory according to the current write pointer, so that each sending core can obtain the total length or the total amount of the communication data, and the interrupt is triggered when the total length or the total amount of the communication data meets the triggering condition, so that the many-to-one inter-core communication can be completed by triggering one interrupt, and the problem that the receiving core frequently triggers the interrupt in the message aggregation mode is solved.

S730, the ith sending core reads a third value from the third register, where the third value is the length or the number of the written data in the shared memory.

The third register is the length or number register RLEN/RNUM of the received message, and stores the data length or data number of the target data transmitted by the first i-1 transmitting cores.

And S740, the ith sending core judges whether an interrupt triggering condition is met according to the third value, and when the third value meets the interrupt triggering condition, an interrupt event is triggered.

In this embodiment of the present application, a data length or a data amount of data sent in a next communication of the message aggregation model may be preset, and the preset data length or the preset data amount is used as a trigger condition, so that the data currently written into the shared memory is triggered when the trigger condition is satisfied.

The register set further includes a fourth register and a fifth register, the fourth register is the write pointer receiving register WPR _ R, and the fifth register is the read write pointer observation register WPR _ O. The fourth register and the fifth register are mirror image registers, namely, the value of the fourth register is copied to the fifth register by the write operation of the fifth register, and the value of the fourth register and the value of the fifth register are kept the same after the receiving core responds to the interrupt event.

In the embodiment of the application, different storage contents are distributed to some general purpose registers, and the general purpose registers, the mirror image registers and the shared memory form a dedicated inter-core communication hardware channel facing to a message convergence mode together to control inter-core communication behaviors, so that the times of triggering interruption are reduced, the functions of memory multiplexing and interruption multiplexing under the condition of many-to-one transmission are realized, and the inter-core communication efficiency is improved.

Optionally, the determining whether an interrupt trigger condition is met according to the third value, and triggering an interrupt event when the third value meets the interrupt trigger condition includes: the ith sending core judges whether a fifth value is larger than or equal to a preset value, wherein the fifth value is the sum of the third value and the data length or the data quantity of the target data; if the fifth value is greater than or equal to the preset value, the ith sending core writes the fourth value into the fourth register to trigger an interrupt event, and initializes the third value.

Specifically, the ith transmitting core calculates the sum of the data length or the data amount of the target data and the value of the length or amount register RLEN/RNUM of the received message. If the sum is larger than the preset value, the data length or the data quantity of the data written in the current shared memory reaches the preset data length or the preset data quantity, the interrupt triggering condition is met, and the ith sending core can initialize a length or quantity register RLEN/RNUM for receiving the message for carrying out the next data communication; and writes the value of the write pointer register WPR into the write pointer reception register WPR _ R, triggering an interrupt event.

When the write pointer receiving register WPR _ R writes the value of the write pointer register WPR, an interrupt signal is generated and sent to the receiving core, the receiving core responds to the interrupt, and performs a write operation on the write pointer observation register WPR _ O to clear the interrupt, and the value in the write pointer receiving register WPR _ R is automatically copied to the write pointer observation register WPR _ O.

Optionally, the method further includes: and if the fifth value is smaller than the preset value, the ith sending core writes the fifth value into the third register.

Further, when the sum of the data length or the data amount of the target data and the value of the length or the amount register RLEN/RNUM of the received message is smaller than a preset value, it indicates that the data length or the data amount of the data written in the current shared memory has not reached the preset data length or data amount, and the ith sending core may write the read sum of the value of the length or the amount register RLEN/RNUM of the received message and the data length or the data amount of the target data in the length or the amount register RLEN/RNUM of the received message, and update the sum. And then writing target data to be transmitted into the shared memory by the (i + 1) th transmitting core according to the method until the sum of the read value of the length or number register RLEN/RNUM of the received message and the data length or data number of the target data is greater than or equal to a preset value.

S750, if an interrupt event is detected, reading the fourth value by a receiving core, wherein the fourth value is the value of the fifth register;

the receiving core can detect whether an interrupt event exists in the hardware channel in real time, and enters interrupt service after the receiving core detects the interrupt event. Specifically, the receiving core accesses the write pointer observation register WPR _ O to obtain the first value and the fourth value, so as to calculate the available data that needs to be read by the receiving core in the shared memory.

Optionally, before reading the fourth value, the method further includes: the receiving core initializes the fifth register.

In the embodiment of the present application, when the receiving core receives the interrupt signal, it may access the write pointer observation register WPR _ O, read the value of the write pointer register WPR from the write pointer observation register WPR _ O, and clear the interrupt. The method specifically comprises the following steps: the receiving core initializes the write pointer observation register WPR _ O after reading the value of the write pointer observation register WPR _ O. Since the fourth register and the fifth register are mirror registers, the write pointer receiving register WPR _ R is initialized after the receiving core initializes the write pointer observation register WPR _ O.

S760, the receiving core reads the target data from the shared memory according to a first value and the fourth value, where the first value is a value of the second register stored by the receiving core.

In this embodiment, the receiving core may determine the size of data to be read according to the difference between the read pointer and the write pointer of the message content managing the shared memory. The first value is a value of a read pointer register RPR storing a read pointer, and represents a first address of data stored in the shared memory. The fourth value is a value of the write pointer register WPR storing the write pointer, which is stored in the write pointer observation register WPR _ O, and represents the first address of the memory space in the shared memory, to which data can be written.

Optionally, the reading, by the receiving core, the target data from the shared memory according to the first value and the fourth value includes: the receiving core calculates a third difference value, wherein the third difference value is a difference value between the fourth value and the first value, and the data length of the target data is determined according to the third difference value; and the receiving core reads the target data with the third difference data length from the storage space corresponding to the first value in the shared memory.

Specifically, the receiving core calculates a difference between the value of the write pointer register WPR and the value of the read pointer register RPR, and the data size of this inter-core communication can be obtained. And the receiving core reads the data of the third difference data length from the memory address pointed by the value of the read pointer register RPR in the shared memory.

Optionally, the method further includes: the receiving core writes a sixth value to the second register, the sixth value being a sum of the first value and the third difference value.

Further, after the receiving core reads the target data from the shared memory, the remaining storage space of the shared memory may change, and the receiving core needs to update the value of the read pointer register RPR for the next normal communication of inter-core communication.

Specifically, the receiving core updates the storage space pointed by the read pointer according to the storage space occupied by the target data read from the shared memory this time. The receiving core writes the sum of the first value and the data length of the target data into a read pointer register RPR so that a read pointer managing the message content of the shared memory points to the next storage space after the target data.

Optionally, the target data includes a service ID and message content, and the service ID is used to identify a software service ID of the receiving core.

When sending data, the sending core may carry a software service program ID of the receiving core in the target data to indicate which receiving core receives the target data for processing.

For example, as shown in fig. 8, fig. 8 is a schematic diagram of a message format of target data according to an embodiment of the present application. As shown in fig. 8, the target data includes a service id (service id), a message content (User payload), a message length (MU Nums), and a message id (message id). Wherein the Service ID is used for indicating the ID of the receiving kernel software Service program; the User payload is used for indicating message content of inter-core communication; the MU Nums is used to indicate the length of the message; the Message id is used to indicate the Message type of the Message content.

In the embodiment of the present application, the N sending cores may write the target data into the shared memory at the same time until the data length or the data amount written into the shared memory at this time is greater than the preset value. For example, the N sending cores respectively write target data into the shared memory, and if the data length or the data quantity in the shared memory is greater than a preset value after the nth sending core writes the target data into the shared content, the nth sending core triggers an interrupt event, thereby implementing inter-core communication in an application scenario of the message aggregation mode. Specifically, as shown in fig. 9, the sending core 1 reads the values of the read pointer register RPR and the write pointer register WRP, respectively, and the sending core 1 checks the remaining storage space in the shared memory according to the value of the read pointer register RPR. When the remaining storage space is enough to write the target data of the sending core 1, the sending core 1 writes the target data into the shared memory, and updates the value of the write pointer register WRP according to the data length or the data quantity of the target data written this time. Then, the sending core 1 reads the value of the length or number register RLEN/RNUM of the received message, and judges whether the interrupt trigger condition is currently satisfied according to the value. If not, the sending core 1 writes the latest data length or data amount into the length or amount register RLEN/RNUM of the received message for updating. And then the sending core 1 writes the target data according to the method and judges whether the interrupt condition is met or not until i is N or the data length or the data quantity of the written target data meets the interrupt condition. If the sending core N reads the length or number register RLEN/RNUM of the received message, the sending core N initializes the length or number register RLEN/RNUM of the received message, writes the value of the write pointer register WPR into the write pointer receiving register WPR _ R, generates an interrupt signal and sends the interrupt signal to the receiving core, and after the receiving core receives the interrupt signal, the receiving core performs write operation on the write pointer observation register WPR _ O to clear the interrupt, and the operation can automatically copy the value of the write pointer receiving register WPR _ R to the write pointer observation register WPR _ O. And then the receiving core reads target data from the shared memory according to the value of the read pointer register maintained by the receiving core and the value of the write pointer read from the write pointer observation register WPR _ O, and updates the read pointer register RPR according to the read target data.

It can be seen that in the inter-core communication method provided in the embodiment of the present application, the electronic device includes a receiving core, N sending cores, a shared memory, and a register set, where the register set includes a first register, a second register, and a third register, and any sending core in the N sending cores reads a first value, where the first value is a value of the second register; writing target data into the shared content according to a second value and the first value, wherein the second value is a value of a first register stored by the ith sending core; a third value is read from the third register, triggering an interrupt event when the third value satisfies an interrupt triggering condition. According to the method and the device, the shared memory and the register group jointly form the exclusive hardware channel for inter-core communication in the message convergence mode, so that the N generation cores can realize inter-core communication behavior with the receiving core through the exclusive hardware channel, the hardware cost is reduced, the number of times of triggering interruption is reduced, the functions of memory multiplexing and interruption multiplexing under the condition of many-to-one transmission are realized, and the inter-core communication efficiency is improved.

It will be appreciated that the electronic device, in order to implement the above-described functions, comprises corresponding hardware and/or software modules for performing the respective functions. The present application is capable of being implemented in hardware or a combination of hardware and computer software in conjunction with the exemplary algorithm steps described in connection with the embodiments disclosed herein. Whether a function is performed as hardware or computer software drives hardware depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, with the embodiment described in connection with the particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.

In this embodiment, the electronic device may be divided into functional modules according to the above method example, for example, each functional module may be divided corresponding to each function, or two or more functions may be integrated into one processing module. The integrated module may be implemented in the form of hardware. It should be noted that the division of the modules in this embodiment is schematic, and is only a logic function division, and there may be another division manner in actual implementation.

In the case of dividing each functional module by corresponding functions, fig. 10 shows a schematic diagram of an inter-core communication apparatus, as shown in fig. 10, the inter-core communication apparatus 1000 is applied to an electronic device, and the inter-core communication apparatus 1000 may include: a read unit 1100, a write unit 1200, and a trigger unit 1300.

Among other things, the reading unit 1100 may be used to support an electronic device to perform the above-described S710, S730, S750, S760, etc., and/or other processes for the techniques described herein.

The writing unit 1200 may be used to support the electronic device to perform the above-described S720, etc., and/or other processes for the techniques described herein.

The trigger unit 1300 may be used to support the electronic device to perform the above-described S740, etc., and/or other processes for the techniques described herein.

It should be noted that all relevant contents of each step related to the method embodiment may be referred to the functional description of the corresponding functional module, and are not described herein again.

The electronic device provided by the embodiment is used for executing the inter-core communication method, so that the same effect as the implementation method can be achieved.

In case an integrated unit is employed, the electronic device may comprise a processing module, a storage module and a communication module. The processing module may be configured to control and manage actions of the electronic device, for example, may be configured to support the electronic device to execute the steps executed by the reading unit 1100, the writing unit 1200, and the triggering unit 1300. The memory module may be used to support the electronic device in executing stored program codes and data, etc. The communication module can be used for supporting the communication between the electronic equipment and other equipment.

The processing module may be a processor or a controller. Which may implement or perform the various illustrative logical blocks, modules, and circuits described in connection with the disclosure. A processor may also be a combination of computing functions, e.g., a combination of one or more microprocessors, a Digital Signal Processing (DSP) and a microprocessor, or the like. The storage module may be a memory. The communication module may specifically be a radio frequency circuit, a bluetooth chip, a Wi-Fi chip, or other devices that interact with other electronic devices.

In an embodiment, when the processing module is a processor and the storage module is a memory, the electronic device according to this embodiment may be a device having the structure shown in fig. 1.

The present embodiment also provides a computer storage medium, where computer instructions are stored in the computer storage medium, and when the computer instructions are run on an electronic device, the electronic device is caused to execute the above related method steps to implement the inter-core communication method in the above embodiments.

The present embodiment also provides a computer program product, which when running on a computer, causes the computer to execute the above related steps to implement the inter-core communication method in the above embodiments.

In addition, embodiments of the present application also provide an apparatus, which may be specifically a chip, a component or a module, and may include a processor and a memory connected to each other; the memory is used for storing computer execution instructions, and when the device runs, the processor can execute the computer execution instructions stored in the memory, so that the chip can execute the inter-core communication method in the above-mentioned method embodiments.

The electronic device, the computer storage medium, the computer program product, or the chip provided in this embodiment are all configured to execute the corresponding method provided above, so that the beneficial effects achieved by the electronic device, the computer storage medium, the computer program product, or the chip may refer to the beneficial effects in the corresponding method provided above, and are not described herein again.

Through the description of the above embodiments, those skilled in the art will understand that, for convenience and simplicity of description, only the division of the above functional modules is used as an example, and in practical applications, the above function distribution may be completed by different functional modules as needed, that is, the internal structure of the device may be divided into different functional modules to complete all or part of the above described functions.

In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, a module or a unit may be divided into only one logic function, and may be implemented in other ways, for example, a plurality of units or components may be combined or integrated into another apparatus, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

Units described as separate parts may or may not be physically separate, and parts displayed as units may be one physical unit or a plurality of physical units, may be located in one place, or may be distributed to a plurality of different places. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit may be implemented in the form of hardware, or may also be implemented in the form of a software functional unit.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a readable storage medium. Based on such understanding, the technical solutions of the embodiments of the present application may be essentially or partially contributed to by the prior art, or all or part of the technical solutions may be embodied in the form of a software product, where the software product is stored in a storage medium and includes several instructions to enable a device (which may be a single chip, a chip, or the like) or a processor (processor) to execute all or part of the steps of the methods of the embodiments of the present application. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.

The above description is only for the specific embodiments of the present application, but the scope of the present application is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present application, and shall be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. The inter-core communication method is applied to electronic equipment, wherein the electronic equipment comprises a receiving core, N sending cores, a shared memory and a register set, the register set comprises a first register, a second register and a third register, and N is a positive integer greater than 1; the method comprises the following steps:

2. The method of claim 1, wherein writing target data into the shared content by the ith sending core according to the second value and the first value comprises:

the ith sending core calculates a first difference value, wherein the first difference value is a difference value between the storage size of the shared memory and a second difference value, and the second difference value is a difference value between the second value and the first value;

if the first difference is smaller than the data length of the target data, the ith sending core repeatedly reads the first value;

and if the first difference is greater than or equal to the data length of the target data, the ith sending core writes the target data into a storage space corresponding to the second value in the shared memory.

3. The method of claim 2, further comprising:

after writing the target data into the storage space corresponding to the second value in the shared memory, the ith sending core writes a fourth value into the first register, where the fourth value is the sum of the second value and the data length of the target data.

4. A method according to any of claims 1-3, wherein the register set further comprises a fourth register;

the judging whether an interrupt triggering condition is met according to the third value, and triggering an interrupt event when the third value meets the interrupt triggering condition includes:

the ith sending core judges whether a fifth value is larger than or equal to a preset value, wherein the fifth value is the sum of the third value and the data length or the data quantity of the target data;

if the fifth value is greater than or equal to the preset value, the ith sending core writes the fourth value into the fourth register to trigger an interrupt event, and initializes the third value.

5. The method of claim 4, further comprising:

and if the fifth value is smaller than the preset value, the ith sending core writes the fifth value into the third register.

6. The method of any of claims 1-5, wherein the target data comprises a service ID and message content, the service ID identifying a software service ID of the receiving core.

7. The inter-core communication method is applied to electronic equipment, wherein the electronic equipment comprises a receiving core, N sending cores, a shared memory and a register set, the register set comprises a second register, a fourth register and a fifth register, the fourth register and the fifth register are mirror image registers, and N is a positive integer greater than 1; the method comprises the following steps:

if an interrupt event is detected, the receiving core reads a fourth value, wherein the fourth value is the value of the fifth register;

8. The method of claim 7, wherein prior to reading the fourth value, the method further comprises:

the receiving core initializes the fifth register.

9. The method of claim 7 or 8, wherein reading, by the receiving core, the target data from the shared memory according to the first value and the fourth value comprises:

the receiving core calculates a third difference value, wherein the third difference value is a difference value between the fourth value and the first value, and the data length of the target data is determined according to the third difference value;

and the receiving core reads the target data with the third difference data length from the storage space corresponding to the first value in the shared memory.

10. The method of claim 9, further comprising:

the receiving core writes a sixth value to the second register, the sixth value being a sum of the first value and the third difference value.

11. The method of any of claims 7-10, wherein the target data service ID and message content, the service ID identifying a software service ID of the receiving core.

12. An inter-core communication device is applied to an electronic device, wherein the electronic device comprises a receiving core, N sending cores, a shared memory and a register set, the register set comprises a first register, a second register and a third register, and N is a positive integer greater than 1; the device comprises:

a reading unit, configured to read a first value, where the first value is a value of the second register, and i is a positive integer smaller than or equal to N;

13. An inter-core communication device is applied to an electronic device, wherein the electronic device includes a receiving core, N sending cores, a shared memory, and a register set, the register set includes a second register, a fourth register, and a fifth register, the fourth register and the fifth register are mirror image registers, and N is a positive integer greater than 1; the device comprises:

14. An electronic device comprising a processor, a memory, a communication interface, and one or more programs stored in the memory and configured to be executed by the processor, the programs comprising instructions for performing the steps in the method of any of claims 1-6 or claims 7-11.

15. A computer-readable storage medium, characterized in that a computer program for electronic data exchange is stored, wherein the computer program causes a computer to perform the method according to any of claims 1-6 or claims 7-11.