CN110600548A - Enhancement mode heterojunction field effect transistor - Google Patents
Enhancement mode heterojunction field effect transistor Download PDFInfo
- Publication number
- CN110600548A CN110600548A CN201910891750.5A CN201910891750A CN110600548A CN 110600548 A CN110600548 A CN 110600548A CN 201910891750 A CN201910891750 A CN 201910891750A CN 110600548 A CN110600548 A CN 110600548A
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- cap layer
- layer
- effect transistor
- field effect
- heterojunction field
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- 230000005669 field effect Effects 0.000 title claims abstract description 35
- 230000004888 barrier function Effects 0.000 claims abstract description 18
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 239000010410 layer Substances 0.000 claims description 144
- 238000002161 passivation Methods 0.000 claims description 17
- 238000001312 dry etching Methods 0.000 claims description 7
- 238000000034 method Methods 0.000 claims description 7
- 238000001039 wet etching Methods 0.000 claims description 7
- 230000002687 intercalation Effects 0.000 claims description 4
- 238000009830 intercalation Methods 0.000 claims description 4
- 239000011229 interlayer Substances 0.000 claims description 3
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 5
- 239000002131 composite material Substances 0.000 description 2
- 229910002601 GaN Inorganic materials 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 229910003460 diamond Inorganic materials 0.000 description 1
- 239000010432 diamond Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 239000011185 multilayer composite material Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
Abstract
The invention is suitable for the technical field of semiconductor devices and discloses an enhanced heterojunction field effect transistor which sequentially comprises a substrate, a buffer layer, a barrier layer and a cap layer from bottom to top; the cap layer sequentially comprises a dielectric layer, a P-type doped cap layer and an N-type doped cap layer from bottom to top; the buffer layer is provided with a source electrode and a drain electrode in a row, and the N-type doped cap layer is provided with a gate electrode. According to the enhancement type heterojunction field effect transistor provided by the invention, the dielectric layer is introduced between the barrier layer and the P-type doped cap layer, and the N-type doped cap layer is introduced between the P-type doped cap layer and the gate electrode, so that the threshold voltage of the device can be improved, and the current density of the device can be increased.
Description
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to an enhanced heterojunction field effect transistor.
Background
A Heterojunction Field Effect Transistor (HFET) device has the characteristics of high electron mobility, high device operating frequency and high efficiency. The method has very important application prospect in the fields of microwave power emitter transmission and power electronics. One of the modes of operation of the HFET is enhancement mode.
At present, an enhancement type heterojunction field effect transistor is generally realized by adopting a P-type cap layer technology, but the enhancement type heterojunction field effect transistor realized by adopting the mode has lower threshold voltage and smaller current density.
Disclosure of Invention
In view of this, embodiments of the present invention provide an enhancement mode heterojunction field effect transistor to solve the problem that the enhancement mode heterojunction field effect transistor implemented in the prior art has a lower threshold voltage and a lower current density.
The embodiment of the invention provides an enhanced heterojunction field effect transistor which sequentially comprises a substrate, a buffer layer, a barrier layer and a cap layer from bottom to top;
the cap layer sequentially comprises a dielectric layer, a P-type doped cap layer and an N-type doped cap layer from bottom to top;
the buffer layer is provided with a source electrode and a drain electrode in a row, and the N-type doped cap layer is provided with a gate electrode.
Optionally, the cap layer further comprises a dielectric intercalation layer;
the medium intercalation layer is positioned between the P-type doping cap layer and the N-type doping cap layer.
Optionally, the P-type doped cap layer sequentially comprises a P-type cap layer with a first doping concentration and a P-type cap layer with a second doping concentration from bottom to top;
the first doping concentration is less than the second doping concentration.
Optionally, the P-type doped cap layer is uniformly doped or non-uniformly doped.
Optionally, the N-type doped cap layer is uniformly doped or non-uniformly doped.
Optionally, the cap layer is located entirely or partially directly below the gate electrode.
Optionally, the forming method of the cap layer includes dry etching and/or wet etching.
Optionally, the enhancement mode heterojunction field effect transistor further comprises a passivation layer;
the passivation layer completely covers the gate electrode, the barrier layer and/or the cap layer, and the passivation layer partially covers the source electrode and the drain electrode.
Optionally, the enhancement mode heterojunction field effect transistor further comprises a field plate structure on the passivation layer.
Optionally, the field plate structure comprises any one of a source field plate and a drain field plate.
Compared with the prior art, the embodiment of the invention has the following beneficial effects: the enhanced heterojunction field effect transistor provided by the embodiment of the invention sequentially comprises a substrate, a buffer layer, a barrier layer and a cap layer from bottom to top, wherein the cap layer sequentially comprises a dielectric layer, a P-type doped cap layer and an N-type doped cap layer from bottom to top; the buffer layer is provided with a source electrode and a drain electrode in a row, and the N-type doped cap layer is provided with a gate electrode. According to the enhancement mode heterojunction field effect transistor provided by the embodiment of the invention, the dielectric layer is introduced between the barrier layer and the P-type doped cap layer, and the N-type doped cap layer is introduced between the P-type doped cap layer and the gate electrode, so that the threshold voltage of the device can be improved, and the current density of the device can be increased.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
FIG. 1 is a schematic diagram of an enhanced heterojunction field effect transistor according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an enhancement mode heterojunction field effect transistor according to another embodiment of the present invention;
FIG. 3 is a schematic diagram of an enhancement mode heterojunction field effect transistor according to yet another embodiment of the present invention;
fig. 4 is a schematic structural diagram of an enhancement mode heterojunction field effect transistor according to yet another embodiment of the invention.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the present application. It will be apparent, however, to one skilled in the art that the present application may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present application with unnecessary detail.
In order to explain the technical means of the present invention, the following description will be given by way of specific examples.
Fig. 1 is a schematic structural diagram of an enhancement mode heterojunction field effect transistor according to an embodiment of the present invention, and only a part related to the embodiment of the present invention is shown for convenience of illustration.
As shown in fig. 1, the enhancement type heterojunction field effect transistor may include a substrate 10, a buffer layer 20, a barrier layer 30, and a cap layer 40 in this order from bottom to top;
the cap layer 40 sequentially comprises a dielectric layer 41, a P-type doped cap layer 42 and an N-type doped cap layer 43 from bottom to top;
the buffer layer 20 is divided into a source electrode 50 and a drain electrode 60, and the N-type doped cap layer 43 is provided with a gate electrode 70.
The structure of the enhancement mode heterojunction field effect transistor provided by the embodiment of the invention is shown in fig. 1, and the enhancement mode heterojunction field effect transistor is manufactured on the basis of a III-group nitride material.
According to the embodiment of the invention, the dielectric layer is introduced between the barrier layer and the P-type doped cap layer, and the N-type doped cap layer is introduced between the P-type doped cap layer and the gate electrode, so that the threshold voltage of the device can be improved, and the current density of the device can be increased.
In one embodiment of the present invention, the capping layer 40 further comprises a dielectric intercalation layer 44;
a dielectric interlayer 44 is located between the P-type doped cap layer 42 and the N-type doped cap layer 43.
As shown in FIG. 2, the cap layer 40 may also include a dielectric interlayer 44 between the P-type doped cap layer 42 and the N-type doped cap layer 43.
In an embodiment of the present invention, the P-type doped cap layer 42 sequentially includes, from bottom to top, a P-type cap layer 421 with a first doping concentration and a P-type cap layer 422 with a second doping concentration;
the first doping concentration is less than the second doping concentration.
As shown in fig. 3, the P-type doped cap layer 42 may include two P-type cap layers with different doping concentrations, namely a P-type cap layer 421 with a first doping concentration and a P-type cap layer 422 with a second doping concentration, wherein the first doping concentration is less than the second doping concentration.
According to the embodiment of the invention, the non-uniformly doped P-type cap layer is introduced, so that the influence of the residual P-type doped cap layer in the etching area on the current can be relieved, the saturation current can be increased, and the on-resistance can be reduced.
In one embodiment of the present invention, the P-doped cap layer 42 is uniformly doped or non-uniformly doped.
In the embodiment of the present invention, the P-type doped cap layer 42 may be uniformly doped or non-uniformly doped. When the P-type doped cap layer 42 is non-uniformly doped, it may be doped in multiple steps, linearly, or in other types, and is not limited herein.
In one embodiment of the present invention, the N-type doped cap layer 43 is uniformly doped or non-uniformly doped.
In the embodiment of the present invention, the N-type doped cap layer 43 may be uniformly doped or non-uniformly doped. When the N-type doped cap layer 43 is non-uniformly doped, it may be doped in multiple steps, linearly, or in other types, and is not limited herein.
In one embodiment of the present invention, the cap layer 40 is located wholly or partially directly below the gate electrode 70.
As shown in FIGS. 1, 2 and 4, the cap layer 40 may be entirely located directly below the gate electrode 70. As shown in FIG. 3, the cap layer 40 may also be partially located directly below the gate electrode 70.
In one embodiment of the present invention, the cap layer 40 is formed by a method including dry etching and/or wet etching.
In the embodiment of the present invention, the forming method of the cap layer 40 may be dry etching, wet etching, or a combination of the dry etching and the wet etching. That is, when the grown cap layer is etched to form the cap layer shown in fig. 1 to 4, the cap layer may be formed by the above-described dry etching, may be formed by wet etching, or may be formed by a combination of both dry etching and wet etching.
In one embodiment of the present invention, the enhancement mode heterojunction field effect transistor further comprises a passivation layer 80;
the passivation layer 80 entirely covers the gate electrode 70, and the passivation layer 80 entirely covers the barrier layer 30 and/or the cap layer 40, and the passivation layer partially covers the source electrode 50 and the drain electrode 60.
As shown in fig. 4, the passivation layer 80 entirely covers the gate electrode 70, and partially covers the source electrode 50, and partially covers the drain electrode 60. When the cap layer 40 is entirely located directly under the gate electrode 70, the passivation layer 80 entirely covers the barrier layer 30; when the cap layer 40 is partially located right under the gate electrode 70 and the cap layer 40 completely covers the barrier layer 30 as shown in fig. 3, the passivation layer 80 completely covers the cap layer 40; when the cap layer 40 is partially located directly under the gate electrode 70 and the cap layer 40 partially covers the barrier layer 30, the passivation layer 80 entirely covers the cap layer 40 and the barrier layer 30.
In one embodiment of the present invention, the enhancement mode heterojunction field effect transistor further comprises a field plate structure 90 on the passivation layer 80.
In one embodiment of the present invention, the field plate structure 90 includes any one of a source field plate and a drain field plate.
The field plate structure 90 is located as shown in fig. 4, the field plate structure 90 may be any one of a source field plate and a drain field plate, and the field plate structure in fig. 4 is a source field plate. By adding a field plate structure, the device performance can be further improved.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; for example, when the cap layer is non-uniformly doped, the cap layer is doped in a multi-layer step doping or linear doping manner, the barrier layer is made of one or more composite materials, the buffer layer is made of a multi-layer composite material, a back barrier structure, a multi-layer buffer layer, and the like, the substrate is made of SiC, Si, diamond, sapphire, GaN, and the like, or a multi-layer composite substrate is selected, the epitaxial layer is directly extended to the substrate or transferred to other substrates, the appearance of the gate electrode can be any existing shape and the like, and the modifications or substitutions are not required, so that the essence of the corresponding technical scheme does not depart from the spirit and scope of the technical scheme of each embodiment of the present application, and the barrier layer is included in the.
Claims (10)
1. An enhancement heterojunction field effect transistor is characterized by comprising a substrate, a buffer layer, a barrier layer and a cap layer from bottom to top in sequence;
the cap layer sequentially comprises a dielectric layer, a P-type doped cap layer and an N-type doped cap layer from bottom to top;
the buffer layer is provided with a source electrode and a drain electrode in a row, and the N-type doped cap layer is provided with a gate electrode.
2. The enhanced heterojunction field effect transistor of claim 1, wherein said cap layer further comprises a dielectric interlayer;
the medium intercalation layer is positioned between the P-type doping cap layer and the N-type doping cap layer.
3. The enhancement mode heterojunction field effect transistor according to claim 1, wherein the P-type doped cap layer comprises a P-type cap layer with a first doping concentration and a P-type cap layer with a second doping concentration in sequence from bottom to top;
the first doping concentration is less than the second doping concentration.
4. The enhancement mode heterojunction field effect transistor of claim 1, wherein the P-type doped cap layer is uniformly doped or non-uniformly doped.
5. The enhancement mode heterojunction field effect transistor of claim 1, wherein said N-type doped cap layer is either uniformly doped or non-uniformly doped.
6. The enhancement mode heterojunction field effect transistor of claim 1, wherein said cap layer is located wholly or partially directly below said gate electrode.
7. The enhancement mode heterojunction field effect transistor according to claim 1, wherein the method of forming the cap layer comprises dry etching and/or wet etching.
8. An enhanced heterojunction field effect transistor according to any of claims 1 to 7, further comprising a passivation layer;
the passivation layer completely covers the gate electrode, the barrier layer and/or the cap layer, and the passivation layer partially covers the source electrode and the drain electrode.
9. The enhancement mode heterojunction field effect transistor of claim 8, further comprising a field plate structure on said passivation layer.
10. The enhancement mode heterojunction field effect transistor of claim 9, wherein said field plate structure comprises any one of a source field plate and a drain field plate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201910891750.5A CN110600548A (en) | 2019-09-20 | 2019-09-20 | Enhancement mode heterojunction field effect transistor |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910891750.5A CN110600548A (en) | 2019-09-20 | 2019-09-20 | Enhancement mode heterojunction field effect transistor |
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2019
- 2019-09-20 CN CN201910891750.5A patent/CN110600548A/en active Pending
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| US20080079023A1 (en) * | 2006-09-29 | 2008-04-03 | Masahiro Hikita | Nitride semiconductor device and method for fabricating the same |
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Application publication date: 20191220 |