CN110600063A - Voltage generation circuit, semiconductor storage device, and voltage generation method - Google Patents

Voltage generation circuit, semiconductor storage device, and voltage generation method Download PDF

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Publication number
CN110600063A
CN110600063A CN201910504534.0A CN201910504534A CN110600063A CN 110600063 A CN110600063 A CN 110600063A CN 201910504534 A CN201910504534 A CN 201910504534A CN 110600063 A CN110600063 A CN 110600063A
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voltage
state
switching element
node
oscillation signal
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CN201910504534.0A
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CN110600063B (en
Inventor
赤堀旭
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Lapis Semiconductor Co Ltd
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Lapis Semiconductor Co Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/30—Power supply circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/145—Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H02M3/073—Charge pumps of the Schenkel-type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H02M3/071—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps adapted to generate a negative voltage output from a positive voltage source
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
    • H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
    • H02M3/073—Charge pumps of the Schenkel-type
    • H02M3/076—Charge pumps of the Schenkel-type the clock signals being boosted to a value being higher than the input voltage value

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dc-Dc Converters (AREA)
  • Read Only Memory (AREA)
  • Dram (AREA)

Abstract

The invention aims to provide a voltage generation circuit, a semiconductor storage device and a voltage generation method, which can inhibit the increase of the circuit scale and the power consumption. And the voltage generation circuit includes: an oscillation signal generating unit that generates an oscillation signal in which a first voltage state and a second voltage state are alternately repeated; a capacitor having one end receiving the oscillation signal and the other end connected to an output node; a switching element receiving a control voltage and being set to an on state or an off state according to the control voltage, the switching element applying a first voltage to an output node when being set to the on state; and a switching control unit configured to supply the second voltage to the switching element as the control voltage when the oscillation signal is in the first voltage state, and supply the voltage of the output node to the switching element as the control voltage when the oscillation signal is in the second voltage state.

Description

Voltage generation circuit, semiconductor storage device, and voltage generation method
Technical Field
The present invention relates to a voltage generation circuit that generates a voltage having a desired voltage value, a semiconductor memory device including the voltage generation circuit, and a voltage generation method.
Background
A semiconductor memory device is provided with a voltage generation circuit that generates various positive and negative voltages to be applied to memory cells, and reads, writes, or erases data.
As such a voltage generation circuit, a charge pump circuit capable of generating not only a positive voltage higher than a power supply voltage but also a negative voltage is known (see, for example, fig. 1 and 5 of japanese patent application laid-open No. h 11-299227 (patent document 1)).
In such a charge pump circuit, first, a ground voltage (0 volt) is applied to one end of a capacitor via a Metal Oxide Semiconductor (MOS) transistor as a switching element. Further, in this period, the capacitor is charged by applying a power supply voltage of 5 volts to the other end of the capacitor. Then, the transistor is switched to an off state, and the power supply voltage that has been applied to the other end of the capacitor is switched to the ground voltage, whereby a voltage of-5 volts is generated as a voltage of negative polarity at one end of this capacitor.
However, since the source of the transistor is connected to one end of the capacitor, a voltage of-5 volts is applied to the source of the transistor. Therefore, in order to set this transistor to an off state, a control voltage of-5 volts or less needs to be applied to the gate thereof.
Therefore, in the charge pump circuit, a level conversion circuit that converts the control voltage supplied to the gate of the transistor from a ground voltage (0 volt) to-5 volts is provided to set the transistor in an off state.
Disclosure of Invention
[ problems to be solved by the invention ]
However, when a charge pump circuit is used as the voltage generation circuit, a level conversion circuit is required to reliably control on/off of a transistor that is responsible for the charge pump operation, which leads to an increase in circuit scale and power consumption.
The invention aims to provide a voltage generation circuit, a semiconductor storage device and a voltage generation method, which can inhibit the increase of the circuit scale and the power consumption.
[ means for solving problems ]
A voltage generation circuit according to the present invention is a voltage generation circuit that generates a dc voltage at an output node, and includes: an oscillation signal generating unit that generates an oscillation signal in which a first voltage state and a second voltage state are alternately repeated; a capacitor having one end receiving the oscillation signal and the other end connected to the output node; a switching element receiving a control voltage and being set to an on state or an off state according to the control voltage, the switching element applying the first voltage to the output node when being set to the on state; and a switching control unit configured to set the switching element to an off state by supplying the second voltage to the switching element as the control voltage when the oscillation signal is in the first voltage state, and set the switching element to an on state by supplying the voltage of the output node to the switching element as the control voltage when the oscillation signal is in the second voltage state.
Further, a voltage generation circuit according to the present invention is a voltage generation circuit that generates a dc voltage at an output node, including: an oscillation signal generation unit that generates a first oscillation signal in which a first voltage state and a second voltage state are alternately repeated, and a second oscillation signal in which a phase of the first oscillation signal is inverted; a first node and a second node; a first capacitor that receives the first oscillation signal at one end and is connected to the first node at the other end; a second capacitor having one end receiving the second oscillation signal and the other end connected to the second node; a first switching element set to an on state or an off state according to a first control voltage, the first switching element applying the first voltage to the first node when set to the on state; a second switching element set to an on state or an off state according to a second control voltage, the second switching element applying the first voltage to the second node when set to the on state; a first switching control unit configured to set the first switching element to an off state by supplying the second voltage to the first switching element as the first control voltage when the first oscillation signal is in the first voltage state, and set the first switching element to an on state by supplying the voltage of the second node to the first switching element as the first control voltage when the first oscillation signal is in the second voltage state; a second switching control unit configured to set the second switching element to an off state by supplying the second voltage to the second switching element as the second control voltage when the second oscillation signal is in the first voltage state, and set the second switching element to an on state by supplying the voltage of the first node to the second switching element as the second control voltage when the second oscillation signal is in the second voltage state; a first output switching element which is turned on only when the first control voltage is in the second voltage state and applies the voltage of the first node to the output node; and a second output switching element which is turned on only when the second control voltage is in the second voltage state, and applies the voltage of the second node to the output node.
Further, a voltage generation circuit according to the present invention is a voltage generation circuit that generates a dc voltage at an output node, including: an oscillation signal generation unit configured to generate a first oscillation signal in which a first voltage state and a second voltage state are alternately repeated, a second oscillation signal in which a phase of a rising edge of the first oscillation signal is advanced by a predetermined time, a third oscillation signal in which a phase of the first oscillation signal is inverted, and a fourth oscillation signal in which a phase of a rising edge of the third oscillation signal is advanced by a predetermined time; a first node and a second node; a first capacitor that receives the first oscillation signal at one end and is connected to the first node at the other end; a second capacitor having one end receiving the third oscillation signal and the other end connected to the second node; a first switching element set to an on state or an off state according to a first control voltage, the first switching element applying the first voltage to the first node when set to the on state; a second switching element set to an on state or an off state according to a second control voltage, the second switching element applying the first voltage to the second node when set to the on state; a first switching control unit configured to set the first switching element to an off state by supplying the second voltage to the first switching element as the first control voltage when the second oscillation signal is in the first voltage state, and set the first switching element to an on state by supplying the voltage of the second node to the first switching element as the first control voltage when the second oscillation signal is in the second voltage state; a second switching control unit configured to set the second switching element to an off state by supplying the second voltage to the second switching element as the second control voltage when the fourth oscillation signal is in the first voltage state, and set the second switching element to an on state by supplying the voltage of the first node to the second switching element as the second control voltage when the fourth oscillation signal is in the second voltage state; a first output switching element which is turned on only when the first control voltage is in the second voltage state and applies the voltage of the first node to the output node; and a second output switching element which is turned on only when the second control voltage is in the second voltage state, and applies the voltage of the second node to the output node.
A semiconductor memory device of the present invention is a semiconductor memory device including a plurality of memory cells, and a voltage generation circuit generating a voltage for writing data into the memory cells or reading data from the memory cells, the voltage generation circuit including: an oscillation signal generating unit that generates an oscillation signal in which a first voltage state and a second voltage state are alternately repeated; a capacitor having one end receiving the oscillation signal and the other end connected to the output node; a switching element receiving a control voltage and being set to an on state or an off state according to the control voltage, the first voltage being applied to the output node when the on state is set; and a switching control unit configured to set the switching element to an off state by supplying the second voltage to the switching element as the control voltage when the oscillation signal is in the first voltage state, and set the switching element to an on state by supplying the voltage of the output node to the switching element as the control voltage when the oscillation signal is in the second voltage state.
A voltage generation method of the present invention is a voltage generation method of a voltage generation circuit including an oscillation signal generation unit that generates an oscillation signal in which a first voltage state and a second voltage state are alternately repeated; a capacitor having one end receiving the oscillation signal and the other end connected to the output node; and a switching element configured to receive a control voltage and set to an on state or an off state according to the control voltage, wherein the switching element is set to the off state by applying the first voltage to the output node when the switching element is set to the on state and supplying the second voltage to the switching element as the control voltage when the oscillation signal is in the first voltage state, and the switching element is set to the on state by supplying the voltage of the output node to the switching element as the control voltage when the oscillation signal is in the second voltage state.
[ Effect of the invention ]
In the present invention, an oscillation signal in which a first voltage state and a second voltage state are alternately repeated is supplied to one end of a capacitor. An output node for generating a dc voltage is connected to the other end of the capacitor.
Further, in the present invention, the switching element that is turned off when the oscillation signal is in the first voltage state and turned on when the oscillation signal is in the second voltage state and applies the first voltage to the output node is controlled by the switching control unit as follows, thereby generating the dc voltage at the output node.
That is, when the oscillation signal is in the first voltage state, the switching control unit supplies the second voltage as the control voltage to the switching element, thereby setting the switching element to the off state. On the other hand, when the oscillation signal is in the second voltage state, the switching control unit supplies the voltage of the output node to the switching element as the control voltage, thereby setting the switching element to the on state.
According to the switching control unit, even when the dc voltage generated at the output node is higher or lower than either of the first voltage and the second voltage, the switching element can be reliably set to the on state or the off state. Further, since the switch control unit can be configured by an inverter including a pair of transistors each having a gate receiving the oscillation signal, the circuit scale and the power consumption can be reduced.
Drawings
Fig. 1 is a block diagram showing a schematic configuration of a semiconductor memory device 200 including a voltage generation circuit according to the present invention.
Fig. 2 is a circuit diagram showing an example of the configuration of the voltage generation circuit 10 of the present invention.
Fig. 3 is a circuit diagram showing another example of the configuration of the voltage generation circuit 10.
Fig. 4 is a timing chart showing an example of the internal operation of the voltage generation circuit 10 shown in fig. 3.
Fig. 5 is a circuit diagram showing a modification of the voltage generation circuit 10 shown in fig. 4.
Fig. 6 is a timing chart showing an example of the internal operation of the voltage generation circuit 10 shown in fig. 5.
Fig. 7 is a circuit diagram showing a configuration of the voltage generation circuit 20 that generates a positive-polarity voltage obtained by boosting the power supply voltage.
Fig. 8 is a timing chart showing an example of the internal operation of the voltage generation circuit 20 shown in fig. 7.
Description of the symbols
10. 20: voltage generation circuit
11. 11a, 11 b: clock generation unit
12. 22: negative voltage generating part
13. 23, 33, 43: switch control unit
32. 42: voltage boosting part
C1, C3: capacitor with a capacitor element
Detailed Description
Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
Fig. 1 is a block diagram showing a schematic configuration of a semiconductor memory device 200 including a voltage generation circuit according to the present invention. The semiconductor memory device 200 includes: a power supply section 100, a memory cell array 101, a row decoder 102, a memory control section 103, and a column decoder 104.
The memory cell array 101 includes bit lines BL1 to BLm (m is an integer of 2 or more), and word lines WL1 to WLn (n is an integer of 2 or more) arranged to intersect the bit lines BL1 to BLm. Further, a memory cell (not shown) is formed at each intersection portion of the bit line BL and the word line WL. Each of the memory cells writes and reads 2-value or multi-value data based on a selection voltage supplied via a word line WL and a write voltage or a read voltage supplied via a bit line BL.
The row decoder 102 applies a selection voltage for data reading or writing to the word lines WL1 to WLn of the memory cell array 101 in accordance with a control signal supplied from the memory control unit 103.
The column decoder 104 applies a ground voltage, a read voltage, or a write voltage to the bit lines BL1 to BLm of the memory cell array 101 in accordance with a control signal supplied from the memory control unit 103.
The memory control unit 103 supplies various control signals for causing the memory cell array 101 to write, read, or erase data to the row decoder 102 and the column decoder 104 from the outside based on memory control signals and addresses indicating a write command, a read command, and the like.
The power supply unit 100 generates an internal power supply voltage for operating the memory control unit 103 based on a power supply voltage VCC supplied from an external power supply (not shown), and supplies the internal power supply voltage to the memory control unit 103. The power supply unit 100 generates various voltages for a write voltage, a read voltage, and an erase voltage based on the power supply voltage VCC, and supplies the voltages to the column decoder 104.
Further, the power supply unit 100 generates a negative voltage for the selection voltage based on the power supply voltage VCC, and supplies the negative voltage to the row decoder 102.
Fig. 2 is a circuit diagram showing an example of the configuration of the voltage generation circuit 10 included in the power supply unit 100 and generating, for example, the dc voltage Vout as a negative voltage for selecting a voltage.
As shown in fig. 2, the voltage generation circuit 10 includes: a clock generation unit 11, a negative voltage generation unit 12, and a switch control unit 13.
The clock generating unit 11 generates a clock signal CK1 and a clock signal CK1B, which is a so-called reverse phase signal that inverts the phase of the clock signal CK1, as oscillation signals that alternately repeat a state of a positive power supply voltage VCC and a state of a ground voltage VSS (for example, 0 volt) lower than the positive power supply voltage VCC, and supplies the oscillation signals to the negative voltage generating unit 12 and the switch control unit 13.
The negative voltage generator 12 is a so-called charge pump circuit including a transistor N0 of an N-channel Metal Oxide Semiconductor (Metal Oxide Semiconductor), a capacitor C1, and a capacitor C2.
The capacitor C1 receives the clock signal CK1 at one end thereof. The other end of the capacitor C1 is connected to the node n 1. One end of the capacitor C2 is connected to the node n1, and the ground voltage VSS is applied to the other end thereof.
The source of the transistor N0 is applied with the ground voltage VSS, and the drain thereof is connected to the node N1. The gate of the transistor N0 is connected to the switch controller 13 via a node N3.
The switch control unit 13 includes a P-channel MOS transistor P1 and an N-channel MOS transistor N1.
The gates of the transistor P1 and the transistor N1 receive a clock signal CK1B that is a reverse phase signal of the clock signal CK 1. The drains of the transistor P1 and the transistor N1 are connected to the gate of the transistor N0 of the negative voltage generator 12 via a node N3. The source of the transistor N1 is connected to the node N1, and the power supply voltage VCC is applied to the source of the transistor P1.
The operation of the voltage generation circuit 10 shown in fig. 2 will be described below.
First, in a state where the node n1 is at a negative voltage, the capacitor C1 is charged in response to the clock signal CK1 while the clock signal CK1 is at the power supply voltage VCC (hereinafter, also referred to as a state of logic level 1). In this period, the clock signal CK1B is the ground voltage VSS. Thus, the transistor P1 is turned on by the clock signal CK1B, and the power supply voltage VCC is applied to the gate of the transistor N0 as a control voltage via the transistor P1 and the node N3. Thus, the transistor N0 is turned on, and the ground voltage VSS is applied to the node N1 through the transistor N0.
Thereafter, when the clock signal CK1 transitions from the state of the power supply voltage VCC to the state of the ground voltage VSS (hereinafter, also referred to as the state of logic level 0), the capacitor C1 discharges, and the voltage of the node n1 drops. As a result, the voltage at the node n1 becomes negative. The capacitor C2 maintains the state of the voltage of the node n1 with negative polarity. In this period, the clock signal CK1B is the power supply voltage VCC. Thus, the transistor N1 is turned on by the clock signal CK1B, and the negative voltage at the node N1 is applied as a control voltage to the gate of the transistor N0 via the transistor N1 and the node N3. Thus, the transistor N0 becomes off.
As described above, in the voltage generation circuit 10 shown in fig. 2, the above-described series of operations are repeated based on the clock signal CK1 and the clock signal CK1B which is a phase-inverted signal thereof, whereby a negative voltage is generated at the node n1 and is output as the dc voltage Vout. Further, the negative voltage value of the voltage Vout can be set to an arbitrary voltage value by the capacitances of the capacitor C1 and the capacitor C2.
Here, in order to reliably set the transistor N0 connected to the node N1 in the negative voltage state to the on state and the off state, the switch control unit 13 shown in fig. 2 is configured by an inverter including a transistor P1 and a transistor N1.
That is, while the clock signal CK1B is in the logic level 1 state, the transistor N1 of the transistor P1 and the transistor N1 is turned on, and a negative voltage is supplied as a control voltage to the gate of the transistor N0 via the transistor N1 and the node N3. At this time, the negative voltage of the node N1 is applied to the drain of the transistor N0, but the voltage of the node N1, which is the negative voltage, is applied to the gate thereof, so that the transistor N0 is reliably set to the off state and maintained in the above state.
On the other hand, while the clock signal CK1B is at the logic level 0, the transistor P1 of the transistor P1 and the transistor N1 is turned on, and the power supply voltage VCC at the node N1 is supplied as a control voltage to the gate of the transistor N0 via the transistor P1 and the node N3. At this time, the transistor N0 is reliably set to the on state because the power supply voltage VCC is applied to the gate thereof.
As described above, in the voltage generation circuit 10, when the clock signal CK1B is in the state of the power supply voltage VCC, the transistor N0 that generates a negative voltage of direct current at the node N1 is controlled as follows by being turned off, and when the clock signal CK1B is in the state of the ground voltage VSS, the transistor N0 is turned on and applies the ground voltage VSS to the node N1.
That is, when CK1B, which is the reverse phase signal of the clock signal CK1, is in the state of the power supply voltage VCC, the switch control unit 13 sets the transistor N0 to the off state by supplying the voltage of the node N1 to the gate of the transistor N0 as the control voltage. On the other hand, when the clock signal CK1B is in the state of the ground voltage VSS, the switch control unit 13 sets the transistor N0 to the on state by supplying the power supply voltage VCC to the gate of the transistor N0 as a control voltage.
According to such a switch control unit, even if the dc voltage generated at the output node is a negative voltage lower than the ground voltage VSS, the transistor N0 can be reliably set to the off state. Further, as shown in fig. 2, since the switch control unit 13 can be configured by an inverter including a pair of transistors (P1, N1) receiving a reverse phase signal CK1B of the clock signal CK1 at their gates, the circuit scale and the power consumption can be suppressed.
Fig. 3 is a circuit diagram showing another example of the configuration of the voltage generation circuit 10.
The voltage generation circuit 10 shown in fig. 3 includes a clock generation unit 11a, a first circuit block BLK1, and a second circuit block BLK 2.
As shown in fig. 3, the clock generator 11a generates a clock signal CK1 as an oscillation signal in which the state of the positive power supply voltage VCC and the state of the ground voltage VSS (for example, 0 volt) are alternately repeated, and supplies the oscillation signal to the first circuit block BLK 1.
Further, as shown in fig. 3, the clock generator 11a generates a clock signal CK1B as an oscillation signal for inverting the phase of the clock signal CK1, and supplies the clock signal to the second circuit block BLK 2.
The circuit block BLK1 includes the negative voltage generation unit 12 and the switch control unit 13 shown in fig. 2, and an n-channel MOS transistor SW 1. In the circuit block BLK1, the source of the transistor N1 of the switch control unit 13 is not connected to the node N1, but is connected to the node N2 included in the circuit block BLK 2.
In the circuit block BLK1, the node N1 is connected to the source of the transistor SW1, and the gate of the transistor SW1 is connected to the drains of the transistors P1 and N1 and the gate of the transistor P0 via the node N3. The drain of the transistor SW1 is connected to the node n 0.
The circuit block BLK2 includes a negative voltage generation section 22, a switch control section 23, and an n-channel MOS transistor SW 2.
The negative voltage generator 22 has the same circuit configuration as that of the negative voltage generator 12, i.e., a transistor P0, a capacitor C1, and a capacitor C2. The switch control unit 23 is configured by a circuit similar to that of the switch control unit 13, that is, an inverter including a transistor P1 and a transistor N1.
In the negative voltage generating section 22, the capacitor C1 receives the clock signal CK1B at one end thereof. The other terminal of the capacitor C1 is connected to the node n 2. One end of the capacitor C2 is connected to the node n2, and the ground voltage VSS is applied to the other end thereof.
Further, in the negative voltage generating section 22, the ground voltage VSS is applied to the drain of the transistor P0, and the source of the transistor P0 is connected to the node n 2. The gate of the transistor P0 is connected to the drains of the transistors P1 and N1 of the switch control unit 23 and the gate of the transistor SW2 via a node N4.
The source of the transistor SW2 is connected to the node n2, and the drain is connected to the node n 0.
In the switch control unit 23, the clock signal CK1B is received at the gates of the transistor P1 and the transistor N1, respectively. Further, in the switch controller 23, the source of the transistor N1 is connected to the node N1 of the circuit block BLK1, and the power supply voltage VCC is applied to the source of the transistor P1.
Hereinafter, the operation of the voltage generation circuit 10 including the configuration shown in fig. 3 will be described with reference to the timing chart shown in fig. 4.
For example, as shown in fig. 4, in the even-numbered cycle CY2, cycle CY4, and cycle CY6 … in which the clock signal CK1 is at the power supply voltage VCC, the capacitor C1 of the negative voltage generation section 12 included in the circuit block BLK1 is charged in accordance with the clock signal CK 1. Further, in this period, the transistor N1 of the switch control unit 13 is turned on by the clock signal CK 1. Thus, the voltage at the node N2 of the circuit block BLK2, that is, the control voltage having the voltage Va of negative polarity described later is applied to the gate of the transistor P0 of the negative voltage generator 12 via the transistor N1 and the node N3 of the switching controller 13. Thus, the transistor P0 is turned on, and the ground voltage VSS is applied to the node n 1.
That is, as shown in fig. 4, in the even-numbered cycle CY2, cycle CY4, and cycle CY6 …, the node n1 on the circuit block BLK1 side is in the state of the ground voltage VSS, and the node n3 is in the state of the negative voltage Va.
Thereafter, when the clock signal CK1 transitions from the state of the power supply voltage VCC to the state of the ground voltage VSS, the capacitor C1 of the negative voltage generation unit 12 is discharged, and the voltage of the node n1 decreases. As a result, at the node n1, a data packet is generated
Va＝-C1u·VCC/(C1u+C2u)
C1 u: electrostatic capacity of C1
C2 u: electrostatic capacity of C2
The voltage Va of negative polarity is shown.
Further, while the clock signal CK1 is in the state of the ground voltage VSS, the transistor P1 of the switch control unit 13 is turned on, and the power supply voltage VCC is applied to the node n 3.
Therefore, as shown in fig. 4, in the odd-numbered cycle CY1, cycle CY3, and cycle CY5 …, the node n1 on the circuit block BLK1 side is in the state of the negative polarity voltage Va, and the node n3 is in the state of the power supply voltage VCC.
In the odd-numbered cycle CY1, cycle CY3, and cycle CY5 … in which the clock signal CK1B is at the power supply voltage VCC, the capacitor C1 of the negative voltage generation section 22 included in the circuit block BLK2 is charged in accordance with the clock signal CK 1B. During this period, the transistor N1 of the switch control unit 23 is turned on by the clock signal CK1B, and the negative voltage at the node N1 on the circuit block BLK1 side is applied as a control voltage to the gate of the transistor P0 of the negative voltage generation unit 22 via the transistor N1 and the node N4 of the switch control unit 23. Thus, the transistor P0 is turned on, and the ground voltage VSS is applied to the node n2 through the transistor P0.
That is, as shown in fig. 4, in the odd-numbered cycle CY1, cycle CY3, and cycle CY5 …, the node n2 on the circuit block BLK2 side is in the state of the ground voltage VSS, and the node n4 is in the state of the negative voltage Va.
Thereafter, when the clock signal CK1B transitions from the state of the power supply voltage VCC to the state of the ground voltage VSS, the capacitor C1 of the negative voltage generation unit 22 is discharged, and the voltage of the node n2 decreases. As a result, at the node n2, a data packet is generated
Va＝-C1u·VCC/(C1u+C2u)
C1 u: electrostatic capacity of C1
C2 u: electrostatic capacity of C2
The voltage Va of negative polarity is shown.
Further, while the clock signal CK1B is in the state of the ground voltage VSS, the transistor P1 of the switch control unit 23 is turned on, and the power supply voltage VCC is applied to the node n 4.
Therefore, as shown in fig. 4, in the even-numbered cycle CY2, cycle CY4, and cycle CY6 …, the node n2 on the circuit block BLK2 side is in the state of the negative polarity voltage Va, and the node n4 is in the state of the power supply voltage VCC.
Here, as shown in fig. 4, while the node n3 is in the state of the power supply voltage VCC, the transistor SW1, which is the output switching element of the circuit block BLK1, is in the on state. On the other hand, while the node n4 is in the state of the power supply voltage VCC, the transistor SW2, which is the output switching element of the circuit block BLK2, is in the on state.
Thus, in the odd-numbered periods CY1, CY3, and CY5 … shown in fig. 4, the voltage Va of the negative polarity generated at the node n1 on the circuit block BLK1 side is applied to the node n0 via the transistor SW 1.
On the other hand, in the even-numbered periods CY2, CY4, and CY6 … shown in fig. 4, the negative-polarity voltage Va generated at the node n2 on the circuit block BLK2 side is applied to the node n0 via the transistor SW 2.
In this way, in the voltage generation circuit 10 shown in fig. 3, the circuit blocks BLK1 and BLK2 alternately generate the negative voltage Va in response to the clock signal CK1 and the clock signal CK 1B. At this time, the circuit blocks BLK1 and BLK2 alternately apply the negative voltage Va generated by themselves to the node n0, and output the negative voltage Va as the dc voltage Vout.
Therefore, if the configuration shown in fig. 3 is adopted as the voltage generation circuit 10, the negative dc voltage Vout that suppresses voltage fluctuation can be generated as compared with the case where the configuration shown in fig. 2 is adopted.
Further, even in the voltage generation circuit 10 having the configuration shown in fig. 3, the transistor P0 included in the negative voltage generation unit 12(22) and the transistors SW1 and SW2 as the output switching elements are controlled as follows, similarly to the configuration shown in fig. 2.
That is, when the clock signal CK1(CK1B) is at the ground voltage VSS, the switch control unit 13(23) supplies the power supply voltage VCC to the gates of the transistor P0, the transistor SW1, and the transistor SW2 as a control voltage. Thereby, the transistor P0 is set to an off state, and the transistor SW1 and the transistor SW2 as output switching elements are set to an on state. On the other hand, when the clock signal CK1(CK1B) is in the state of the power supply voltage VCC, the switch control unit 13(23) supplies the voltage of the node n2(n1) to the gate of each of the transistor P0, the transistor SW1, and the transistor SW2 as a control voltage. Thereby, the transistor P0 is set to an on state, and the transistor SW1 and the transistor SW2 as output switching elements are set to an off state.
According to the switch control unit, even when the dc voltage generated at the node n1(n2) is the negative voltage Va lower than the ground voltage VSS, the transistor P0 can be reliably turned on, and the transistor SW1 and the transistor SW2 can be reliably turned off.
Further, as shown in fig. 3, since the switch control sections 13 and 23 can be constituted by inverters including a pair of transistors (P1 and N1) receiving the clock signal CK1(CK1B) at their gates, the circuit scale and the power consumption can be suppressed.
Fig. 5 is a circuit diagram showing a modification of the voltage generation circuit 10 shown in fig. 3.
In the configuration shown in fig. 5, a clock generation unit 11b is used instead of the clock generation unit 11a shown in fig. 3. The voltage generation circuit 10 shown in fig. 5 includes a circuit block BLK1 including the negative voltage generation unit 12, the switch control unit 13, and the transistor SW1, and a circuit block BLK2 including the negative voltage generation unit 22, the switch control unit 23, and the transistor SW2, in the same manner as the configuration shown in fig. 3.
The clock generation unit 11b generates the clock signal CK1 and the clock signal CK1B, and generates the clock signal CK2 and the clock signal CK3 shown in fig. 6 as oscillation signals having the same frequency as the clock signal CK 1.
As shown in fig. 6, the phase of the rising edge of the clock signal CK2 is earlier than the phase of the rising edge of the clock signal CK1 by time t 1. Here, the phase of the falling edge of the clock signal CK2 is the same as the phase of the falling edge of the clock signal CK 1B.
As shown in fig. 6, the phase of the rising edge of the clock signal CK3 is earlier than the phase of the rising edge of the clock signal CK1B by a time t 2. Here, the phase of the falling edge of the clock signal CK3 is the same as the phase of the falling edge of the clock signal CK 1B.
The clock generation unit 11b supplies the clock signal CK1 to the capacitor C1 of the negative voltage generation unit 12, and supplies the clock signal CK2 to the gate of each of the transistor P1 and the transistor N1 of the switch control unit 13.
Further, the clock generation unit 11b supplies the clock signal CK1B to the capacitor C1 of the negative voltage generation unit 22, and supplies the clock signal CK3 to the gate of each of the transistor P1 and the transistor N1 of the switch control unit 23.
The operation of the configuration shown in fig. 5 will be described below with reference to the timing chart shown in fig. 6. As shown in fig. 6, the clock signal CK1 maintains the state of logic level 0 during a period from a time point when the clock signal CK2 transits from the state of logic level 0 (VSS) to the state of logic level 1 (VCC) to an elapsed time t 1.
Therefore, in the period Ta shown in fig. 6, the transistor N1 of the switch control unit 13 is turned on, and the ground voltage VSS, which is the voltage of the node N2 of the circuit block BLK2, is applied to the node N3. Therefore, in the period Ta, as shown in fig. 6, the voltage of the node n3 is temporarily maintained at the ground voltage VSS.
Then, the clock signal CK1 transitions from a state of logic level 0 to a state of logic level 1, and the clock signal CK1B transitions from a state of logic level 1 to a state of logic level 0. At this time, the voltage at the node n2 of the circuit block BLK2 shifts to the negative voltage Va, and along with this, the node n3 of the circuit block BLK1 also enters the state of the negative voltage Va.
In this way, the timing of the rising edge of the clock signal CK1 is made later than the timing of the rising edge of the clock signal CK2, whereby the voltage of the node n3 is temporarily lowered from the state of the power supply voltage VCC to the state of the ground voltage VSS, and the state is maintained. This prevents the node n2 from rapidly rising due to the voltage of the node n3 and causing a voltage fluctuation in the process of generating a negative voltage at the node n 2.
As shown in fig. 6, the clock signal CK1B maintains the state of logic level 0 during a period from a time point when the clock signal CK3 transits from the state of logic level 0 (VSS) to the state of logic level 1 (VCC) to an elapsed time t 2.
Therefore, in the period Tb shown in fig. 6, the transistor N1 of the switch control unit 23 is turned on, and the ground voltage VSS, which is the voltage of the node N1 of the circuit block BLK1, is applied to the node N4. Therefore, in the period Tb, the voltage of the node n4 is temporarily maintained at the ground voltage VSS as shown in fig. 6.
Then, the clock signal CK1B transitions from the state of logic level 0 to the state of logic level 1. At this time, the voltage at the node n1 of the circuit block BLK1 shifts to the negative voltage Va, and along with this, the node n4 of the circuit block BLK2 also enters the state of the negative voltage Va.
In this way, the timing of the rising edge of the clock signal CK1B is made later than the timing of the rising edge of the clock signal CK3, whereby the voltage of the node n4 is temporarily lowered from the state of the power supply voltage VCC to the state of the ground voltage VSS, and the state is maintained. This prevents the node n1 from rapidly rising due to the voltage of the node n4 and causing a voltage fluctuation in the process of generating a negative voltage at the node n 1.
Therefore, by adopting the configuration shown in fig. 5, voltage fluctuations of the negative-polarity voltages generated at the node n1 and the node n2 by the negative voltage generator 12 and the negative voltage generator 22 can be suppressed.
Fig. 5 shows a configuration in which the present invention is applied to the voltage generation circuit 10 that generates a negative voltage, but the present invention can be similarly applied to a circuit that generates a positive voltage obtained by boosting a power supply voltage.
Fig. 7 is a circuit diagram showing a configuration of the voltage generation circuit 20 that generates a voltage obtained by boosting the power supply voltage. In the configuration shown in fig. 7, the clock generation unit 11b is used similarly to the configuration shown in fig. 5, and the circuit blocks BLK10 and BLK20 are used instead of the circuit blocks BLK1 and BLK2 shown in fig. 5.
The circuit block BLK10 shown in fig. 7 includes a voltage boosting section 32, a switch control section 33, and a p-channel MOS transistor SW3 as an output switching element.
The voltage boost unit 32 includes a capacitor C3 and an N-pass MOS transistor N0. The capacitor C3 receives the clock signal CK1 at one end thereof and is connected to the node n1 at the other end thereof.
The transistor N0 has a drain to which a power supply voltage VCC is applied and a source connected to the node N1. A gate of the transistor N0 is connected to the switch control unit 33 and the gate of the transistor SW3 via a node N3.
The switch control unit 33 includes a P-channel MOS transistor P10 and an N-channel MOS transistor N10.
The clock signal CK2 is supplied to the gate of each of the transistor P10 and the transistor N10, and the drain of each of the transistor P10 and the transistor N10 is connected to the gate of each of the transistor N0 and the transistor SW3 via the node N3. The source of the transistor P10 is connected to the node N2 of the circuit block BLK20, and the ground voltage VSS is applied to the source of the transistor N10. The source of the transistor SW3 is connected to the node n1, and the drain thereof is connected to the node n 0.
The circuit block BLK20 includes a voltage boosting section 42, a switch control section 43, and a p-channel MOS transistor SW4 as an output switching element.
The voltage boost unit 42 includes a capacitor C3 and an N-channel MOS transistor N0, similarly to the voltage boost unit 32. The capacitor C3 of the voltage boosting section 42 receives the clock signal CK1B at one end thereof and is connected to the node n2 at the other end thereof. The power supply voltage VCC is applied to the drain of the transistor N0 of the voltage step-up unit 42, and the source thereof is connected to the node N2. A gate of the transistor N0 is connected to the switch control unit 43 and the gate of the transistor SW4 via the node N4.
The switch control unit 43 includes a P-channel MOS transistor P10 and an N-channel MOS transistor N10, as in the switch control unit 33.
The clock signal CK3 is supplied to the gate of each of the transistor P10 and the transistor N10, and the drain of each of the transistor P10 and the transistor N10 is connected to the gate of each of the transistor N0 and the transistor SW4 of the voltage boosting section 42 via the node N4. The source of the transistor P10 of the switch control unit 43 is connected to the node N1 of the circuit block BLK10, and the ground voltage VSS is applied to the source of the transistor N10. The source of the transistor SW4 is connected to the node n2, and the drain thereof is connected to the node n 0.
The operation of the voltage generation circuit 20 shown in fig. 7 will be described below with reference to the timing chart shown in fig. 8.
As shown in fig. 8, when the clock signal CK1 and the clock signal CK2 are in a state of being at the ground voltage VSS in common and the clock signal CK1B and the clock signal CK3 are in a state of being at the power supply voltage VCC in common, the node n3 is in a state of being at the voltage (2 · VCC). Thereby, the transistor SW3 is turned off, the transistor N0 is turned on, and the node N1 is in the state of the power supply voltage VCC. During this period, the capacitor C3 of the voltage boost unit 32 is charged.
Next, when the clock signal CK1 and the clock signal CK2 are transferred to the power supply voltage VCC in common and the clock signal CK1B and the clock signal CK3 are transferred to the ground voltage VSS in common, the capacitor C3 of the voltage boosting section 32 is discharged, and the voltage at the node n1 is boosted to 2 · VCC in accordance with the discharge. While the clock signal CK2 is in the state of the power supply voltage VCC, the transistor N10 of the switch control unit 33 is turned on, and the ground voltage VSS is applied to the node N3. Thereby, the transistor SW3 is turned on, and the voltage at the node n1, i.e., the boosted voltage (2 · VCC) is output as the dc voltage VQout via the node n 0.
However, as shown in fig. 8, the clock generation unit 11b shifts the clock signal CK2 from the power supply voltage VCC to the ground voltage VSS at a timing earlier by time t2 than the timing at which the clock signal CK1 is shifted from the power supply voltage VCC to the ground voltage VSS. Therefore, in the period Tb shown in fig. 8, the clock signal CK2 is in the state of the ground voltage VSS, and therefore the transistor P10 is in the on state, and the power supply voltage VCC, which is the voltage of the node n2 of the circuit block BLK20, is applied to the node n 3. Further, the capacitor C3 of the voltage boost section 42 is charged with the power supply voltage VCC applied to the node n 2.
Then, the clock signal CK1B transits to the power supply voltage VCC, and the capacitor C3 of the voltage boosting unit 42 is discharged, so that the voltage at the node n2 is boosted to 2 · VCC along with this. In this period, since the clock signal CK2 is at the ground voltage VSS, the transistor P10 of the switch control unit 33 is turned on, and the voltage (2 · VCC) of the node n2 is applied to the node n 3. Therefore, the transistor N0 of the voltage boosting section 32 is turned on, and the transistor SW3 is turned off.
Further, in the period, since the clock signal CK3 is in the state of the power supply voltage VCC, the transistor N10 of the switch control unit 43 is turned on, and the ground voltage VSS is applied to the node N4. Thereby, the transistor N0 of the voltage boosting section 42 is turned off, and the transistor SW4 is turned on. Thus, the voltage (2 · VCC) boosted at the node n2 as described above is output as the voltage VQout via the transistor SW4 and the node n 0.
Therefore, in the odd-numbered periods CY1, CY3, and … shown in fig. 8, the positive-polarity voltage (2 · VCC) generated at the node n1 on the circuit block BLK10 side is applied to the node n0 via the transistor SW 3.
On the other hand, in even-numbered cycles CY2, CY4, and … shown in fig. 8, the positive-polarity voltage (2 · VCC) generated at the node n2 on the circuit block BLK20 side is applied to the node n0 via the transistor SW 4.
In this way, the voltage generation circuit 20 alternately generates a positive voltage (2 · VCC) from the clock signal CK1, the clock signal CK1B, the clock signal CK2, and the clock signal CK3, and the circuit block BLK10 and the circuit block BLK 20. At this time, the circuit blocks BLK10 and BLK20 alternately apply the positive voltage (2 · VCC) generated by themselves to the node n0, thereby outputting the positive voltage (2 · VCC) as the dc voltage Vout.
Here, in the voltage generation circuit 20, the transistor N0 which is turned off when the clock signal CK2(CK3) is in the state of the power supply voltage VCC and turned on when the clock signal CK2(CK3) is in the state of the ground voltage VSS is controlled as follows, and applies the power supply voltage VCC to the node N1 (N2).
That is, when the clock signal CK2(CK3) is in the state of the power supply voltage VCC, the switch control unit 33(43) supplies the ground voltage VSS as a control voltage to the gate of each of the transistor N0, the transistor SW3, and the transistor SW 4. Thereby, the transistor N0 is set to an off state, and the transistor SW3 and the transistor SW4 as output switching elements are set to an on state. On the other hand, when the clock signal CK2(CK3) is in the state of the ground voltage VSS, the switch control unit 33(43) supplies the voltage of the node N2(N1) to the gate of each of the transistor N0, the transistor SW3, and the transistor SW4 as a control voltage. Thereby, the transistor N0 is set to an on state, and the transistor SW3 and the transistor SW4 as output switching elements are set to an off state.
By the operation of the switch control units 33 and 43, even when the dc voltage generated at the node N1(N2) is higher than the power supply voltage VCC, the transistor N0 is reliably set to the on state, and the transistors SW3 and SW4 as the output switching elements are reliably set to the off state.
Further, as shown in fig. 7, since the switch control section 33(43) can be constituted by an inverter including a pair of transistors (P10, N10) receiving the clock signal CK2(CK3) at their gates, the circuit scale and the power consumption can be suppressed.
In the configuration shown in fig. 7, the positive voltage (2 · VCC) is alternately generated by the power block BLK10 and the circuit block BLK20 of the 2-system, but the voltage generation circuit 20 may be configured by only one of the circuit block BLK10 and the circuit block BLK 20. For example, when the voltage generation circuit 20 is configured by only the circuit block BLK10, the source of the transistor P10 of the switch control unit 33 is connected to the node n 1.
In short, the voltage generation circuit of the present invention may be any voltage generation circuit including the following oscillation signal generation unit, capacitor, switching element, and switching control unit.
That is, the oscillation signal generating units (11, 11a, 11b) generate oscillation signals (CK1, CK1B, CK2, CK3) that alternately repeat a state of a first voltage (for example, one of VCC and VSS) and a state of a second voltage (for example, the other of VCC and VSS). The capacitor receives the oscillation signal at one end thereof, and is connected to output nodes (n1, n2, n0) that generate a direct-current voltage at the other end thereof. The switching elements (P0, N0) receive control voltages (Va, VSS, VCC, 2. VCC) and are set to an on state or an off state according to the control voltages, and apply a first voltage to an output node when set to the on state. When the oscillation signal is in the first voltage state, the switching control unit (13, 23, 33, 43) supplies a second voltage as a control voltage to the switching element, thereby setting the switching element to an off state. When the oscillation signal is in the second voltage state, the voltage of the output node is supplied as a control voltage to the switching element, thereby setting the switching element to an on state.

Claims (8)

1. A voltage generation circuit for generating a DC voltage at an output node, comprising:
an oscillation signal generating unit that generates an oscillation signal in which a first voltage state and a second voltage state are alternately repeated;
a capacitor having one end receiving the oscillation signal and the other end connected to the output node;
a switching element receiving a control voltage and being set to an on state or an off state according to the control voltage, the first voltage being applied to the output node when the on state is set; and
and a switching control unit configured to set the switching element to the off state by supplying the second voltage to the switching element as the control voltage when the oscillation signal is in the first voltage state, and set the switching element to the on state by supplying the voltage of the output node to the switching element as the control voltage when the oscillation signal is in the second voltage state.
2. The voltage generation circuit of claim 1,
the switching element is a transistor, the first voltage is applied to a drain of the transistor, a source of the transistor is connected to the output node,
the switch control unit includes a pair of transistors each having a gate for receiving the oscillation signal and a drain connected to the gate of the transistor, and the second voltage is applied to a source of one of the pair of transistors, and a source of the other of the pair of transistors is connected to the output node.
3. The voltage generation circuit according to claim 1 or 2, wherein the second voltage is a voltage of a positive polarity higher than the first voltage,
the dc voltage is a negative polarity voltage.
4. The voltage generation circuit according to claim 1 or 2, wherein the first voltage is a voltage of a positive polarity higher than the second voltage,
the direct current voltage is a voltage higher than the first voltage.
5. A voltage generation circuit for generating a DC voltage at an output node, comprising:
an oscillation signal generation unit that generates a first oscillation signal in which a first voltage state and a second voltage state are alternately repeated, and a second oscillation signal in which a phase of the first oscillation signal is inverted;
a first node and a second node;
a first capacitor that receives the first oscillation signal at one end and is connected to the first node at the other end;
a second capacitor having one end receiving the second oscillation signal and the other end connected to the second node;
a first switching element set to an on state or an off state according to a first control voltage, the first switching element applying the first voltage to the first node when set to the on state;
a second switching element set to an on state or an off state according to a second control voltage, the second switching element applying the first voltage to the second node when set to the on state;
a first switching control unit configured to set the first switching element to the off state by supplying the second voltage to the first switching element as the first control voltage when the first oscillation signal is in the first voltage state, and set the first switching element to the on state by supplying the voltage of the second node to the first switching element as the first control voltage when the first oscillation signal is in the second voltage state;
a second switching control unit configured to set the second switching element to the off state by supplying the second voltage to the second switching element as the second control voltage when the second oscillation signal is in the first voltage state, and set the second switching element to the on state by supplying the voltage of the first node to the second switching element as the second control voltage when the second oscillation signal is in the second voltage state;
a first output switching element which is turned on only when the first control voltage is in the second voltage state and applies the voltage of the first node to the output node; and
and a second output switching element which is turned on only when the second control voltage is in the second voltage state, and applies the voltage of the second node to the output node.
6. A voltage generation circuit for generating a DC voltage at an output node, comprising:
an oscillation signal generation unit configured to generate a first oscillation signal in which a first voltage state and a second voltage state are alternately repeated, a second oscillation signal in which a phase of a rising edge of the first oscillation signal is advanced by a predetermined time, a third oscillation signal in which a phase of the first oscillation signal is inverted, and a fourth oscillation signal in which a phase of a rising edge of the third oscillation signal is advanced by the predetermined time;
a first node and a second node;
a first capacitor that receives the first oscillation signal at one end and is connected to the first node at the other end;
a second capacitor having one end receiving the third oscillation signal and the other end connected to the second node;
a first switching element set to an on state or an off state according to a first control voltage, the first switching element applying the first voltage to the first node when set to the on state;
a second switching element set to an on state or an off state according to a second control voltage, the second switching element applying the first voltage to the second node when set to the on state;
a first switching control unit configured to set the first switching element to the off state by supplying the second voltage to the first switching element as the first control voltage when the second oscillation signal is in the first voltage state, and set the first switching element to the on state by supplying the voltage of the second node to the first switching element as the first control voltage when the second oscillation signal is in the second voltage state;
a second switching control unit configured to set the second switching element to the off state by supplying the second voltage to the second switching element as the second control voltage when the fourth oscillation signal is in the first voltage state, and set the second switching element to the on state by supplying the voltage of the first node to the second switching element as the second control voltage when the fourth oscillation signal is in the second voltage state;
a first output switching element which is turned on only when the first control voltage is in the second voltage state and applies the voltage of the first node to the output node; and
and a second output switching element which is turned on only when the second control voltage is in the second voltage state, and applies the voltage of the second node to the output node.
7. A semiconductor storage device which includes a plurality of memory cells, and a voltage generation circuit which generates a voltage for writing data into the memory cells or reading data out of the memory cells, and which is characterized in that,
the voltage generation circuit includes:
an oscillation signal generating unit that generates an oscillation signal in which a first voltage state and a second voltage state are alternately repeated;
a capacitor having one end receiving the oscillation signal and the other end connected to an output node;
a switching element receiving a control voltage and being set to an on state or an off state according to the control voltage, the first voltage being applied to the output node when the on state is set; and
and a switching control unit configured to set the switching element to the off state by supplying the second voltage to the switching element as the control voltage when the oscillation signal is in the first voltage state, and set the switching element to the on state by supplying the voltage of the output node to the switching element as the control voltage when the oscillation signal is in the second voltage state.
8. A voltage generation method is a voltage generation method of a voltage generation circuit including an oscillation signal generation section that generates an oscillation signal in which a first voltage state and a second voltage state are alternately repeated; a capacitor having one end receiving the oscillation signal and the other end connected to an output node; and a switching element that receives a control voltage and is set to an on state or an off state according to the control voltage, the first voltage being applied to the output node when the on state is set, and the voltage generation method is characterized in that,
setting the switching element to the off state by supplying the second voltage as the control voltage to the switching element when the oscillation signal is in the first voltage state,
when the oscillation signal is in the second voltage state, the voltage of the output node is supplied as the control voltage to the switching element, thereby setting the switching element to the on state.
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