CN110599979A - Grid driving circuit, grid driving method and display device - Google Patents
Grid driving circuit, grid driving method and display device Download PDFInfo
- Publication number
- CN110599979A CN110599979A CN201910932014.XA CN201910932014A CN110599979A CN 110599979 A CN110599979 A CN 110599979A CN 201910932014 A CN201910932014 A CN 201910932014A CN 110599979 A CN110599979 A CN 110599979A
- Authority
- CN
- China
- Prior art keywords
- transistor
- pull
- module
- circuit unit
- control
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
Abstract
The invention discloses a grid driving circuit which comprises an N-stage circuit unit, wherein the nth-stage circuit unit comprises an up-down pulling control module, an up-down pulling module, a maintaining module and an emptying module; the pull-up and pull-down module of the nth stage circuit unit receives the first clock signal and outputs a grid scanning signal to a grid scanning signal line; the up-down pull control module of the nth-stage circuit unit inputs a preceding-stage clock signal and a grid scanning signal of the (n-1) th-stage circuit unit, and the preceding-stage clock signal is used as a stage transmission signal. The invention can avoid the influence on the potential maintenance of the previous stage circuit in the non-scanning stage and also avoid the influence on the circuit performance caused by the control stage transmission of the grid scanning signal.
Description
Technical Field
The present invention relates to the field of liquid crystal display, and in particular, to a gate driving circuit, a gate driving method, and a display device.
Background
The GDM technology is widely applied to liquid crystal displays, and a GDM circuit architecture adopted at present is shown in fig. 1, and includes a pull-up and pull-down control module, a pull-up and pull-down module, an emptying module, and a maintaining module.
In this type of GDM circuit, the pull-up and pull-down control module usually uses the gate scan signal Gn as a stage signal. At the moment of circuit pre-charging, a Gn signal is adopted for stage transmission, and the Gn signal is easily interfered by a circuit and other signal lines of a display area, so that the circuit performance is influenced; when the circuit is cleared, the potential of the netA point of the pull-up control node at the stage is directly released to a grid scanning signal line of a circuit at the previous stage, so that the potential maintenance of the circuit at the non-scanning time of the previous stage is influenced, and the negative influence is generated on the circuit maintenance.
Disclosure of Invention
In order to solve the above technical problems, the present invention provides a gate driving circuit, a gate driving method and a display device.
The technical scheme provided by the invention is as follows:
the invention discloses a gate drive circuit, which comprises an N (N is a positive integer larger than 1) stage circuit unit, wherein the nth (1 is more than or equal to N and N is a positive integer) stage circuit unit comprises an up-down pull control module, an up-down pull module, a maintaining module and an emptying module; the pull-up and pull-down control module, the pull-up and pull-down module, the maintaining module and the emptying module of the nth stage circuit unit are connected with a pull-up control node; the maintaining module and the emptying module of the nth stage circuit unit input a constant voltage low level; the pull-up module, the pull-down module, the maintaining module and the clearing module of the nth stage circuit unit are connected with the grid scanning signal line of the nth stage circuit unit; the grid scanning signal line outputs a grid scanning signal;
the pull-up and pull-down module of the nth stage circuit unit receives the first clock signal and outputs a grid scanning signal to a grid scanning signal line; the up-down pull control module of the nth-stage circuit unit inputs a preceding-stage clock signal and a grid scanning signal of the (n-1) th-stage circuit unit, and the preceding-stage clock signal is used as a stage transmission signal.
Preferably, the pull-up and pull-down control module of the nth stage circuit unit specifically includes a first transistor and an eleventh transistor;
a control end of the first transistor is used for inputting a preceding-stage clock signal, a first path end of the first transistor is connected to the pull-up control node, and a second path end of the first transistor is connected to a second path end of the eleventh transistor;
the control end of the eleventh transistor is input with a grid scanning signal of the (n-1) th-level circuit unit, the first path end of the eleventh transistor is connected with the control end of the first transistor and is input with a preceding-stage clock signal, and the second path end of the eleventh transistor is connected with the second path end of the first transistor and is connected with the emptying module.
Preferably, the pull-up and pull-down module of the nth stage circuit unit includes:
a tenth transistor, a control terminal of which is connected to the pull-up control node, a first path terminal of which inputs the clock signal, and a second path terminal of which outputs the gate scan signal through the gate scan signal line.
Preferably, the sustain module of the nth stage circuit unit includes a fifth transistor, a sixth transistor, and a thirteenth transistor;
a control end and a first path end of the fifth transistor are connected and input with a constant-voltage high level, and a second path end of the fifth transistor and a first path end of the sixth transistor are connected to a control end of the thirteenth transistor;
a control end of the sixth transistor is connected to the pull-up control node, and a second path end of the sixth transistor inputs a constant voltage low level;
a first path terminal of the thirteenth transistor is connected to a gate scan signal line of the nth stage circuit unit, and a second path terminal of the thirteenth transistor is input with a constant voltage low level.
Preferably, the clearing module of the nth stage circuit unit includes a first clearing module and a second clearing module;
the first emptying module comprises a third transistor and a fourth transistor, wherein the control end of the third transistor inputs an emptying signal, the first path end of the third transistor is connected to a pull-up control node, and the second path end of the third transistor inputs a constant voltage low level; a control end of the fourth transistor inputs a starting signal, a first path end of the fourth transistor is connected to a pull-up control node, and a second path end of the fourth transistor inputs a constant voltage low level;
the second clearing module comprises a second transistor, a control end of the second transistor inputs a clearing signal, a first path end of the second transistor is connected to a grid scanning signal line of the nth stage circuit unit, and a second path end of the second transistor inputs a constant voltage low level.
Preferably, the clearing module of the nth stage circuit unit further includes a third clearing module;
the third emptying module comprises a ninth transistor; the control end of the ninth transistor inputs a grid scanning signal of the (n + 2) th-level circuit unit, the first path end of the ninth transistor is connected to the upper pull-down control module, and the second path end of the ninth transistor inputs a constant voltage low level.
The invention also discloses a display device comprising the grid drive circuit.
The invention also discloses a grid driving method which is suitable for the grid driving circuit.
Compared with the prior art, the invention can bring the following beneficial effects:
1. in the up-down pulling control module, a new TFT is added, a grid scanning signal is only responsible for the opening and closing of the new TFT, and a clock signal controls the stage transmission of a circuit, so that the signal of a net A of a pull-up control node is ensured not to interfere with a grid scanning signal of the previous stage, the main purpose is to avoid the influence on the potential maintenance of the circuit of the previous stage in a non-scanning stage and the influence on the performance of a GDM circuit, and simultaneously, the influence on the circuit performance caused by the control stage transmission of the grid scanning signal is also avoided;
2. and meanwhile, a clearing module is newly added for eliminating the influence of the potential of the netA point of the pull-up control node on the potential maintenance of the previous stage circuit at the non-scanning moment.
Drawings
The present invention will be further described in the following detailed description of preferred embodiments, which is to be read in connection with the accompanying drawings.
FIG. 1 is a schematic diagram of a prior art GDM circuit;
FIG. 2 is a schematic diagram of a gate driving circuit according to the present invention;
fig. 3 is a schematic circuit waveform diagram of a gate driving circuit according to the present invention.
Detailed Description
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following description will be made with reference to the accompanying drawings. It is obvious that the drawings in the following description are only some examples of the invention, and that for a person skilled in the art, other drawings and embodiments can be derived from them without inventive effort.
For the sake of simplicity, the drawings only schematically show the parts relevant to the present invention, and they do not represent the actual structure as a product. In addition, in order to make the drawings concise and understandable, components having the same structure or function in some of the drawings are only schematically illustrated or only labeled. In this document, "one" means not only "only one" but also a case of "more than one".
Fig. 2 is a schematic diagram of a gate driving circuit according to the present invention, and as shown in fig. 2, the gate driving circuit includes N (N is a positive integer greater than 1) stage circuit units, where the nth (1 ≦ N, and N is a positive integer) stage circuit unit includes a pull-up and pull-down control module 01, a pull-up and pull-down module 02, a sustain module 03, and a flush module; the pull-up and pull-down control module 01, the pull-up and pull-down module 02, the maintaining module 03 and the emptying module of the nth stage circuit unit are connected to the pull-up control node netA; the maintaining module 03 and the emptying module of the nth stage circuit unit input a constant voltage low level VSS; the up-down pulling module 01, the maintaining module 03 and the emptying module of the nth-stage circuit unit are connected with a grid scanning signal line of the nth-stage circuit unit; the grid scanning signal line outputs a grid scanning signal Gn;
the pull-up and pull-down module 02 of the nth stage circuit unit receives the first clock signal CKm and outputs the gate scan signal Gn to the gate scan signal line; the pull-up and down control module 01 of the nth stage circuit unit inputs a previous stage clock signal CKm-1 and a gate scan signal Gn-1 of the nth-1 stage circuit unit, and the previous stage clock signal CKm-1 serves as a stage transfer signal.
The pull-up and pull-down control module 01 of the nth stage circuit unit specifically includes a first transistor M1 and an eleventh transistor M1A;
the control terminal of the first transistor M1 inputs the previous stage clock signal CKm-1, the first path terminal of the first transistor M1 is connected to the pull-up control node netAn, and the second path terminal of the first transistor M1 is connected to the second path terminal of the eleventh transistor M1A;
the control end of the eleventh transistor M1A inputs the gate scan signal Gn-1 of the (n-1) th stage circuit unit, and if the stage circuit unit is the first stage circuit unit, the control end of the eleventh transistor M1A inputs the GSP start signal; a first path terminal of the eleventh transistor M1A is connected to the control terminal of the first transistor M1 and inputs the previous stage clock signal CKm-1, and a second path terminal of the eleventh transistor M1A is connected to the second path terminal of the first transistor M1 and connected to the clearing module.
The pull-up and pull-down module 02 of the nth stage circuit unit includes:
a tenth transistor M10, a control terminal of the tenth transistor M10 being connected to the pull-up control node netAn, a first path terminal of the tenth transistor M10 being input with the clock signal CKm, and a second path terminal of the tenth transistor M10 outputting the gate scan signal Gn through the gate scan signal line.
The sustain module 03 of the nth stage circuit unit includes a fifth transistor M5, a sixth transistor M6, and a thirteenth transistor M13;
a control terminal and a first path terminal of the fifth transistor M5 are connected and input with a constant high voltage VGH, a second path terminal of the fifth transistor M5 and a first path terminal of the sixth transistor M6 are connected to a control terminal of the thirteenth transistor M13;
a control terminal of the sixth transistor M6 is connected to the pull-up control node netAn, and a second path terminal of the sixth transistor M6 inputs the constant-voltage low level VSS;
a first path terminal of the thirteenth transistor M13 is connected to the gate scan signal line Gn of the nth stage circuit unit, and a second path terminal of the thirteenth transistor M13 is inputted with a constant voltage low level VSS.
The emptying module of the nth stage circuit unit includes a first emptying module 041 and a second emptying module 042;
the first clear module 041 includes a third transistor M3, a control terminal of the third transistor M3 inputs a clear signal CLR, a first path terminal of the third transistor M3 is connected to a pull-up control node netAn, and a second path terminal of the third transistor M3 inputs a constant voltage low level VSS; a control end of the fourth transistor M4 inputs a start signal GSP, and if the circuit unit of the stage is the first two stages, a control end of the fourth transistor M4 inputs a constant voltage low level VSS; a first path terminal of the fourth transistor M4 is connected to the pull-up control node netAn, and a second path terminal of the fourth transistor M4 inputs the constant voltage low level VSS;
the second clear block 042 includes a second transistor M2, a control terminal of the second transistor M2 inputs a clear signal CLR, a first path terminal of the second transistor M2 is connected to a gate scan signal line of the nth stage circuit unit, and a second path terminal of the second transistor M2 inputs a constant voltage low level VSS.
The emptying module of the nth stage circuit unit further comprises a third emptying module 043; the third emptying module 043 comprises a ninth transistor M9; a control terminal of the ninth transistor M9 inputs the gate scan signal Gn +2 of the (n + 2) th stage circuit unit, a first path terminal of the ninth transistor M9 is connected to the upper pull-down control module 01, and a second path terminal of the ninth transistor M9 inputs the constant voltage low level VSS.
In the pull-up and pull-down control module 01 of the present invention, a new TFT, that is, an eleventh transistor M1A, is added, a gate scan signal is only responsible for the switching of the eleventh transistor M1A, and a clock signal CKm controls the stage transmission of the circuit, so as to ensure that a signal of the pull-up control node netA does not interfere with a gate scan signal of a previous stage, and mainly aims to prevent the potential of the previous stage circuit from being influenced during the non-scan stage, thereby affecting the performance of the GDM circuit, and simultaneously prevent the gate scan signal control stage transmission from influencing the circuit performance, and at the same time, the potential of the previous stage circuit at the non-scan time is eliminated by adding the ninth transistor M9, thereby being not influenced by the potential of the pull-up control node netA point of the.
Fig. 3 is a schematic circuit waveform diagram of a gate driving circuit according to the present invention, as indicated by an oval in the figure, when a netA point of an n +1 th level starts to become a low level, and if a gate signal Gn is used as a level transfer signal, the gate signal Gn of the nth level is interfered by the first transistor M1, so that a convex wave appears in the gate signal of the nth level in a non-scanning stage.
The invention also discloses a display device comprising the grid drive circuit.
The invention also discloses a grid driving method which is suitable for the grid driving circuit.
It should be noted that the above embodiments can be freely combined as necessary. The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, various modifications and decorations can be made without departing from the principle of the present invention, and these modifications and decorations should also be regarded as the protection scope of the present invention.
Claims (8)
1. A gate driving circuit includes N (N is a positive integer greater than 1) stages of circuit units, and is characterized in that:
the nth (1 ≦ N ≦ N, and N is a positive integer) stage circuit unit comprises a pull-up and pull-down control module, a pull-up and pull-down module, a maintaining module and a clearing module; the pull-up and pull-down control module, the pull-up and pull-down module, the maintaining module and the emptying module of the nth stage circuit unit are connected with a pull-up control node; the maintaining module and the emptying module of the nth stage circuit unit input a constant voltage low level; the pull-up module, the pull-down module, the maintaining module and the clearing module of the nth stage circuit unit are connected with the grid scanning signal line of the nth stage circuit unit; the grid scanning signal line outputs a grid scanning signal;
the pull-up and pull-down module of the nth stage circuit unit receives the first clock signal and outputs a grid scanning signal to a grid scanning signal line; the up-down pull control module of the nth-stage circuit unit inputs a preceding-stage clock signal and a grid scanning signal of the (n-1) th-stage circuit unit, and the preceding-stage clock signal is used as a stage transmission signal.
2. The gate driving circuit according to claim 1, wherein the pull-up and pull-down control module of the nth stage circuit unit specifically includes a first transistor and an eleventh transistor;
a control end of the first transistor is used for inputting a preceding-stage clock signal, a first path end of the first transistor is connected to the pull-up control node, and a second path end of the first transistor is connected to a second path end of the eleventh transistor;
the control end of the eleventh transistor is input with a grid scanning signal of the (n-1) th-level circuit unit, the first path end of the eleventh transistor is connected with the control end of the first transistor and is input with a preceding-stage clock signal, and the second path end of the eleventh transistor is connected with the second path end of the first transistor and is connected with the emptying module.
3. The gate driving circuit of claim 1, wherein the pull-up and pull-down module of the nth stage circuit unit comprises:
a tenth transistor, a control terminal of which is connected to the pull-up control node, a first path terminal of which inputs the clock signal, and a second path terminal of which outputs the gate scan signal through the gate scan signal line.
4. The gate driving circuit according to claim 1, wherein the sustain module of the nth stage circuit unit includes a fifth transistor, a sixth transistor, and a thirteenth transistor;
a control end and a first path end of the fifth transistor are connected and input with a constant-voltage high level, and a second path end of the fifth transistor and a first path end of the sixth transistor are connected to a control end of the thirteenth transistor;
a control end of the sixth transistor is connected to the pull-up control node, and a second path end of the sixth transistor inputs a constant voltage low level;
a first path terminal of the thirteenth transistor is connected to a gate scan signal line of the nth stage circuit unit, and a second path terminal of the thirteenth transistor is input with a constant voltage low level.
5. The gate driving circuit according to claim 1, wherein the clearing modules of the nth stage circuit unit include a first clearing module and a second clearing module;
the first emptying module comprises a third transistor and a fourth transistor, wherein the control end of the third transistor inputs an emptying signal, the first path end of the third transistor is connected to a pull-up control node, and the second path end of the third transistor inputs a constant voltage low level; a control end of the fourth transistor inputs a starting signal, a first path end of the fourth transistor is connected to a pull-up control node, and a second path end of the fourth transistor inputs a constant voltage low level;
the second clearing module comprises a second transistor, a control end of the second transistor inputs a clearing signal, a first path end of the second transistor is connected to a grid scanning signal line of the nth stage circuit unit, and a second path end of the second transistor inputs a constant voltage low level.
6. The gate driving circuit according to claim 5, wherein the clearing module of the nth stage circuit unit further comprises a third clearing module;
the third emptying module comprises a ninth transistor; the control end of the ninth transistor inputs a grid scanning signal of the (n + 2) th-level circuit unit, the first path end of the ninth transistor is connected to the upper pull-down control module, and the second path end of the ninth transistor inputs a constant voltage low level.
7. A display device, characterized in that: comprising a gate drive circuit as claimed in any one of claims 1 to 6.
8. A gate driving method applied to the gate driving circuit according to any one of claims 1 to 6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910932014.XA CN110599979A (en) | 2019-09-29 | 2019-09-29 | Grid driving circuit, grid driving method and display device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910932014.XA CN110599979A (en) | 2019-09-29 | 2019-09-29 | Grid driving circuit, grid driving method and display device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110599979A true CN110599979A (en) | 2019-12-20 |
Family
ID=68864687
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910932014.XA Pending CN110599979A (en) | 2019-09-29 | 2019-09-29 | Grid driving circuit, grid driving method and display device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110599979A (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080285705A1 (en) * | 2007-05-18 | 2008-11-20 | Au Optronics Corp. | Shift register with individual driving node |
| CN106448594A (en) * | 2016-10-24 | 2017-02-22 | 南京华东电子信息科技股份有限公司 | Gate drive circuit with high reliability |
| CN106601169A (en) * | 2016-12-29 | 2017-04-26 | 南京华东电子信息科技股份有限公司 | Bidirectional scanning gate drive circuit |
| CN107221295A (en) * | 2017-06-27 | 2017-09-29 | 南京中电熊猫平板显示科技有限公司 | Gated sweep drive circuit and liquid crystal display device |
| CN108735177A (en) * | 2018-07-20 | 2018-11-02 | 深圳市华星光电半导体显示技术有限公司 | A kind of GOA circuits and liquid crystal display device |
-
2019
- 2019-09-29 CN CN201910932014.XA patent/CN110599979A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080285705A1 (en) * | 2007-05-18 | 2008-11-20 | Au Optronics Corp. | Shift register with individual driving node |
| CN106448594A (en) * | 2016-10-24 | 2017-02-22 | 南京华东电子信息科技股份有限公司 | Gate drive circuit with high reliability |
| CN106601169A (en) * | 2016-12-29 | 2017-04-26 | 南京华东电子信息科技股份有限公司 | Bidirectional scanning gate drive circuit |
| CN107221295A (en) * | 2017-06-27 | 2017-09-29 | 南京中电熊猫平板显示科技有限公司 | Gated sweep drive circuit and liquid crystal display device |
| CN108735177A (en) * | 2018-07-20 | 2018-11-02 | 深圳市华星光电半导体显示技术有限公司 | A kind of GOA circuits and liquid crystal display device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105206244B (en) | A kind of GOA circuits and liquid crystal display | |
| JP5968452B2 (en) | Display device and driving method thereof | |
| JP3409768B2 (en) | Display device circuit | |
| CN102054426B (en) | Shift buffer circuit | |
| US7764263B2 (en) | Display apparatus and driver circuit of display apparatus having precharged and written simultaneously without collision | |
| US9666140B2 (en) | Display device and method for driving same | |
| US8106874B2 (en) | Shift register and liquid crystal display using same | |
| US20140191935A1 (en) | Liquid crystal display device and driving method thereof | |
| US20030234761A1 (en) | Driver circuit and shift register of display device and display device | |
| US9030397B2 (en) | Gate driver, driving circuit, and LCD | |
| WO2019001059A1 (en) | Gate drive unit circuit, gate drive circuit and liquid crystal display device | |
| CN104732904B (en) | Display device and gate drive circuit and gate drive unit circuit thereof | |
| CN108154856B (en) | Grid scanning driving circuit | |
| CN102368378B (en) | Gate drive unit and gate drive circuit | |
| CN109637484B (en) | Gate driving unit circuit, gate driving circuit and display device | |
| CN205122157U (en) | GOA circuit and LCD | |
| WO2019037435A1 (en) | Gate drive unit circuit, gate drive circuit and liquid crystal display device | |
| KR20080053597A (en) | Gate driving circuit and liquid crystal display using thereof | |
| CN108648703B (en) | Display panel and display device | |
| CN108538268B (en) | Bidirectional scanning grid driving circuit | |
| CN114974163B (en) | Scanning driving circuit, array substrate and display panel | |
| US11373569B2 (en) | Display driving circuit | |
| CN101447232B (en) | Shift buffer of pre-pull-down forward stage surge | |
| CN100405451C (en) | Liquid display device and signal transmitting system | |
| KR20080056781A (en) | Gate driving circuit and liquid crystal display using thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| TA01 | Transfer of patent application right | ||
| TA01 | Transfer of patent application right |
Effective date of registration: 20200826 Address after: No.7 Tianyou Road, Qixia District, Nanjing City, Jiangsu Province Applicant after: NANJING CEC PANDA LCD TECHNOLOGY Co.,Ltd. Address before: Nanjing Crystal Valley Road in Qixia District of Nanjing City Tianyou 210033 Jiangsu province No. 7 Applicant before: NANJING CEC PANDA FPD TECHNOLOGY Co.,Ltd. Applicant before: NANJING CEC PANDA LCD TECHNOLOGY Co.,Ltd. Applicant before: Nanjing East China Electronic Information Technology Co.,Ltd. |
|
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20191220 |