CN110582846B

CN110582846B - High power MMIC device with bypass gate transistor

Info

Publication number: CN110582846B
Application number: CN201880029743.8A
Authority: CN
Inventors: S·M·伍德; J·米里甘; M·弗洛尔斯; D·法雷尔; K·法耶德
Original assignee: Cree Inc
Current assignee: Wofu Semiconductor Co ltd
Priority date: 2017-05-05
Filing date: 2018-05-03
Publication date: 2023-05-12
Anticipated expiration: 2038-05-03
Also published as: EP3619738A4; JP2022002308A; JP7242777B2; EP3619738A1; WO2018204622A1; JP2020519025A; JP6929968B2; CN116403982A; JP2023081974A; CN110582846A

Abstract

A monolithic microwave integrated circuit is provided that includes a substrate having a transistor and at least one additional circuit formed thereon. The transistor includes a drain contact extending in a first direction, a source contact extending in the first direction parallel to the drain contact, a gate finger extending in the first direction between the source contact and the drain contact, and a gate jumper extending in the first direction. The gate jumper is conductively connected to the gate finger at two or more locations spaced apart from each other along the first direction.

Description

High power MMIC device with bypass gate transistor

Technical Field

The inventive concepts described herein relate to microelectronic devices and, more particularly, to high power, high frequency transistors having a unit cell based structure.

Background

In recent years, circuits that require high power processing capability while operating at high frequencies such as radio frequency (500 MHz), S-band (3 GHz), and X-band (10 GHz) have become increasingly popular. As high power, high frequency circuits increase, so does the need for transistors that can reliably operate at radio and microwave frequencies while still being able to handle higher power loads.

Transistors with larger gate periphery have been developed in order to provide increased output power. One technique for increasing the effective gate periphery of a transistor is to provide multiple transistor cells connected in parallel. For example, as shown in fig. 1, a high power transistor may include a plurality of gate fingers extending in parallel between respective elongated source and drain contacts.

In particular, fig. 1 shows a metal layout of a conventional transistor structure 10, the conventional transistor structure 10 including a gate pad 12, a source pad 22, and a drain pad 32 on a semiconductor structure 20. Fig. 1 is a plan view of the device (i.e., looking down the device from above). As shown in fig. 1, in a conventional transistor 10, a gate pad 12 is connected by a gate bus line 14 to a plurality of gate fingers 16 extending in parallel in a first direction (e.g., the y-direction shown in fig. 1). The source pad 22 is connected to a plurality of parallel source contacts 26 via a source bus 24, and the drain pad 32 is connected to a plurality of drain contacts 36 via a drain bus 34. Each gate finger 16 extends along the y-direction between a pair of adjacent source and

drain contacts

26, 36. A unit cell of the transistor 10 is shown at block 40 and includes a gate finger 16 extending between adjacent source and

drain contacts

26, 36. The "gate width" refers to the distance that the source and

drain contacts

26, 36 overlap in the y-direction. That is, the "width" of the gate finger 16 refers to the size (distance along the y-direction) of the gate finger 16 extending parallel to the adjacent source/

drain contacts

26, 36. The gate periphery of the device refers to the sum of the gate widths of each gate finger 16 of device 10.

In addition to adding unit cells, the gate periphery of the multi-cell transistor device may be increased by making the gate fingers wider (i.e., longer in the y-direction). However, as the gate fingers of the device become wider, the high frequency performance of the device may be adversely affected. In addition, widening the gate fingers generally means that the gate fingers must handle increased current densities, which may lead to electromigration of the gate finger metallization.

Disclosure of Invention

A transistor device according to some embodiments includes a source contact extending in a first direction, a gate finger extending in the first direction adjacent to the source contact, and a drain contact adjacent to the gate finger. The gate is between the drain contact and the source contact. The gate pads are electrically connected to the gate fingers at a plurality of points along the gate fingers.

The device further includes a gate jumper extending in the first direction and conductively connected to the gate pad. The gate pad is conductively connected to at least one of a plurality of points along the gate finger by a gate jumper.

The device may further include: a gate bus connected to the gate jumper and the gate finger; and a gate signal distribution bar spaced apart from the gate bus line in a first direction and connecting the gate jumper to the gate finger.

A transistor device according to a further embodiment comprises: a gate pad; a gate finger in conductive contact with the gate pad at a first location on the gate finger and extending in a first direction; and a gate jumper in conductive contact with the gate pad and extending in the first direction. The gate jumper is conductively connected to the gate finger at a second location on the gate finger spaced apart from the first location such that the gate signal received at the gate pad is applied to the gate finger at the first location and the second location.

A transistor device according to a further embodiment includes a gate bus line, a gate finger in contact with the gate bus line and extending in a first direction, and a gate jumper in contact with the gate bus line and extending in the first direction, wherein the gate jumper is in electrical contact with the gate guide at a location along the gate finger spaced apart from the gate bus line in the first direction.

A transistor device according to a further embodiment includes a substrate, a gate bus line on the substrate, and first and second source contact segments on the substrate and extending in a first direction. The first and second source contact segments are spaced apart from each other by a gap in a first direction. The device further includes a gate finger on the substrate and connected to the gate bus. The gate finger extends adjacent to the source contact segment in a first direction. The device further comprises: a drain contact on the substrate adjacent to the gate finger, wherein the gate finger is between the drain contact and the source contact segment; a gate jumper connected to the gate bus, wherein the gate jumper is provided over the source contact section and extends in a first direction; and a gate signal distribution strip on the substrate and extending from the gap between the first and second source contact segments to the gate finger. The gate signal distribution bars contact the gate fingers at gate signal distribution points spaced apart from the gate bus lines in a first direction, and the gate signal distribution bars are conductively connected to the gate jumper lines.

A transistor according to a further embodiment includes: a drain contact extending along a first axis; a source contact extending along a second axis parallel to the first axis; a gate finger extending between the source contact and the drain contact; and a plurality of spaced apart gate resistors electrically connected to the gate fingers. At least the first gate resistor is disposed in a portion of the region between the first axis and the second axis, the portion being between the first end and the second end of the gate finger when the transistor is viewed from above.

In some embodiments, the gate finger may include a plurality of discrete, collinear gate finger segments electrically connected to one another. The transistor may further include a gate jumper electrically connected between the gate bus and the first gate finger segment. The first gate resistor may be inserted along an electrical path between the gate jumper and the first gate finger segment. The transistor may further include a first gate signal distribution bar interposed along an electrical path between the gate jumper and the first gate finger segment. The first gate resistor may be interposed along an electrical path between the first gate signal distribution strip and the first gate finger segment. Each gate finger segment may be part of a respective gate split, and the transistor may further include an odd mode resistor (odd mode resistor) positioned between two adjacent gate splits.

In some embodiments, the source contact includes a plurality of collinear, discontinuous source contact segments, and the gate jumper extends over the source contact. The first gate signal distribution strip may extend in a gap between two adjacent source contact segments. An odd mode resistor may be interposed between the first gate signal distribution bar and a second gate signal distribution bar collinear with the first gate signal distribution bar. Further, the transistor may include a second source contact including a plurality of collinear, discontinuous source contact segments without gate jumpers extending thereon, and an odd mode resistor may be between two adjacent ones of the source contact segments of the second source contact.

A transistor according to yet a further embodiment includes a source contact extending in a first direction, a gate jumper extending in the first direction, and a gate finger including a plurality of discontinuous gate finger segments that may be collinear with each other. The transistor further includes a plurality of spaced apart gate resistors electrically connected to the gate jumper. The first gate finger segment is connected to a gate jumper through a first gate resistor.

In some embodiments, the source contact includes a plurality of discontinuous source contact segments, and the first gate resistor is in a gap between two adjacent source contact segments. The gate jumper may extend over at least some of the source contact segments. The transistor may further include: a drain contact extending adjacent to the gate finger in a first direction such that the gate finger extends between the source contact and the drain contact; a second gate finger comprising a plurality of discontinuous and collinear gate finger segments extending in a first direction such that a drain contact extends between the gate finger and the second gate finger; and a second source contact comprising a plurality of discontinuous source contact segments extending adjacent to the second gate finger in the first direction. An odd mode resistor may be provided in a gap between two adjacent ones of the source contact segments of the second source contact.

The gate signal distribution bars may extend between the gate jumper and the first gate finger segment of the first gate finger and between the gate jumper and the first gate finger segment of the second gate finger. The gate signal distribution bar may be located in a gap between two adjacent ones of the source contact segments of the source contact. The odd mode resistor may be connected between a gate signal distribution bar and a second gate signal distribution bar connecting gate finger segments of the plurality of additional gate fingers to a second gate jumper.

A transistor according to a further embodiment includes a plurality of gate fingers extending in a first direction and spaced apart from each other in a second direction perpendicular to the first direction. Each gate finger includes at least first and second spaced apart and substantially co-linear gate finger segments, wherein the first gate finger segment is separated from the second gate finger segment in a first direction by a gap region extending in a second direction. The resistor is disposed in the gap region.

In some embodiments, the transistor further comprises: a plurality of source contacts extending in a first direction, each source contact comprising a plurality of discrete source contact segments, and each source contact extending between gate fingers of a respective pair of gate fingers; and a plurality of drain contacts extending in the first direction, each drain contact extending between a respective pair of gate fingers. The gate bus may be electrically connected to the gate fingers, and the gate jumper may be electrically connected to the gate bus, wherein the gate jumper is interposed along an electrical path between at least some of the gate finger segments and the gate bus.

In some embodiments, the resistor may be an odd mode resistor positioned between two adjacent ones of the source contact segments of one of the source contacts. In other embodiments, the resistor may be a gate resistor interposed along an electrical path between the gate jumper and the first gate finger segment of the first gate finger. In these embodiments, the gate resistor may be inserted along a first gate signal distribution bar that extends between the gate jumper and the first gate finger segment of the first gate finger.

According to a further embodiment of the present invention, a monolithic microwave integrated circuit is provided that includes a substrate having a transistor and at least one additional circuit formed thereon. The transistor includes a drain contact extending in a first direction, a source contact extending in the first direction parallel to the drain contact, a gate finger extending in the first direction between the source contact and the drain contact, and a gate jumper extending in the first direction. The source contact is spaced apart from the drain contact in a second direction perpendicular to the first direction. The gate jumper is conductively connected to the gate finger at two or more locations spaced apart from each other along the first direction. The area of the cross section of the gate jumper in a plane extending in the second direction and perpendicular to the first direction is at least five times the area of the cross section of the gate finger in the plane. In some embodiments, the area of this cross section of the gate jumper may be ten times, twenty times, or even thirty times the area of the corresponding cross section of the gate finger.

In some embodiments, the at least one additional circuit may be an impedance matching circuit and the transistor may be a high electron mobility transistor.

In some embodiments, the gate finger includes a plurality of physically discontinuous gate finger segments that are electrically connected to one another by gate jumpers. The discontinuous gate finger segments may be collinear.

In some embodiments, the gate jumper may be located at a different level above the substrate than the gate finger.

In some embodiments, the source contact may include a plurality of discrete source contact segments electrically connected to each other. In such embodiments, the gate jumper may extend over at least one of the source contact segments and may be electrically insulated from the source contact. The gate jumper need not extend over all of the source contact segments.

In some embodiments, the monolithic microwave integrated circuit may be an amplifier. The amplifier may include at least one driver stage and an output stage, and the output stage may include at least one transistor.

In some embodiments, the gate jumper may vertically overlap at least one of the drain contact, the source contact, and/or the gate finger.

According to a further embodiment of the present invention, a monolithic microwave integrated circuit is provided that includes a substrate having a transistor and at least one additional circuit formed thereon. The at least one transistor includes a plurality of gate fingers extending in a first direction and spaced apart from each other in a second direction perpendicular to the first direction, each of the gate fingers including spaced apart and substantially collinear first and second gate finger segments electrically connected to each other, wherein the first gate finger segment is separated from the second gate finger segment in the first direction by a gap region extending in the second direction. The gate jumper may vertically overlap at least one of the drain contact, the source contact, and/or the gate finger.

In some embodiments, the transistor further comprises: a plurality of source contacts extending in a first direction, each source contact extending between a respective pair of gate fingers; and a plurality of drain contacts extending in the first direction, each drain contact extending between gate fingers of a respective pair of gate fingers. The monolithic microwave integrated circuit may further include: a gate bus electrically connected to the gate fingers; and a gate jumper electrically connected to the gate bus, wherein the gate jumper is interposed along an electrical path between the gate bus and at least one of the second gate finger segments. The area of the cross section of the gate jumper in a plane extending in the second direction and perpendicular to the first direction is at least five times the area of the cross section of the gate finger in the plane. In other embodiments, the area of this cross section of the gate jumper may be ten times, twenty times, or even thirty times the area of the corresponding cross section of the gate finger. The gate jumper may be at a different level above the substrate than the gate finger. The gate jumper may extend over at least a portion of the first source contact. In some embodiments, the first source contact may include a plurality of discontinuous source contact segments. In such embodiments, the gate jumper may not extend over the source contact segment that is furthest from the gate bus line from among the source contact segments.

In some embodiments, the at least one additional circuit may be an impedance matching circuit. The monolithic microwave integrated circuit includes an amplifier. The amplifier may comprise at least one driver stage and an output stage, wherein the output stage comprises a transistor.

In some embodiments, the transistor may be a high electron mobility transistor.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this application, illustrate certain embodiment(s) of the invention. In the drawings:

fig. 1 is a plan view of a metal layout of a conventional multi-cell transistor.

Fig. 2 is a plan view of a metal layout of a transistor according to some embodiments.

Fig. 3 is a partial isometric view of the transistor of fig. 2.

Fig. 4 is a partial cross-sectional view of the transistor of fig. 2 taken along line A-A' of fig. 2.

Fig. 5 is a plan view of a larger version of the transistor of fig. 2.

Fig. 6 is a detailed plan view of a small portion of the transistor of fig. 5.

Fig. 7A is a cross-sectional view of a unit cell of the transistor device taken along line B-B' of fig. 2.

Fig. 7B is a cross-sectional view of a unit cell of the transistor device taken along line C-C' of fig. 2.

Fig. 8 is a plan view of a metal layout of a transistor according to a further embodiment.

Fig. 9A is a partial cross-sectional view taken along line A-A' of fig. 8.

Fig. 9B is a partial cross-sectional view taken along line B-B' of fig. 8.

Fig. 10 is a plan view of a larger version of the transistor of fig. 8.

Fig. 11 is a detailed plan view of a small portion of the transistor of fig. 10.

Fig. 12 is a plan view of a metal layout of a transistor according to an additional embodiment.

Fig. 13 is a plan view of a metal layout of a transistor according to yet an additional embodiment.

Fig. 14 is a plan view of a metal layout of a transistor according to yet a further embodiment.

Fig. 15 is a plan view of a metal layout of a transistor according to an additional embodiment.

Fig. 16 is a schematic diagram of a conventional wafer with a plurality of MMIC devices formed thereon.

Fig. 17 is a plan view of a conventional two-stage MMIC amplifier.

Fig. 18A and 18B are schematic plan views of a conventional two-stage MMIC amplifier and an MMIC amplifier including a FET driver stage and a FET output stage each including a unit cell FET transistor having a segmented gate finger.

Fig. 19A and 19B are schematic diagrams comparing the relative sizes of the conventional two-stage MMIC amplifier of fig. 18A and the two-stage MMIC amplifier according to an embodiment of the invention.

Fig. 20A-20C are schematic diagrams of several example MMIC amplifiers according to further embodiments of the invention.

Fig. 20D is a schematic diagram of an MMIC switch according to a further embodiment of the invention.

Detailed Description

Embodiments of the inventive concept are described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the invention are shown. The inventive concept may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the inventive concept to those skilled in the art. Like numbers refer to like elements throughout.

Embodiments of the inventive concept provide a multi-cell transistor device having a large effective gate width. By feeding gate signals to the gate fingers at multiple locations along the width of the gate fingers, the high frequency gain performance of the transistor may be improved and the electromigration issues typically associated with wide gate fingers may be reduced. According to some embodiments, the larger gate width of the multi-cell transistor device may be accommodated by adding a second metal layer over the source region of the unit cell to act as a gate jumper. The gate jumpers connect to the gate fingers at a plurality of locations along the gate fingers, effectively dividing the gate fingers into a plurality of segments. The gate jumper may be provided by a second metal layer extending over and above the source contact. A gate jumper may be interposed between the gate pad and at least some of the gate finger segments and may electrically connect the gate pad to the gate finger segments. In some embodiments, the gate jumper may extend over and above the drain contact or gate finger, rather than over and above the source contact.

By effectively dividing the gate finger into multiple segments and distributing the gate signal to each gate finger segment by means of a gate jumper, the gain performance of the transistor can be improved and electromigration issues can be alleviated.

Accordingly, embodiments of the inventive concept provide a transistor layout defining a plurality of unit cells connected in series for each gate finger. Individually, each unit cell has a shorter effective gate width. However, when connected in series, the unit cell may increase the effective width of a single gate finger. The gate fingers of the serially connected unit cells are connected to the gate bus line by means of a second metal bridge extending over the source contacts of the unit cells. The metal bridge is connected between the source contacts to a connection bar that extends along the substrate surface between the source contacts and connects to the gate fingers.

Transistors having the layout as described herein may have higher frequency performance and higher output power while having reduced current density, which may improve device reliability.

In accordance with a further embodiment of the present invention, a multi-cell transistor having a large effective gate width is provided, wherein a plurality of series gate resistors (also referred to herein as "gate resistors") are distributed throughout the device. For example, a transistor may have segmented gate fingers, and a series gate resistor may be provided for each gate finger segment or pair of gate finger segments. This approach breaks the long feedback loop in the gate finger and drain of the transistor structure by making the feedback loop sufficiently lossy to avoid high levels of instability. The distributed series gate resistor may be positioned, for example, in a gap region provided between gate finger segments of the gate fingers.

Thus, in some embodiments, a transistor is provided, the transistor comprising: a drain contact extending along a first axis; a source contact extending along a second axis parallel to the first axis; and a gate finger extending between the source contact and the drain contact. The gate finger may include a plurality of physically discontinuous, collinear gate finger segments electrically connected to one another by one or more other structures (e.g., gate jumpers). The transistor further includes a plurality of spaced apart gate resistors electrically connected to the gate fingers. At least one gate resistor is disposed in a portion of the region between the first axis and the second axis, the portion being between the first end and the second end of the gate finger when the transistor is viewed from above. In some embodiments, a gate jumper may be electrically connected to the gate finger, and the gate jumper may be electrically connected to the gate bus. A gate jumper may be inserted along an electrical path between the first gate finger segment and the gate bus, and a first gate resistor may be inserted along an electrical path between the gate jumper and the first gate finger segment.

In other embodiments, a transistor is provided that includes a source contact extending in a first direction, a gate jumper extending in the first direction, and a gate finger including a plurality of discontinuous gate finger segments extending in the first direction. The transistor further includes a plurality of spaced apart gate resistors, each gate resistor electrically connected to a gate jumper. A first one of the gate finger segments is connected to a gate jumper through a first gate resistor.

In accordance with yet a further embodiment of the present invention, a multi-cell transistor having a large effective gate width is provided wherein a plurality of odd mode resistors are distributed throughout the device. In an example embodiment, an odd mode resistor may be provided in a gap region formed between "gate splits," where a gate split refers to a region where a plurality of gate finger segments extend parallel to each other. Odd mode resistors may be allocated in these gap regions to further improve the stability of the transistor. The gate resistors described above may also be located in these gap regions.

Thus, in an additional embodiment, a transistor is provided that includes a plurality of gate fingers extending in a first direction and spaced apart from each other in a second direction perpendicular to the first direction, each gate finger including at least first and second spaced apart substantially collinear gate finger segments electrically connected to each other, wherein the first gate finger segment is separated from the second gate finger segment in the first direction by a gap region extending in the second direction. At least one resistor is disposed in the gap region. The at least one resistor may be an odd mode resistor and/or a series gate resistor.

Transistors according to embodiments of the inventive concept may have a large effective gate width, support increased power density levels, and exhibit improved frequency response compared to conventional transistors. Additionally, the gate series resistor and odd mode resistor (if provided) may help prevent a feedback loop that may generate unwanted signals at frequencies low enough to be close to or within the operating frequency range of the transistor. Thus, the transistor may also exhibit increased stability and may thus have improved yield and/or better reliability.

It will be appreciated that the above embodiments may be combined in any manner. For example, a transistor may be provided that includes both a distributed gate resistor and a distributed odd mode resistor. Likewise, a transistor with an unsegmented gate finger may include one or both of a distributed gate resistor and a distributed odd mode resistor.

According to yet further embodiments of the present invention, FET-based MMIC devices are provided that use one or more pass gate transistors. For example, MMIC amplifiers are provided that use bypass gate transistors in one or more stages of the amplifier. In an example embodiment, an MMIC amplifier may include an input impedance matching network, a FET driver stage, an interstage impedance matching network, a FET output stage, and an output impedance matching network. At least the FET output stage may include a bypass gate transistor. Since the gate width of the gate bypass transistor may be increased compared to conventional FET transistors, the MMIC amplifier may have a FET output stage that is physically larger and thus has increased power handling capabilities.

Example embodiments of bypass gate transistors according to embodiments of the present invention will now be described in more detail with reference to fig. 2-15.

Fig. 2 is a plan view of a metal layout of transistor 100 according to some embodiments. The transistor is formed on a semiconductor structure 120, the semiconductor structure 120 including one or more device epitaxial layers, which will be described in detail below. The layout of fig. 2 is simplified for ease of understanding and includes gate pad 112 connected to gate bus 114 and drain pad 132 connected to drain bus 134. The source pads and source bus lines are omitted from fig. 2 for clarity of illustration, but are shown in fig. 5 and 6.

A plurality of gate fingers 116 are connected to gate bus 114 and extend in the y-direction. Likewise, a plurality of drain contacts 136 are connected to the drain bus 134 and extend parallel and adjacent to the respective gate fingers 116. Although only four gate fingers 116 and three drain contacts 136 are shown in fig. 2, it should be appreciated that transistor 100 may have more gate fingers 116 and drain contacts 136 so that the transistor has a large number of unit cells.

A source contact 162 is also provided, and the source contact 162 extends parallel to the adjacent gate finger 116 in the y-direction. The source contact 162 is divided into respective

source contact segments

162a, 162b, and 162c in the y-direction. The source contact segments may be connected by means of source contact strips extending laterally across the device structure (in the x-direction). The

source contact segments

162a, 162b, 162c may also be connected by other means. For example, a source contact plug may be provided that electrically connects each

source contact segment

162a, 162b, 162c to a common conductive layer located, for example, in a lower level of the device.

Adjacent ones of the source contact segments 162a-162c are separated by a gap 162 g. Although FIG. 2 shows three source contact segments 162a-162c for each source contact 162, the inventive concepts are not limited to this configuration and it will be appreciated that the source contact 162 may include two or more source contact segments 162a-162c.

The gate finger 116 may extend parallel to the source contact 162 over the entire length of the source contact 162. However, since the source contact 162 is divided into source contact segments 162a-162c, the

source contact segments

162a, 162b, and 162c define a plurality of

series unit cells

40a, 40b, 40c for each gate finger 116. That is, each gate finger 116 serves as a gate contact for a plurality of

unit cells

40a, 40b, 40c, the plurality of

unit cells

40a, 40b, 40c being arranged in a direction (y-direction) along which the gate finger 116 extends and defining a width of the gate finger 116. Thus, the total width that each gate finger 116 contributes to the gate periphery of the entire device is equal to the distance that the gate finger 116 overlaps adjacent

source contact segments

162a, 162b, and 162c in the y-direction.

The transistor 100 further includes a plurality of gate jumpers 172, the gate jumpers 172 extending parallel to the gate fingers 116 along the y-direction. The gate jumper 172 may be formed over the source contact 162 and may be insulated from the source contact 162 by, for example, a dielectric layer and/or an air gap. Thus, each gate jumper 172 may "vertically overlap" a respective one of the source contacts 162, meaning that an axis perpendicular to the major surface of the substrate extends through at least one of each gate jumper 172 and source contact 162. In other embodiments, each gate jumper 172 may additionally and/or alternatively vertically overlap a respective drain contact 126 and/or a respective gate finger 116, as will be discussed in further detail below. A gate jumper 172 is electrically connected to the gate bus 114 and connects each gate finger 116 to the gate bus 114 at a plurality of locations along the gate finger 116.

In particular, gate jumpers 172 are connected to gate fingers 116 by gate signal distribution bars 174, the gate signal distribution bars 174 being provided at a plurality of locations along the width of the device and extending laterally (in the x-direction) within gaps 162g between adjacent source contact segments of

source contact segments

162a, 162b, and 162 c. Gate signal distribution bars 174 contact gate fingers 116 at respective gate signal distribution points 176. Accordingly, electrical signals ("gate signals") applied to the gate pads 112 are transferred to the gate bus 114 and then to the gate jumpers 172, the gate jumpers 172 distributing the gate signals to the gate fingers 116 at a plurality of locations along the width of the gate fingers 116 (gate signal distribution points 176). One end of each gate finger 116 may also be directly connected to the gate bus 114, as shown in fig. 2. Thus, in the embodiment of fig. 2, rather than having gate fingers 116 carry gate signals for the entire width of the device, gate signals may travel from gate bus 114 onto each gate finger 116 and may also be carried by gate jumpers 172 over a majority of the width of the device and then distributed to gate fingers 116 at multiple locations along the width of the device.

The gate jumpers 172 may have a larger cross-sectional area than the gate fingers 116 and thus may handle higher current densities better than the gate fingers 116 without the problems typically associated with gate width increases such as electromigration and degradation of high frequency gain performance. For example, in some embodiments, the area of the cross-section of the gate jumper 172 in a first plane (i.e., a plane extending in the x-axis direction and perpendicular to the y-axis direction) is at least five times the area of the cross-section of the gate finger 116 in the first plane, the first plane extending in the x-axis and z-axis directions. In other embodiments, the area of this cross-section of the gate jumper 172 in the first plane may be ten times, twenty times, or even thirty times the area of the corresponding cross-section of the gate finger 116 in the first plane. It will be appreciated that by extending the gate jumpers 172 farther in the x-axis direction and/or the z-axis direction than the gate fingers 116, the gate jumpers 172 can be designed to have such an increased cross-sectional area as compared to the cross-sectional area of the gate fingers 116. In some embodiments, it may be most convenient to design the gate jumper 172 to extend farther than the gate finger 116 in both the x-axis direction and/or the z-axis direction. For example, in some embodiments, the length of the gate jumper 172 in the x-axis direction may be at least twice the length of its corresponding gate finger 116 in the x-axis direction. In other embodiments, the length of the gate jumper 172 in the x-axis direction may be at least three times the length of its corresponding gate finger 116 in the x-axis direction. In still other embodiments, the length of the gate jumper 172 in the x-axis direction may be at least five times the length of its corresponding gate finger 116 in the x-axis direction. Fig. 7A, discussed below, illustrates how the area of the cross section of the gate jumper 172 in the first plane may be greater than the area of the cross section of the gate finger 116 in the first plane. In fig. 7A, the cross-sectional area of the gate jumper 172 may be five times the cross-sectional area of the gate finger 116. As noted above, in other embodiments, this difference in cross-sectional area may be greater (e.g., by a factor of 10, 20, 30, or even 50). The gate jumpers in all embodiments disclosed herein may have these expanded cross-sectional areas relative to their respective gate fingers.

Fig. 3 is a partial isometric view of the metal layout of transistor 100, and fig. 4 is a partial cross-sectional view taken along line A-A' of fig. 2. As can be seen in fig. 3 and 4, the gate jumper 172 is formed at a metal level that is higher than the metal levels of the

source contact segments

162a, 162b, 162c, the gate finger 116, the gate bus 114, and the gate signal distribution bar 174. The gate jumper 172 is connected to the gate bus 114 and the gate signal distribution bar 174 by a vertical contact plug 178.

The gate jumper 172, the gate bus 114, the vertical contact plug 178, and the gate signal distribution bar 174 may be formed of a conductive material such as copper or aluminum having a very low resistance.

Fig. 5 is a plan view of a larger version of transistor 100, and fig. 6 is a detailed plan view of a small portion 150 (i.e., the portion within the dashed box in fig. 5) of the metal layout of fig. 5. The transistor 100 includes a plurality of unit cells 40 extending vertically (in the y-direction). Each unit cell 40 includes one gate finger 116 extending over the entire width of the device, and is subdivided into

serial unit cells

40a, 40b, 40c arranged in the vertical direction (y-direction) as described above. In the embodiment shown in fig. 5 and 6, the total width of each unit cell 40 is 1120 microns, with the widths of the

serial unit cells

40a, 40b, and 40c being 370 microns, 380 microns, and 370 microns, respectively, although the inventive concept is not limited to these particular sizes. In this way, the effective gate width of the device may be increased.

Referring to fig. 6, a gate pad 112 and a gate bus 114 are provided at one end of the structure, and a drain pad 132 and a drain bus 134 are provided at the other end of the structure. Source pads 122 are provided on the sides of the structure and are connected to source bus lines 124. The source bus 124 is connected to a plurality of source contact strips that extend in the lateral direction (x-direction) to contact the

source contact segments

162a, 162b, 162 c. As described above, the

source contact segments

162a, 162b, 162c may be electrically connected in other ways, such as through the use of source contact plugs that electrically connect each

source contact segment

162a, 162b, 162c to a common conductive layer.

The detailed view of the portion 150 of the device layout of the transistor 100 in fig. 6 also shows the gate finger 116, the gate jumper 172, the gate signal distribution bar 174, and the gate signal distribution point 176, with the gate signal distribution bar 174 contacting the gate finger 116 at the gate signal distribution point 176.

Fig. 7A is a cross-sectional view of unit cell 40 of transistor device 100 taken along line B-B' of fig. 2. Fig. 7B is a cross-sectional view of the unit cell 40 taken along line C-C' of fig. 2. As shown in fig. 7A-7B, the transistor structure 100 includes a semiconductor structure 120, the semiconductor structure 120 including a substrate 200, which substrate 200 may include, for example, 4H-SiC or 6H-SiC. A channel layer 210 is formed on the substrate 200, and a barrier layer 220 is formed on the channel layer 210. The channel layer 210 and the barrier layer 220 may include a group III nitride based material, the material of the barrier layer 220 having a higher bandgap than the material of the channel layer 210. For example, the channel layer 210 may include GaN, and the barrier layer 220 may include AlGaN.

Due to the difference in band gap between the barrier layer 220 and the channel layer 210 and the piezoelectric effect at the interface between the barrier layer 220 and the channel layer 210, a two-dimensional electron gas (2 DEG) is induced in the channel layer 210 at the junction between the channel layer 210 and the barrier layer 220. The 2DEG acts as a highly conductive layer that allows conduction between the source and drain regions of the device under the source contact segment 162b and drain contact 136, respectively. Source contact segment 162b and drain contact 136 are formed on barrier layer 220. Gate finger 116 is formed on barrier 220 between drain contact 136 and source contact segment 162 b. A gate jumper 172 is provided over the source contact segment 162b and is connected to the gate finger 116 by a vertical contact plug 178 and a gate signal distribution strip 174. The vertical contact plugs 178 and gate signal distribution bars 174 are provided in the gaps 162g between adjacent ones of the source contact segments 162a-162c and do not physically contact the source contact segments 162a-162 c.

A first interlayer insulating layer 232 is formed over the drain contacts 136, the gate fingers 116, the source contact segments 162b, and the gate signal distribution bars 174. The interlayer insulating layer 232 may include a dielectric material such as SiN, siO ₂ Etc. The vertical contact plugs 178 penetrate the first interlayer insulating layer 232. The gate jumper 172 is formed on the first interlayer insulating layer 232 that insulates the gate jumper 172 from the source contact segment 162 b. The second interlayer insulating layer 234 may be formed on the first interlayer insulating layer 232 and the gate jumper 172. The second interlayer insulating layer 234 may include a dielectric material such as SiN, siO ₂ Etc.

The material of the gate finger 116 may be selected based on the composition of the barrier layer 220. However, in some embodiments, conventional materials capable of schottky contact with nitride-based semiconductor materials may be used, such as Ni, pt, niSi _x Cu, pd, cr, W and/or WSiN. The drain contact 136 and the source contact segment 162 may include a metal such as TiAlN that may form an ohmic contact to GaN.

Series gate resistors and odd mode resistors may be included in high power transistors according to embodiments of the invention to stabilize the feedback loop within the gate fingers and drain of the device. In high power devices, the gate may have a long gate width to increase the gate periphery of the device, which may result in a long feedback loop. Since these high power transistors have large transconductance values, the feedback loop may become unstable. In particular, the feedback loop may generate unwanted signals that may be within or outside the operating frequency band of the transistor. In either case, the generation of such signals can be problematic and can render the transistor unusable. The instability of the feedback loop tends to increase with the length of the feedback loop.

According to a further embodiment of the present invention, a high power transistor is provided comprising a plurality of series gate resistors and/or odd mode resistors distributed throughout the device and in particular along the long gate fingers. Distributed series gate resistors and/or odd mode resistors may be particularly advantageous in transistors having segmented gate fingers because such devices may include gap regions between "gate splits" that are natural locations for locating the series gate resistors and/or odd mode resistors along the width of the gate fingers. In this context, the term "gate split" refers to a shorter array of gate finger segments that results when a long gate finger is segmented into multiple gate finger segments, as discussed above with reference to fig. 2-7. The gap regions that exist between adjacent gate splits may be convenient locations for implementing distributed series gate resistors and odd mode resistors, as will be discussed in more detail below.

It has been found that by distributing the series gate resistors and/or odd mode resistors along the extended width of the gate fingers, the feedback loop can become sufficiently lossy to overcome potential instability. Thus, by distributing the series gate resistors and/or odd mode resistors along the extended width of the gate fingers, device yield may be increased and/or failure rates of field devices may be reduced. Further, relatively small resistance levels may be used when the series gate resistors and/or odd mode resistors are distributed along and among the gate finger segments of the segmented gate fingers. For example, if the transistor has three gate splits, the resistance level may be about one third of the size of the resistance level that would be used if the gate fingers were not segmented. Furthermore, it has been found in practice that the reduction in resistance is even greater. For example, when three gate splits are used, the resistance value of the series resistors included along each gate finger segment may be one-fourth to one-fifth of the resistance value of the series gate resistors implemented at the gate pad. The use of resistors with lower resistance values reduces losses, thus resulting in transistors with higher gain while also exhibiting increased stability.

Fig. 8 is a plan view (top view) of a metal layout of a transistor 300 according to a further embodiment that implements both a series gate resistor and an odd mode resistor in a distributed manner, as discussed above. Transistor 300 is formed on a semiconductor structure 320 that includes one or more device epitaxial layers. Semiconductor structure 320 may be the same as semiconductor structure 120 discussed above with reference to fig. 7A and 7B. As with the previous figures, the layout of fig. 8 is simplified for ease of understanding and includes a pair of gate pads 312 connected to a corresponding pair of gate buses 314 and a drain pad 332 connected to a drain bus 334. Source pad 322 and source bus are also included in transistor 300, but are omitted from fig. 8 for clarity of illustration. Source pad 322 is shown in fig. 10.

A plurality of gate fingers 316 are connected to each gate bus 314 and extend in the y-direction. Each gate finger 316 is divided into three

gate finger segments

316a, 316b, and 316c in the y-direction. The first gate finger segment may (but need not) be directly connected to the gate bus 314 without the gate jumper 372 interposed therebetween. A gate jumper may be interposed between the

gate finger segments

316b, 316c and the gate bus 314. As described below, the

gate finger segments

316a, 316b, 316c of each gate finger 316 may be electrically connected to each other via a gate jumper 372, a gate signal distribution bar 374, and a vertical contact plug 378 (fig. 9A). A plurality of drain contacts 336 are connected to drain bus 334 and extend parallel and adjacent to respective gate fingers 316. The gate signal distribution bar 374 may be formed at a different vertical level in the device than the gate distribution bar 174 of the transistor 100 to allow the gate signal distribution bar 374 to pass over the drain contact 336, as will be described below. A source contact 362 is also provided, and the source contact 362 extends parallel to the adjacent gate finger 316 in the y-direction. The source contact 362 is also divided into respective

source contact segments

362a, 362b, and 362c in the y-direction. The

source contact segments

362a, 362b, 362c may be electrically connected to each other via a source contact plug 364. Each source contact plug 364 may electrically connect a respective

source contact segment

362a, 362b, 362c to a common conductive layer that serves as a source bus. The source bus may be located, for example, in a lower layer of the device. In some embodiments, each

source contact segment

362a, 362b, 362c may provide more than one source contact plug 364. Two representative source contact plugs 364 are shown on one source contact segment 362c in fig. 8. To simplify the drawing, source contact plugs 364 for the other

source contact segments

362a, 362B, 362c are omitted from fig. 8 (and fig. 9A-9B and 12-13). Fig. 10 and 11 illustrate how a pair of source contact plugs 364 may be provided for each

source contact segment

362a, 362b, 362c, for example. The

source contact segments

362a, 362b, 362c may also be electrically connected by other means, such as source contact strips. In fig. 8, a total of sixteen segmented gate fingers 316, eight segmented source contacts 362, and eight drain contacts 336 are shown. However, it will be appreciated that transistor 300 may have more gate fingers 316, source contacts 362, and drain contacts 336, such that transistor 300 has a large number of unit cells. In other embodiments, fewer gate fingers 316, source contacts 362, and drain contacts 336 may be provided.

Adjacent ones of the gate finger segments 316a-316c are separated by a gap 316g, while adjacent ones of the source contact segments 362a-362c are separated by a gap 362 g. Although fig. 8 shows three gate finger segments 316a-316c and three source contact segments 362a-362c for each respective gate finger 316 and source contact 362, the inventive concept is not limited to this configuration. Thus, it will be appreciated that the gate finger 316 may include two or more gate finger segments, and the source contact 362 may include two or more source contact segments.

The gate finger 316 may extend parallel to the source contact 362 over the entire length of the source contact 362. Since the gate finger 316 and the source contact 362 are segmented, a plurality of

unit cells

340a, 340b, 340c are defined along each gate. That is, each gate finger segment 316a-316c acts as a gate contact for a

respective unit cell

340a, 340b, 340c, with these

unit cells

340a, 340b, 340c being aligned in the direction along which the gate finger 316 extends (y-direction). The sum of the widths of the gate finger segments 316a-316c defines the total width of each gate finger 316. Thus, the total width that each gate finger 316 contributes to the gate periphery of the entire device is equal to the sum of the widths of gate finger segments 316a-316c in the y-direction.

Transistor 300 further includes a plurality of gate jumpers 372 extending in the y-direction parallel to gate fingers 316. The gate jumper 372 may be formed at a metal level that is higher than the metal level of the source contact segment 362, the gate finger 316, and the gate bus 314. The gate jumper 372 may be formed over the source contact 362 and may be insulated from the source contact 362 by, for example, a dielectric layer and/or an air gap. The gate jumper 372 need not extend over the source contact segment 362c furthest from the gate bus 314. A gate jumper 372 is electrically connected to the gate bus 314. A gate jumper 372 may electrically connect some or all of the gate finger segments 316a-316c of each gate finger 316 to one of the gate bus lines 314. In the embodiment depicted in fig. 8, each gate jumper 372 electrically connects

gate finger segments

316b and 316c to gate bus 314, while gate finger segment 316a is connected to gate bus 314 via a more direct connection. In other embodiments, gate finger segment 316a may be connected to gate bus 314 by a gate jumper 372. In some embodiments, the gate jumper 372 may be positioned over the drain contact 336 or the gate finger 316, rather than over the source contact 362.

Fig. 9A is a partial cross-sectional view taken along line A-A' of fig. 8. Fig. 9B is a partial cross-sectional view taken along line B-B' of fig. 8. As can be seen in fig. 8 and 9A, a plurality of gate jumpers 372, gate signal distribution bars 374, and vertical contact plugs 378 are provided. The gate jumper 372 is connected to the gate bus 314 and the gate signal distribution bar 374 through a vertical contact plug 378. A gate jumper 372, a gate signal distribution bar 374, and a vertical contact plug 378 are used to connect each gate finger segment 316b-316c to one of the gate bus lines 314. The gate signal distribution strip 374 may be formed at a higher metal layer in the device than the gate finger 316. For example, the gate signal distribution bar 374 may be formed in the same metal layer of the device as the gate jumper 372, as shown in fig. 9A. The vertical contact plugs 378 may connect the gate jumpers 372 to the gate bus 314. Additional vertical contact plugs 378 (not visible in the cross-sectional view of fig. 9A, but located at the point where each gate signal distribution strip crosses gate resistor 380 in the plan view of fig. 8) may physically and electrically connect gate signal distribution strip 374 to the gate resistor and gate finger segments 316a-316c connected thereto. As described above, the gate jumper 372 may extend over and above the source contact 362. As can be seen in fig. 8, a gate jumper 372 is provided over every other source contact 362, in contrast to the transistor 100 in fig. 2-7 that includes a gate jumper 172 extending over each source contact 162. Thus, each gate jumper 372 in the transistor 300 of fig. 8-9B feeds four gate fingers 316, rather than two gate fingers 116 as in the case of the transistor 100. Gate signal distribution bars 374 are formed at a higher metal layer in the device than gate distribution bars 174 of transistor 100 to allow each gate signal distribution bar 374 to pass over two drain contacts 336 to connect to an outer one of the four gate finger segments 316a-316c.

The gate jumper 372, the gate bus 314, the vertical contact plug 378, and the gate signal distribution bar 374 may be formed of a conductive material having a very low resistance, such as copper or aluminum.

Still referring to fig. 8 and 9A, the gate signal distribution bar 374 extends laterally (in the x-direction) in the gap 362g between adjacent ones of the

source contact segments

362a, 362b, and 362 c. The gate signal distribution bar 374 coupled to the first gate finger segment 316a may be coupled to both gate finger segments 316a. Each gate signal distribution bar 374 coupled to the second or third

gate finger segment

316b, 316c may be coupled to four

gate finger segments

316b or 316c. As can be seen in fig. 8, each gate signal distribution bar 374 coupled to the first gate finger segment 316a may be connected to one of the gate bus lines 314 through a gate resistor 380. The gate signal distribution bars 374 connected to the gate finger segments 316a may be part of the same metal layer as the gate fingers 316 or part of the same metal layer as the gate jumpers 372, as these gate signal distribution bars 374 do not need to span the drain contacts 336. Each gate signal distribution bar 374 coupled to the second gate finger segment 316b or the third gate finger segment 316c may be connected to one of the gate bus lines 314 by one of the gate jumper lines 372 and may be connected to the

gate finger segments

316b, 316c by respective vertical contact plugs 378, as can be seen in fig. 8 and 9A. A series gate resistor 380 is provided on the electrical path between each

gate finger segment

316b, 316c and its associated gate signal distribution bar 374.

Still referring to fig. 8 and 9A, the distribution of electrical signals applied to the left-hand gate pad 312 of fig. 8 to the leftmost

gate finger segments

316a, 316b, 316c in fig. 8 will now be discussed. When a gate signal is applied to the gate pad 312, the gate signal is transferred to the left gate bus 314. The gate signal travels from the left gate bus 314 through the first gate signal distribution bar 374 and the first series gate resistor 380 to the first gate finger segment 316a. The gate signal also travels from the left gate bus 314 to the second gate signal distribution bar 374 through the first vertical contact plug 378 connecting the gate bus 314 to the gate jumper 372, and to the second vertical contact plug 378 through the second gate signal distribution bar 374, the second vertical contact plug 378 being connected to the leftmost second gate finger segment 316b through the second series gate resistor 380. Similarly, the gate signal travels from the left gate bus 314 to the gate jumper 372 through the first vertical contact plug 378, to the third gate signal distribution bar 374 through the gate jumper 372, and to the third vertical contact plug 378 through the third gate signal distribution bar 374, the third vertical contact plug 378 being connected to the leftmost third gate finger segment 316c through the third series gate resistor 380.

Thus, as shown in fig. 8 and 9A, the gate signal does not travel the entire width of any gate finger 316, but only along the width of the gate finger segment (e.g., gate finger segment 316 a) or along the width of the gate finger segment and a portion of the gate jumper 372 (e.g., gate finger segment 316 b) or along the width of the gate finger segment and the entire width of the gate jumper 372 (e.g., gate finger segment 316 c). As described above, the gate jumper 372 may have a larger cross-sectional area than the gate finger 316 and thus may handle higher current densities than the gate finger 316 without the problems typically associated with an increase in gate width, such as electromigration and a decrease in high frequency gain performance. The gate signal also travels along a portion of the gate signal distribution strip 374 and the vertical contact plugs 378. It should be noted, however, that fig. 8 is not drawn to scale and that the distance that the gate signal travels along any gate signal distribution strip 374 may be very small (e.g., less than 5%) as compared to the width of the gate finger segments in the y-direction, as can be seen in fig. 10-11. The distance traveled along the vertical contact plug 378 is also small. Thus, the distance traveled by the gate signal along the narrow conductive trace may be reduced.

As discussed above, transistor 300 includes a plurality of series gate resistors 380 distributed throughout the device. In particular, a series gate resistor 380 is provided at or near one end of each

gate finger segment

316a, 316b, 316 c. As shown in fig. 8, the gate finger 316 is divided into three "gate splits," namely a first gate split 382a comprising a gate finger segment 316a, a second gate split 382b comprising a gate finger segment 316b, and a third gate split 382c comprising a gate finger segment 316 c. A first gap region 384a is provided between the gate bus line 314 and the first gate split 382a, a second gap region 384b is provided between the gate split 382a and 382b, and a third gap region 384c is provided between the gate split 382b and 382c.

As shown in fig. 8, a series gate resistor 380 may be formed in the above-described gap regions 384a-384 c. The series gate resistor 380 may be formed, for example, by depositing a higher resistivity conductive material than the conductive material used to form the gate finger 316, the drain contact 336, the source contact 362, and the like. The series gate resistor 380 may be provided in any suitable vertical level of the transistor 300. In an example embodiment, the series gate resistor 380 may be formed at the same metallization level as the source contact 362, the drain contact 336, and the gate finger 316, as can be seen or inferred from fig. 8 and 9A. It will also be appreciated that the gate resistor 380 (or odd mode resistor 390 discussed below) may be replaced by other lossy elements that may serve a function equivalent to a resistor, such as a series inductor-capacitor circuit.

As will be discussed below with reference to fig. 12, a single series gate resistor 80 may be provided between each gate pad 312 and its associated gate bus 314, instead of a distributed series gate resistor 380 included in a transistor, in accordance with some embodiments of the present invention. When the series gate resistors are implemented as a single series gate resistor 80 between each gate pad 312 and its corresponding gate bus 314, each series gate resistor 80 may need to have a relatively high resistance value in order to reduce or prevent instability in the device. In transistor 300, a plurality of series gate resistors 380 are positioned between the gate splits 382 of the device. Each gate resistor 380 may have a much smaller resistance value than the gate resistor 80 that would be required if the gate resistor 80 were located only between the gate pad 312 and the gate bus 314.

In some embodiments, a series gate resistor 380 may be provided for each

gate finger segment

316a, 316b, 316c, while in other embodiments, some gate finger segments may share a series gate resistor 380. In the particular embodiment depicted in fig. 8, all

gate finger segments

316b, 316c have their own associated series gate resistors 380, while the paired gate finger segments 316a share a single series gate resistor 380. It will also be appreciated that in other embodiments, some of the gate finger segments 316a-316 may not have an associated gate resistor 380.

By distributing the series gate resistance at two or more locations along the gate finger 316, the feedback loop within the gate finger and the drain of the transistor can be made sufficiently lossy, such that instability can be reduced or eliminated. This may improve device yield and/or reduce the incidence of field device failure. Also, as described above and as can be seen in fig. 8, the current path along any particular

gate finger segment

316a, 316b, 316c may only pass through a single series gate resistor 380. Since the series gate resistor 380 may have a relatively small resistance value, power loss is reduced and the transistor 300 may therefore support higher gain levels for a given size device.

As can be seen in fig. 8, the transistor 300 includes a drain contact 336 extending in the y-direction along a first axis, a source contact 362 extending in the y-direction along a second axis parallel to the first axis, and a gate finger 316 extending between the source contact 362 and the drain contact 336. The gate finger 316 includes a plurality of discrete and collinear

gate finger segments

316a, 316b, 316c electrically connected to one another. Transistor 300 further includes a plurality of spaced apart gate resistors 380 electrically connected to gate fingers 316. Each gate resistor 380 may be coupled between a respective one of the

gate finger segments

316a, 316b, 316c and a respective one of the gate signal distribution bars 374. At least one of the gate resistors 380 is disposed between the first axis and the second axis. Gate jumpers 372 are inserted along the electrical path between the gate bus 314 and the gate finger 316. Gate jumpers 372 are inserted along respective electrical paths between

gate finger segments

316b and 316c and gate bus 314, and respective gate resistors 380 are inserted along respective electrical paths between gate jumpers 372 and

gate finger segments

316b, 316c.

As can also be seen in fig. 8, the transistor 300 includes a source contact 362 extending in the y-direction, a gate jumper 372 extending in the y-direction, and a gate finger 316, the gate finger 316 including a plurality of discrete and electrically connected

gate finger segments

316a, 316b, 316c. Transistor 300 further includes a plurality of spaced apart gate resistors 380.

Gate finger segments

316b and 316c are connected to gate jumper 372 through respective first and second gate resistors 380. The pair of gate finger segments 316a are connected to the gate bus 314 by respective gate resistors 380.

As further shown in fig. 8, an odd mode resistor 390 is also included in transistor 300. An odd mode resistor 390 is provided to disrupt the long odd mode instability feedback loop in the device. In particular, as the number of gate fingers 316 fed by gate jumper 372 increases, instability may occur. For example, a transistor may be stable when the gate jumper 372 feeds four gate fingers 316, but may begin to exhibit instability if eight gate fingers 316 are fed using the gate jumper 372. When instability occurs, it may be a function of the gate finger width and the operating frequency of the device. An odd mode resistor 390 may be interposed between adjacent gate signal distribution bars 374. When the transistor 300 is operating normally, the voltage on each side of each odd mode resistor 390 should be the same and therefore no current should flow between adjacent gate signal distribution bars 374.

An odd mode resistor 390 may be provided in the gap region 384 between adjacent gate splits 382. As shown in fig. 8 and 9B, the odd mode resistor 390 may be implemented at the same metallization level as the gate signal distribution bar 374 and the source contact 362, for example, and the odd mode resistor 390 may be directly connected between two adjacent gate distribution bars 374. An odd mode resistor 390 may also be interposed between adjacent gate buses 314.

Thus, the transistor 300 may include a plurality of gate fingers 316 extending in the y-direction and spaced apart from each other in the x-direction. Each gate finger 316 may include a plurality of spaced apart and substantially co-linear

gate finger segments

316a, 316b, 316c electrically connected to each other, wherein the

gate finger segments

316a, 316b, 316c are disposed in respective gate splits 382a, 382b, 382c separated by

gap regions

384b, 384 c. An odd mode resistor 390 is disposed in the

gap regions

384b, 384 c. In an example embodiment, an odd mode resistor 390 may be interposed between adjacent gate signal distribution bars 374.

It will also be appreciated that in some embodiments, the source contact 362 need not be segmented. In particular, both the gate resistor 380 and the odd mode resistor may be implemented in the same metal layer as the gate signal distribution bar 374 and the gate jumper 372. In such an embodiment, the source contact 362 need not be segmented. Thus, it will be appreciated that in other embodiments, the

resistors

380, 390 may be implemented directly above, or above and sideways of, the source contacts 362 in other embodiments, and that each source contact 362 may be a single continuous (i.e., non-segmented) source contact 362.

Although fig. 8 depicts a transistor 300 including a segmented gate finger 316 and a segmented source contact 362, it will be appreciated that embodiments of the invention are not so limited. For example, in other embodiments, the drain contacts 336 may be segmented in a similar manner such that each drain contact includes, for example, three separate segments. When the drain contacts 336 are segmented, they may be electrically connected to each other via, for example, a drain contact plug and another metallization layer in the device. In an embodiment, where the drain contact is segmented, the source contact 362 may or may not be segmented. Additionally, the gate finger 316 may be segmented as shown in fig. 8 or may not be segmented as shown in fig. 2 (and in fig. 14-15). Segmenting the drain contact may provide additional space for the gate resistor 380 and/or the odd mode resistor 390 in the region between the gate splits. As a simple example of such an embodiment with segmented drain contact 336, transistor 300 of fig. 8 may be modified such that

reference numerals

332, 334, and 336 are source pad, source bus, and source contact, respectively, and

reference numerals

362, 362a/362b/362c, and 364 are drain contact, drain contact segment, and drain plug, respectively. In other words, fig. 8 may also be viewed as an embodiment with segmented gate fingers 316 and segmented drain contacts 362 by simply reversing the source and drain features.

Fig. 10 is a plan view of a larger version of the transistor 300 of fig. 8. Fig. 11 is a detailed plan view of a small portion 302 of the transistor 300 of fig. 10.

Referring to fig. 10 and 11, the transistor 300 includes a plurality of unit cells extending vertically (in the y-direction). Each unit cell includes a gate finger 316 extending across the width of the device and is subdivided into series-connected

unit cells

340a, 340b, 340c arranged in the vertical direction (y-direction) as described above. In the embodiment shown in fig. 10-11, the total width of each unit cell 340 is 1120 microns, with the widths of the

serial unit cells

340a, 340b, and 340c being 370 microns, 380 microns, and 370 microns, respectively, although the inventive concept is not limited to these particular sizes.

A plurality of gate bus lines 314 are provided at one end of the structure and a drain bus line 334 is provided at the other end of the structure. Source pads 322 are provided on the sides of the structure and are connected to source busses, for example, on lower metallization layers (not shown) of the device. The

source contact segments

362a, 362b, 362c are connected to the source bus via contact plugs 364.

The detailed view of the portion 302 of the device layout of the transistor 300 in fig. 11 also shows the gate finger 316, the gate jumper 372, the gate signal distribution bar 374, the series gate resistor 380, and the odd mode resistor 390.

A transistor according to an embodiment of the inventive concept may include a semiconductor structure as a multi-layer structure. For example, as discussed above with reference to fig. 7A and 7B, the semiconductor structure 120 of the transistor 100 may include a substrate 200 (e.g., 4H-SiC or 6H-SiC), with the substrate 200 having formed thereon at least a channel layer 210 and a barrier layer 220. This also applies with respect to other transistors according to embodiments of the inventive concepts depicted herein. Thus, while it will be appreciated that the discussion of the semiconductor structure 120 in fig. 7A and 7B applies equally to the semiconductor structure of each of the other embodiments described herein, the metallization and other aspects of the device will vary based on the differences between the various embodiments depicted in the figures. Thus, for example, it will be appreciated that all of the transistors described herein may include a silicon carbide substrate and a group III nitride based channel and barrier layer, and that the semiconductor structures of these transistors may operate in the manner described with reference to fig. 7A and 7B.

Fig. 12 is a plan view of a metal layout of a transistor 400 according to a further embodiment of the inventive concept. Transistor 400 is similar to transistor 300 discussed above with reference to fig. 8-11, except that transistor 400 uses a series gate resistor 80 connected between each gate pad 312 and a corresponding gate bus 314 instead of the distributed series gate resistor 380 included in transistor 300. Since the two

transistors

300, 400 may be otherwise substantially identical except for this change, further discussion of the transistor 400 will be omitted.

Fig. 13 is a plan view of a metal layout of a transistor 500 according to yet a further embodiment of the inventive concept. Transistor 500 is also similar to transistor 300 discussed above with reference to fig. 8-11, except that transistor 500 uses a single odd mode resistor 90 between each pair of adjacent gate buses 314 and does not include distributed odd mode resistors 390 provided in the

gap regions

384b, 384c in transistor 300 of fig. 8. Since the two

transistors

300, 500 may be otherwise substantially identical except for this change, further discussion of the transistor 500 will be omitted.

It will be appreciated that the features of the above-described embodiments can be combined in any manner to create additional embodiments. For example, fig. 14 is a plan view of the metal layout of the same transistor 100' as the transistor 100 described above, except that it has been modified to include a series gate resistor 180 that may be the same as the series gate resistor 380 of fig. 8. As another example, fig. 15 is a plan view of a metal layout of a transistor 300' similar to transistor 300 described above, except that the gate finger 316 is no longer segmented and the location of the series gate resistor 380 is modified accordingly. It will be appreciated that figures 14 and 15 are provided to illustrate some of the possible combinations of different embodiments that lead to additional embodiments.

Embodiments of the inventive concept may be particularly suitable for use with group III nitride based High Electron Mobility Transistor (HEMT) devices. As used herein, the term "group III nitride" refers to those semiconductor compounds formed between nitrogen and elements of group III of the periodic table, typically aluminum (Al), gallium (Ga), and/or indium (In). The term also refers to ternary and quaternary compounds such as AlGaN and AlInGaN. These compounds are all of empirical formula in which one mole of nitrogen is combined with a total of one mole of group III elements.

Suitable structures of GaN-based HEMTs that can utilize embodiments of the present invention are described, for example, in the following patent documents: commonly assigned U.S. publication No.2002/0066908A1"Aluminum Gallium Nitride/Gallium Nitride High Electron Mobility Transistors Having A Gate Contact On A Gallium Nitride Based Cap Segment And Methods Of Fabricating Same," U.S. publication No.2002/0167023A1, "group-III Nitride Based High Electron Mobility Transistor (HEMT) With Barrier/Spacer Layer," U.S. publication No.2004/0061129, "Niride-Based Transistors And Methods Of Fabrication Thereof Using Non-Etched Contact Recesses," U.S. patent No.7,906,799 "Niride-Based Transistors With A Protective Layer And A Low-Damage Recesses," 15, 2011, and U.S. patent No.6,316,793, entitled "Nitride Based Transistors On Semi-Insulating Silicon Carbide Substrates," 11, 13, 2001, which are hereby incorporated by reference in their entirety.

In particular embodiments of the present invention, substrate 200 may be a semi-insulating silicon carbide (SiC) substrate, which may be, for example, 4H polytype of silicon carbide. Other silicon carbide candidate polytypes include the 3C, 6H and 15R polytypes.

An optional buffer layer, nucleation layer, and/or transition layer (not shown) may be provided on the substrate 200 below the channel layer 210. For example, an AlN buffer layer may be included to provide an appropriate crystal structure transition between the silicon carbide substrate and the rest of the device. Additionally, strain balanced transition layer(s) may also be provided as described, for example, in commonly assigned U.S. publication 2003/0102482A1 entitled "Strain Balanced Nitride Hetrojunction Transistors And Methods Of Fabricating Strain Balanced Nitride Heterojunction Transistors," published 5 th year 2003, the disclosure of which is incorporated herein by reference as if fully set forth herein. Further, one or more cap layers, such as SiN cap layers, may be provided on the barrier layer 220.

With sapphire (Al) ₂ O ₃ ) Silicon carbide is a very common substrate material for group III nitride devices because of its closer lattice match to group III nitride. The closer lattice match of SiC can result in a group III nitride film of higher quality than is commonly available on sapphire. Silicon carbide also has a very high thermal conductivity, and therefore the total output power of a group III nitride device on silicon carbide is generally not limited by the heat dissipation of the substrate, as compared to the case of the same device formed on sapphire. Also, the availability of semi-insulating silicon carbide substrates may provide device isolation and reduced parasitic capacitance. Suitable SiC substrates are manufactured by Cree, inc, e.g., the assignee of the present invention, durham, n.c.

Although silicon carbide may be used as the substrate material, embodiments of the present invention may utilize any suitable substrate, such as sapphire, aluminum nitride, aluminum gallium nitride, silicon, gaAs, LGO, znO, LAO, inP, and the like. In some embodiments, an appropriate buffer layer may also be formed.

In some embodiments of the invention, the channel layer 210 is a group III nitride, such as Al _x Ga _1-x N, where 0.ltoreq.x < 1, assuming that the energy of the conduction band edge of the channel layer 210 is less than the energy of the conduction band edge of the barrier layer 220 at the interface between the channel and the barrier layer. In some embodiments of the present invention, x=0 indicates that channel layer 210 is GaN. The channel layer 210 may also be other group III nitrides, such as InGaN, alInGaN, etc. Channel layer 210 may be undoped or unintentionally doped and may be grown to a temperature greater than about

Is a thickness of (c). The channel layer 210 may also be a multi-layer structure such as a superlattice or a combination of GaN, alGaN, and the like.

The channel layer 210 may have a bandgap smaller than that of the barrier layer 220, and the channel layer 210 may also have a greater electron affinity than the barrier layer 220. In certain embodiments of the inventive concept, the barrier layer 220 is AlN, alInN, alGaN or AlInGaN having a thickness between about 0.1nm and about 10 nm. In certain embodiments of the inventive concept, barrier layer 22 is sufficiently thick and has a sufficiently high Al composition and doping to cause significant carrier concentrations at the interface between channel layer 210 and barrier layer 220.

The barrier layer 220 may be a group III nitride and have a band gap greater than that of the channel layer 210 and an electron affinity less than that of the channel layer 210. Thus, in certain embodiments of the present invention, the barrier layer 220 may comprise AlGaN, alInGaN and/or AlN or a combination of layers thereof. The barrier layer 220 may be, for example, about 0.1nm to about 30nm thick. In certain embodiments of the present invention, barrier layer 220 is undoped or doped with an n-type dopant to less than about 10 ¹⁹ cm ^-3 Is a concentration of (3). In some embodiments of the invention, barrier layer 220 is Al _x Ga _1-x N, wherein 0 < x < 1. In a particular embodiment, the aluminum concentration is about 25%. However, the process is not limited to the above-described process,in other embodiments of the present invention, barrier layer 220 comprises AlGaN having an aluminum concentration between about 5% and about 100%. In a specific embodiment of the invention, the aluminum concentration is greater than about 10%.

Although example embodiments of bypass gate transistors according to embodiments of the present invention are shown with reference to GaN High Electron Mobility Transistor (HEMT) structures, the inventive concepts are not limited to such devices. Accordingly, embodiments of the present invention may include other transistor devices having a plurality of unit cells and control electrodes. Embodiments of the present invention may be adapted for use in any semiconductor device where a wider control electrode is desired and where there are multiple unit cells of the device. Thus, for example, embodiments of the invention may be adapted for use in various types of devices such as MESFET, MMIC, SIT, LDMOS, BJT, pHEMT, fabricated using SiC, gaN, gaAs, silicon, etc.

According to further embodiments of the inventive concept, monolithic Microwave Integrated Circuit (MMIC) devices are provided that can support significantly higher output power levels. These MMIC devices may also exhibit high output power densities for a given operating frequency. In some embodiments, MMIC devices may support the same output power level as comparable conventional MMIC devices, but do so in a significantly smaller package. MMIC devices according to embodiments of the present invention may exhibit enhanced performance, resulting in significant cost savings and/or improved reliability.

MMIC devices are used in a variety of applications including radar, cellular communications, satellite communications, electronic warfare applications, and the like. MMIC devices are high frequency devices (i.e., devices operating in the microwave frequency range extending from about 300MHz to about 300 GHz), and many applications in which MMIC devices are used must be able to support high output power levels. Currently, most MMIC devices are formed in high bandgap semiconductor material systems such as silicon carbide, gallium arsenide, and/or gallium nitride based semiconductor material systems. MMIC devices formed in these semiconductor material systems can generally operate at higher frequencies and support higher power density levels.

Many MMIC devices include Field Effect Transistors (FETs), such as Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) and High Electron Mobility Transistors (HEMTs). For example, high power RF amplifiers, low noise RF amplifiers, RF switches, RF limiters, RF mixers, and various other circuits may include one or more FETs. Typically, the MMIC devices described above will each have a unit cell structure in which a plurality of individual FET transistor cells are connected in parallel. The unit cell structure allows the MMIC device to support higher output power levels. The actual output power level that an MMIC device can support may be limited by several factors including the length of the "good gate region" that can be used to fabricate the output stage of the device, the operating frequency of the device, and the thermal environment in which the MMIC device operates.

The output power level supported by the FET-based MMIC device is based on the current carrying capability of the output stage of the MMIC device. The current carrying capacity of an output stage may be proportional to the physical size (area) of the output stage when viewed in plan. "good gate region" of a FET-based MMIC device refers to the portion of the device that forms the output stage of the FET.

Since the equipment used in the wafer level fabrication process may be capable of forming fine patterns in devices only in a limited area, good gate regions of MMIC devices may be constrained. In general, the main constraint on the size of a good gate region is in a direction perpendicular to the direction in which the gate fingers of the FET transistors in each unit cell extend. This direction, which corresponds to the x-axis direction in the subsequent fig. 16-20D, determines how many unit cell transistors may be included in the FET output stage (this direction is referred to herein as the "length" of the good gate region, and the y-axis direction is referred to as the "width" of the good gate region, since the width of the gate finger refers to the distance the gate finger extends in the y-axis direction, as described above with reference to fig. 1). Since the length of the good gate regions is typically much smaller than the diameter of the wafer on which the MMIC devices are formed, a large number of separate MMIC devices can be formed on the wafer. In many cases, conventional high power MMIC devices use the entire length of the good gate region to form the FET output stage, so expanding the good gate region requires the acquisition of processing equipment capable of forming fine patterns over a large area, to the extent that such equipment is even useful.

The physical size of the output stage, and thus the output power level supported by the output stage, may also be increased by increasing the width of the gate fingers in the output stage, as this increases the size of the output stage in the y-axis direction. However, since the resistance of each unit cell FET transistor is proportional to the width of its gate finger, and as the resistance increases, the power loss also increases, the width of the gate finger may be limited. Thus, the width of the gate fingers in the output stage can be effectively limited by the power loss of interest. The resistance is also a function of the microwave signal frequency (the frequency increase corresponds to the resistance increase), and therefore the microwave signal frequency (and other desired or required performance parameters) can effectively set the maximum width of the gate finger.

The thermal operating environment of an MMIC device also affects the maximum output power level that the device can support, as the thermal operating environment typically sets the minimum required spacing between gate fingers sufficient to avoid excessive mutual heating that may lead to reduced performance of the MMIC device. The thermal operating environment may depend on one or more parameters such as the type of MMIC device, the efficiency of the device, the mode of operation (e.g., pulsed or continuous wave operation of the MMIC amplifier), etc. Again, these parameters are typically determined by the intended application of the MMIC device and the specified performance parameters. In this way, the maximum supportable output level of various MMIC devices may be substantially determined by various constraints such as the length of good gate regions, the operating frequency of the devices, and the thermal operating environment of the devices. In many cases, if such MMIC devices can be manufactured, it is desirable that the MMIC devices be capable of supporting higher output power levels. As will be discussed in detail below, MMIC devices according to some embodiments of the invention may support significantly higher output power levels than comparable conventional MMIC devices. Example embodiments of such MMIC devices will now be discussed in more detail with reference to fig. 16-20D.

Fig. 16 is a schematic diagram of a conventional wafer 600 with a plurality of MMIC devices formed thereon. The wafer may comprise, for example, a silicon carbide or sapphire wafer having a plurality of gallium nitride-based layers (e.g., gaN, alGaN, etc.) and a metallization layer formed thereon. As shown in fig. 16, the wafer 600 is generally divided into a grid pattern 610, and MMIC devices 630 are formed in each "cell" 620 of the grid pattern 610 (only three MMIC devices 630 are shown in fig. 16 to simplify the drawing). The size of each cell 620 may be based on the available processing equipment. For example, in an example embodiment, the size of each cell 620 may be 10mm by 10mm square. In another example embodiment, the size of each cell 620 may be 6mm by 6mm. The cells 620 may have other sizes and need not be the same length and width. It will also be appreciated that only certain portions of the MMIC device need be contained within the unit 620. For example, in an MMIC amplifier, FET amplification stages may be included within the cell 620, but input and/or output impedance matching circuits may be formed outside of the cell 620, as these circuits may be formed without a fine pattern.

As described above, a limitation on the size of each cell 620, particularly a limitation on the length of each cell in the x-axis direction, may be used to limit the maximum output power that each MMIC device 630 may support. This can be seen with reference to fig. 17, which is a plan view of a conventional two-stage MMIC amplifier 700. The MMIC amplifier 700 shown in fig. 17 may be an MMIC device 630 in one or more of the cells 620 of the wafer 600 of fig. 16.

As shown in fig. 17, the MMIC amplifier 700 includes a FET driver stage 710 and a FET output stage 720, the FET driver stage 710 and the FET output stage 720 representing two amplification stages of the two-stage MMIC amplifier 700. MMIC amplifier 700 further includes input impedance matching circuit 730, inter-stage impedance matching circuit 740, and output impedance matching circuit 750. Input pads 760 and output pads 762 may also be provided as well as other pads 764 that provide power and ground connections for the MMIC device 700. As discussed above, the maximum supportable output power of the MMIC amplifier 700 will be based on the maximum current level supported by the FET output stage 720.

An input signal in the form of a microwave signal (e.g., an RF signal of 700 MHz) may be input to MMIC amplifier 700 at input pad 760. The input RF signal passes through an input stage impedance matching circuit 730, which input stage impedance matching circuit 730 matches the impedance at the input of the FET driver stage 710 to the impedance seen at the input pad 760. The FET driver stage 710 amplifies the RF signal input thereto to provide a higher power RF signal. The higher power RF signal output by FET driver stage 710 (after appropriate impedance matching by inter-stage impedance matching circuit 740) may be provided as an input signal to FET output stage 720. The FET output stage 720 amplifies the RF signal input thereto to further increase its power. The high power RF signal output by the FET output stage 720 passes through the output stage impedance match circuit 750 and is output from the MMIC device 700 at the output pad 762. The FET driver stage 710 may be implemented, for example, as a plurality of unit cell FET transistors 712 (e.g., HEMT transistors) electrically connected in parallel with each other. The FET output stage 720 may be similarly implemented, for example, as a plurality of unit cell FET transistors 712 (e.g., HEMT transistors) electrically connected in parallel with each other. As shown in fig. 17, the FET output stage 720 typically includes more unit cell FET transistors 712 than the FET driver stage 710 to improve the efficiency of the MMIC amplifier 700.

The input impedance matching circuit 730 may include, for example, one or more capacitors, inductors, resistors, and/or other circuit elements arranged to match the impedance of the RF signal input to the MMIC amplifier 700 at the input pad 760 to the impedance seen at the input of the FET driver stage 710. Similarly, the inter-stage impedance matching circuit 740 may include, for example, one or more capacitors, inductors, resistors, and/or other circuit elements arranged to match the impedance of the signal output from the FET driver stage 710 to the impedance seen at the input of the FET output stage 720. The output impedance matching circuit 750 may include, for example, one or more capacitors, inductors, resistors, and/or other circuit elements arranged to match the impedance of the signal output from the FET output stage 720 to the impedance seen at the output pad 762 of the MMIC amplifier 700.

As discussed above, the maximum output power level supported by an MMIC amplifier, such as the two-stage MMIC amplifier 700 of fig. 17, is a function of (1) the number of unit cell FET transistors 712 in the FET output stage 720 and (2) the power supported by each unit cell FET transistor 712 in the FET output stage 720. The number of unit cell FET transistors 712 in the FET output stage 720 may be determined by (1) the "length" of the good gate region (which is the length of the MMIC device 700 in the x-axis direction of fig. 17) and (2) the spacing between the gate fingers of adjacent unit cell FET transistors 712. As discussed above, the length of the good gate region is set by the size of the cell 620 (see fig. 16), which may be a function of the processing device, and the minimum gate finger pitch may be set based on thermal considerations which may be a function of the amplifier design criteria. Thus, the number of unit cell FET transistors 712 in FET output stage 720 may not easily increase above the limit set based on the size of cell 620 and amplifier design criteria.

The power supported by each unit cell FET transistor 712 of FET output stage 720 is a function of the gate finger width (i.e., the distance that the gate finger extends in the y-axis direction), with larger gate finger widths supporting increased output power levels. The length of each gate finger (i.e., the distance the gate finger extends in the x-axis direction) is typically made very small to enable each unit cell FET transistor 712 to switch at a high frequency. As a result, as the width of the gate fingers increases, the resistance of each gate finger also increases, resulting in increased power loss. At various microwave frequencies (e.g., 3 GHz), power loss considerations may limit the width of the gate fingers to, for example, about 500 microns. Thus, for a particular MMIC amplifier design, the above physical constraints and considerations may place practical limits on the maximum supported output power of the device.

As described above with reference to fig. 2-15, a multi-cell FET transistor with increased gate width may be provided in accordance with embodiments of the present invention. As described above, a larger gate width may be achieved by using segmented gate fingers and/or gate jumpers. These multi-cell transistors may be used in place of conventional multi-cell transistors in MMIC devices such as the two-stage MMIC amplifier described above to increase their maximum supportable output power.

For example, fig. 18A and 18B are schematic plan views of the conventional two-stage MMIC amplifier 700 and MMIC amplifier 800 of fig. 17, respectively, the MMIC amplifier 800 including FET driver and FET output stages each implemented using unit cell FET transistors with segmented gate fingers and/or gate jumpers. Fig. 18A and 18B are drawn on the same relative scale so that the dimensions of the respective regions of each MMIC amplifier and the overall dimensions of each MMIC amplifier can be visually compared.

As described above and schematically shown in fig. 18A, a conventional MMIC amplifier 700 has a FET driver stage 710 and a FET output stage 720, each having a unit cell FET transistor 712 with a gate finger width of 500 microns. The FET driver stage 710 and FET output stage 720 occupy a relatively small amount of device area, such as perhaps 20% to 30%. As shown in fig. 18B, an MMIC amplifier 800 according to an embodiment of the invention may have a FET driver stage 810, a FET output stage 820, an input impedance matching circuit 830, an inter-stage impedance matching circuit 840, and an output impedance matching circuit 850. The FET driver stage 810 and FET output stage 820 each have a unit cell FET transistor 812 with segmented gate fingers and/or gate jumpers according to embodiments of the invention. In the depicted MMIC amplifier 800, each unit cell FET transistor 812 has a gate finger that includes three 250 micron gate finger segments. Gate finger segments having a larger width (e.g., 400 microns each) may be used in other embodiments. Since the gate width of the gate finger of the unit cell FET transistor 812 is 50% greater than the unit cell FET transistor 712 included in the conventional MMIC amplifier 700, the maximum supportable output power of the MMIC amplifier 800 may be about 50% greater than the maximum supportable output power of the conventional MMIC amplifier 700. Thus, MMIC amplifiers (and other MMIC devices) according to embodiments of the invention may support output levels that are not achievable using conventional techniques.

Further, as can also be seen from fig. 18A and 18B, MMIC amplifiers and other devices according to embodiments of the invention can achieve these enhanced output power levels without scaling up the size of the device. In particular, although the size of the impedance matching circuit generally increases with increasing output power levels, the increase need not be proportional to the increase in maximum supported output power levels. Thus, as can be seen in the schematic diagrams of fig. 18A and 18B, the area of the MMIC amplifier 800 supporting a 50% higher output power level according to an embodiment of the invention may only be increased by, for example, 20%.

Fig. 19A and 19B provide another comparative example showing how an MMIC device according to an embodiment of the invention may provide enhanced performance while having a smaller physical footprint compared to conventional MMIC devices. In particular, fig. 19A is a schematic diagram of the conventional two-stage MMIC amplifier 700 of fig. 18A. Fig. 19B is a schematic diagram of a two-stage MMIC amplifier 900 according to an embodiment of the invention, the amplifier 900 supporting a higher output power level while occupying a smaller area than the MMIC device 700. Fig. 19A and 19B are drawn on the same relative scale so that the dimensions of the respective regions of each MMIC amplifier and the overall dimensions of each MMIC amplifier can be visually compared.

As shown in fig. 19B, the MMIC amplifier 900 includes FET driver stage 910 and FET output stage 920, the FET driver stage 910 and FET output stage 920 each having a unit cell FET transistor 912 with segmented gate fingers and/or gate jumpers according to embodiments of the invention. The MMIC amplifier 900 further includes an input impedance matching circuit 930, an interstage impedance matching circuit 940, and an output impedance matching circuit 950. In MMIC amplifier 900, the gate fingers of each unit cell FET transistor 912 include three 250 micron gate finger segments that are 50% greater than the width of the gate fingers in unit cell FET transistor 712 included in conventional MMIC amplifier 700. However, the MMIC amplifier 900 extends about 25% less in the x-direction than the MMIC amplifier 700. Thus, the maximum supportable output power of the MMIC amplifier 900 may be about 25% greater than the maximum supportable output power of the conventional MMIC amplifier 700, and the output power is implemented by an MMIC amplifier that is about 25% less than the MMIC amplifier 700.

The increased performance exhibited by the MMIC amplifier 900 of fig. 19B may be achieved by using unit cell FET transistors 912 with segmented (or "bypass") gate fingers and/or gate jumpers to form FET driver and

output stages

910, 920. The use of such a bypass gate FET transistor increases the size of each unit cell 912, which may increase the output power per unit cell by, for example, 50%. Thus, as shown in fig. 19A and 19B, the MMIC amplifier 900 may be smaller than the MMIC amplifier 700 while still supporting higher output currents and power levels. Although the MMIC amplifier 900 is smaller in size, it can support a higher output power level because the physical area of the FET output stage 920 may be larger than the physical area of the FET output stage 720 of the MMIC amplifier 700 due to the longer gate width of the FET transistor 912 included in the FET output stage 920 of the MMIC amplifier 900.

Since the processing of many MMIC devices is performed at the wafer level, the cost of an MMIC device may be proportional to the size of the device, because the more MMIC devices contained on a wafer, the lower the cost per MMIC device. Thus, MMIC devices according to embodiments of the present invention may have significant cost advantages over conventional MMIC devices while providing comparable or even improved performance. The smaller device size (for a given supported output power level) may also be advantageous in terms of system integration in various applications where a large number of MMIC devices are used in devices with a relatively small system footprint, such as phased array radar systems and massive MIMO beamforming antenna arrays. As more and more applications shift to higher microwave frequencies (such as the 28GHz and 80GHz bands), each individual radiating element becomes very small, which will become more and more true.

It will be appreciated that FET transistors according to embodiments of the invention with increased gate finger width may be used in a variety of MMIC devices, not just in a two-stage MMIC amplifier. For example, fig. 20A-20D illustrate several example MMIC devices according to further embodiments of the invention. As shown in fig. 20A, a single stage MMIC amplifier 1000 using multi-cell FET transistors with segmented gate fingers and/or gate jumpers according to embodiments of the invention may be provided. The example single stage MMIC amplifier 1000 shown in fig. 20A includes an input impedance matching stage 1030, a FET amplification/output stage 1020 including a pass gate transistor according to an embodiment of the invention, and an output impedance matching stage 1050.

As shown in fig. 20B, an MMIC amplifier having more than two stages may also be provided. In particular, the MMIC amplifier 1100 of fig. 20B includes a total of four amplification stages, namely first to third FET driver stages 1110, 1114, 1116 and a FET output stage 1120. The MMIC amplifier 1100 further includes an input impedance matching circuit 1130, an output impedance matching circuit 1150, and first to third inter-stage

impedance matching circuits

1140, 1142, 1144. It will be appreciated that in other embodiments (not shown) a three stage MMIC amplifier or an MMIC amplifier with five or more amplification stages may be provided. One or more of the first through third FET driver stages 1110, 1114, 1116 and FET output stage 1120 may include a bypass gate transistor according to an embodiment of the present invention.

It will also be appreciated that not all FET transistors included in MMIC devices according to embodiments of the invention need to use the bypass gate transistor designs disclosed herein. For example, fig. 20C is a schematic plan view of an MMIC amplifier 1200 according to an embodiment of the invention, the MMIC amplifier 1200 having a FET output stage 1220 formed using a bypass gate unit cell FET transistor 1222 according to an embodiment of the invention and a FET driver stage 1210 formed using a conventional FET transistor 1212. Because the good gate length is sufficient to allow a sufficient number of conventional unit cell FET transistors 1212, conventional FET transistors 1212 may be used in FET driver stage 1210. The MMIC amplifier 1200 further includes an input impedance matching circuit 1230, an interstage impedance matching circuit 1240, and an output impedance matching circuit 1250.

As shown in fig. 20D, in still other embodiments, an MMIC switch 1300 may be provided that exhibits increased power handling capability or has a reduced physical size for a given operating frequency as compared to conventional RF switches. The MMIC switch 1300 may include, for example, an RF input 1302, a plurality of RF outputs 1304, and a control input 1306. A plurality of individual RF switches 1310 may be included in the MMIC switch 1300. Some or all of the RF switch 1310 may be implemented using a pass gate transistor in accordance with an embodiment of the invention. The MMIC switch 1300 may be used, for example, in an RF switching network for a phased array antenna.

As discussed above, the maximum output power supported by prior art MMIC amplifiers is limited due to the limitations on the good gate regions available and the limitations on gate width based on loop stability and power loss considerations. An MMIC amplifier according to embodiments of the invention may, for example, provide a three-fold increase in maximum power density for amplifiers operating at frequencies up to 6GHz and a two-fold increase in maximum power density for amplifiers operating at frequencies between 6-15 GHz. FET-based MMIC devices according to embodiments of the invention may implement FET transistors included in these MMIC devices using any of the bypass gate transistor designs disclosed herein. For example, each FET-based MMIC device disclosed herein according to embodiments of the invention may use any of the bypass-gate transistors discussed above with reference to fig. 2-7, 8-9B, 10-11, 12, 13, 14, and/or 15, and each modification thereof discussed above.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises," "comprising," "includes," and/or "including," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

It will be understood that when an element such as a layer, region or substrate is referred to as being "on" or extending "over" another element, it can extend directly on or over the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly over" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

Relative terms such as "below" or "above" or "upper" or "lower" or "horizontal" or "lateral" or "vertical" may be used herein to describe one element, layer or region's relationship to another element, layer or region as illustrated in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures.

Embodiments of the present invention are described herein with reference to cross-sectional illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the present invention. The thickness of layers and regions in the drawings may be exaggerated for clarity. Additionally, variations in the shapes of the illustrations as a result, for example, of manufacturing techniques and/or tolerances. Accordingly, embodiments of the present invention should not be construed as limited to the particular shapes of regions illustrated herein but are to include deviations in shapes that result, for example, from manufacturing.

In the drawings and specification, there have been disclosed typical embodiments of the invention and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation, the scope of the invention being set forth in the following claims.

Claims

1. A transistor, comprising:

a drain contact extending along a first axis;

a source contact extending along a second axis parallel to the first axis;

a gate finger extending between the source contact and the drain contact; and

a gate bus electrically connected to the gate finger;

a gate jumper electrically connected to the gate bus line, wherein the gate jumper is interposed along an electrical path between the gate finger and the gate bus line; and

a plurality of spaced apart lossy elements electrically connected to the gate fingers,

wherein at least one of the lossy elements is disposed in a portion of the region between the first and second axes, the portion being between the first and second ends of the gate finger, and

wherein a first one of the lossy elements is inserted along an electrical path between the gate jumper and the gate finger.

2. The transistor of claim 1, wherein each lossy element is a gate resistor.

3. The transistor of claim 2, wherein the gate finger comprises a plurality of physically discontinuous gate finger segments electrically connected to one another.

4. A transistor according to claim 3 wherein the discontinuous gate finger segments are collinear.

5. The transistor of any of claims 3-4, wherein each gate finger segment is part of a respective gate split, the transistor further comprising an odd mode resistor positioned between two adjacent gate splits.

6. The transistor of claim 1, wherein the source contact comprises a plurality of discrete source contact segments electrically connected to one another.

7. The transistor of claim 6, further comprising:

a second source contact comprising a plurality of collinear, discontinuous source contact segments; and

an odd mode resistor positioned between two adjacent ones of the source contact segments of the second source contact.

8. The transistor of any of claims 1-4, wherein the gate jumper extends over and is electrically insulated from the source contact.

9. The transistor of claim 6, wherein the gate jumper extends over only some of the source contact segments.

10. The transistor of any of claims 2-4, wherein the gate finger is formed of a first material and each gate resistor is formed of a second material having a higher resistance than the first material.

11. A transistor according to claim 3, wherein a first one of the lossy elements is interposed along an electrical path between a first one of the gate finger segments and a first gate signal distribution strip extending between the gate jumper and the first one of the gate finger segments.

12. The transistor of claim 11, wherein an odd mode resistor is interposed between the first gate signal distribution bar and a second gate signal distribution bar collinear with the first gate signal distribution bar.

13. The transistor of any of claims 1-4, wherein the source contact comprises a plurality of discontinuous source contact segments electrically connected to each other, wherein the gate jumper extends over the source contact, and wherein a first gate signal distribution bar is in a gap between two adjacent source contact segments.

14. The transistor of claim 13, further comprising a conductive plug connecting the gate jumper to the first gate signal distribution bar.

15. A transistor, comprising:

a source contact extending in a first direction;

a gate jumper extending in the first direction;

a gate bus line extending in a second direction;

a gate finger, the gate finger comprising a plurality of discontinuous gate finger segments; and

a plurality of spaced apart lossy elements, each lossy element of the plurality of spaced apart lossy elements electrically connected to the gate jumper;

wherein a first one of the gate finger segments is connected to the gate jumper by a first one of the lossy elements,

wherein the gate jumper extends parallel to a second one of the gate finger segments and the second one of the gate finger segments is electrically connected to the gate bus by a second one of the lossy elements.

16. The transistor of claim 15, wherein each lossy element is a gate resistor.

17. The transistor of claim 15 or 16, wherein the first one of the lossy elements is in a gap between two adjacent gate finger segments.

18. The transistor of any of claims 15 or 16, wherein the discontinuous gate finger segments are collinear.

19. The transistor of any of claims 15 or 16, wherein the source contact comprises a plurality of discontinuous source contact segments electrically connected to each other, and wherein the gate jumper extends over and is electrically insulated from the source contact.

20. The transistor of any of claims 15 or 16, further comprising a plurality of additional gate jumpers, wherein the source contact extends farther from the gate bus than the gate jumpers.

21. The transistor of claim 15, further comprising:

a drain contact extending in the first direction adjacent to the gate finger such that the gate finger extends between the source contact and the drain contact;

a second gate finger comprising a plurality of discontinuous gate finger segments extending in the first direction electrically connected to each other such that the drain contact extends between the gate finger and the second gate finger; and

a second source contact comprising a plurality of discrete source contact segments electrically connected to each other, the plurality of discrete source contact segments extending in the first direction adjacent to the second gate finger.

22. The transistor of claim 21, further comprising an odd mode resistor in a gap between two adjacent source contact segments of the second source contact.

23. The transistor of claim 21 or 22, further comprising a gate signal distribution bar extending between the gate jumper and a first one of the gate finger segments of the gate finger and between the gate jumper and a first one of the gate finger segments of the second gate finger.

24. The transistor of claim 23, wherein the gate signal distribution strip is in a gap between two adjacent source contact segments of the source contact.

25. The transistor of claim 23, wherein an odd mode resistor is connected between the gate signal distribution bar and a second gate signal distribution bar connecting gate finger segments of a plurality of additional gate fingers to a second gate jumper.