CN110581066B

CN110581066B - Manufacturing method of multiple mask layer

Info

Publication number: CN110581066B
Application number: CN201810579600.6A
Authority: CN
Inventors: 请求不公布姓名
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2018-06-07
Filing date: 2018-06-07
Publication date: 2024-06-21
Anticipated expiration: 2038-06-07
Also published as: CN110581066A

Abstract

The invention provides a manufacturing method of a multiple mask layer, which comprises the steps of forming grooves by stacking multiple layers of hard masks with different etching selection ratios and self-aligning, exposing the multiple layers of hard masks on the surface by a thinning process, and finally obtaining the multiple mask layer by selective etching. According to the manufacturing method of the multiple mask layers, a structure similar to a ox horn is not formed in the manufacturing process of space multiplication, and the precise etching of the multiple mask layers can be greatly improved. The invention utilizes the configuration of different lamination of the multi-layer mask layer and the selection of etching rate ratio, and based on the method of forming the groove by self-alignment, the multi-layer mask layer is manufactured, thereby effectively reducing the characteristic size of the device and increasing the characteristic density of the device. Meanwhile, the invention can realize 3 times and 4 times of space multiplication, and can realize the width adjustment of the gap by controlling the thickness of each mask layer.

Description

Manufacturing method of multiple mask layer

Technical Field

The invention belongs to the field of semiconductor manufacturing, and particularly relates to a manufacturing method of a multiple mask layer.

Background

With the continued development of semiconductor technology, integrated circuits have become smaller and denser, which provides many advantages to the performance of integrated circuits, but at the same time, the production of smaller and denser integrated circuits has become more difficult to achieve and expensive to manufacture due to manufacturing equipment limitations. Improved processes are therefore used to reduce feature sizes, thereby increasing the density of integrated circuits.

Pitch doubling or pitch multiplication is a method that can extend the capabilities of photolithography beyond its minimum pitch. The existing manufacturing method of the space multiplication mask layer comprises the following steps:

1) Providing a substrate 101, and forming a bottom mask layer 102 on the substrate;

2) Forming a patterned photoresist layer on the bottom mask layer 102, wherein the photoresist layer comprises a plurality of photoresist units 103, and two adjacent photoresist units are provided with first gaps 104;

3) Depositing a silicon dioxide layer 105 on the bottom mask layer 102, wherein the silicon dioxide layer 105 covers the sidewalls of the photoresist units 103 and covers the bottoms of the first gaps 104 and the surfaces of the photoresist units 103;

4) Etching to remove the surface of the photoresist unit 103 and the silicon dioxide layer 105 at the bottom of the first gap 104, and retaining the silicon dioxide layer 105 on the side wall of the photoresist unit 103;

5) Removing the photoresist unit 103, and retaining the silicon dioxide layer 105 on the side wall of the photoresist unit 103;

6) Etching the bottom mask layer 102 with the silicon dioxide layer 105 as a mask until the substrate 101 is exposed to form a second gap 106 in the bottom mask layer 102;

7) The silicon dioxide layer 105 is removed.

In the above manufacturing method, a "ox horn" similar structure is formed in the process of forming the pitch multiplication mask layer, such as the silicon dioxide layer 105 shown in fig. 4, and when the bottom mask layer 102 is etched by using the "ox horn" similar structure, the etching accuracy may be reduced, which is not beneficial to improving the manufacturing accuracy of the mask layer. In addition, the above method can only manufacture double mask layers, and can not meet the production requirement under the condition that the space needs to be further reduced.

Based on the above, it is necessary to provide a method for manufacturing a multiple mask layer, which can effectively improve the accuracy of the multiple mask layer and further reduce the pitch.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, an object of the present invention is to provide a method for manufacturing a multiple mask layer, which is used for solving the problems of low precision and difficulty in further reducing the pitch of the multiple mask layer in the prior art.

To achieve the above and other related objects, the present invention provides a method for manufacturing a multiple mask layer, including: 1) Providing a substrate, forming a first mask layer on the substrate, wherein the first mask layer comprises a plurality of imaging mask units, and imaging gaps on the substrate are formed among the imaging mask units; 2) Depositing a second mask layer on the substrate, wherein the second mask layer covers the top surface and the side wall of the imaging mask unit and the bottom of the imaging gap so as to form a first groove in the imaging gap in a self-aligning mode, and the bottom of the first groove is lower than the top surface of the imaging mask unit; 3) Depositing a third mask layer on the second mask layer, wherein the third mask layer at least fills the first grooves, and the third mask layer comprises a plurality of first intermediate mask units positioned in the first grooves; 4) Thinning the third mask layer and the second mask layer until the imaging mask unit is exposed, and exposing the second mask layer and the third mask layer at the same time, wherein the thinned second mask layer has a size corresponding to the imaging gap, and the first intermediate mask unit of the third mask layer is separated and embedded in the second mask layer; 5) Selectively etching to remove the imaging mask unit of the first mask layer to form an anti-imaging gap on the substrate; 6) Depositing a fourth mask layer on the substrate, wherein the fourth mask layer covers the top surface and the side wall of the second mask layer, the top surface of the first intermediate mask unit and the bottom of the reverse imaging gap so as to form a second groove in the reverse imaging gap in a self-aligning mode, and the bottom of the second groove is lower than the top surface of the second mask layer and not higher than the bottom surface of the first intermediate mask unit; 7) Depositing a fifth mask layer on the fourth mask layer, wherein the fifth mask layer at least fills the second grooves, and the fifth mask layer comprises a plurality of second intermediate mask units positioned in the second grooves; 8) Thinning the fifth mask layer and the fourth mask layer until the second mask layer is exposed, and exposing the first intermediate mask unit, the fourth mask layer and the fifth mask layer at the same time, wherein the thinned fourth mask layer has a size corresponding to the reverse imaging gap, and the second intermediate mask unit of the fifth mask layer is separated and embedded in the fourth mask layer; 9) Patterning and etching the second mask layer based on the first intermediate mask unit of the third mask layer to form a multiple division gap in the imaging gap on the substrate, wherein one side of the first multiple division gap comprises a side wall of the first intermediate mask unit, and the other side of the first multiple division gap comprises a side wall of the fourth mask layer after thinning; 10 Selectively etching to remove the second intermediate mask unit of the fifth mask layer in the second recess; and 11) self-aligning the fourth mask layer based on the second groove until the substrate is exposed at the second groove, so that the fourth mask layer is formed with a double-divided spacer on the substrate and in the reverse imaging gap, the double-divided spacer having a second double-divided gap therebetween.

Preferably, step 1) further comprises a step of performing mask trimming on the imaging mask unit to reduce the width of the imaging mask unit.

Preferably, the mask trimming method comprises one or two of the group consisting of isotropic dry etching and anisotropic wet etching.

Preferably, in step 5), the etching selectivity ratio of the first mask layer to the second mask layer is not less than 10:1, and the etching selectivity ratio of the first mask layer to the third mask layer is not less than 10:1.

Preferably, in step 9), the etching selectivity ratio of the second mask layer to the third mask layer is not less than 10:1, the etching selectivity ratio of the second mask layer to the fourth mask layer is not less than 10:1, and the etching selectivity ratio of the second mask layer to the fifth mask layer is not less than 10:1.

Preferably, in step 10), the etching selectivity ratio of the fifth mask layer to the third mask layer is not less than 10:1, and the etching selectivity ratio of the fifth mask layer to the fourth mask layer is not less than 10:1.

Preferably, the material of the first mask layer includes one of a group consisting of photoresist, silicon dioxide, silicon nitride, silicon oxynitride and polysilicon; the material of the second mask layer comprises one of the group consisting of photoresist, silicon dioxide, silicon nitride, silicon oxynitride and polysilicon; the material of the third mask layer comprises one of the group consisting of photoresist, silicon dioxide, silicon nitride, silicon oxynitride and polysilicon; the material of the fourth mask layer comprises one of the group consisting of photoresist, silicon dioxide, silicon nitride, silicon oxynitride and polysilicon; the fifth mask layer is made of one of photoresist, silicon dioxide, silicon nitride, silicon oxynitride and polysilicon.

Preferably, the method further includes step 12), etching to remove the third mask layer to form a plurality of mask layers including the first and fourth mask layers in the imaging gap and separated by the second mask layer.

Preferably, the width of the first division gap is adjusted by controlling the thickness of the second mask layer deposited on the sidewall of the imaging mask unit, and the width of the second division gap is adjusted by controlling the width of the second groove.

Preferably, the thickness of the second mask layer is controlled to be equal to the width of the second groove, so that the width of the first dividing gap is equal to the width of the second dividing gap.

The invention also provides a manufacturing method of the multiple mask layer, which comprises the following steps: 1) Providing a substrate, forming a first mask layer on the substrate, wherein the first mask layer comprises a plurality of imaging mask units, and imaging gaps on the substrate are formed among the imaging mask units; 2) Depositing a second mask layer on the substrate, wherein the second mask layer covers the top surface and the side wall of the imaging mask unit and the bottom of the imaging gap so as to form a first groove in the imaging gap in a self-aligning mode, and the bottom of the first groove is lower than the top surface of the imaging mask unit; 3) Depositing a third mask layer on the second mask layer, wherein the third mask layer at least fills the first grooves, and the third mask layer comprises a plurality of first intermediate mask units positioned in the first grooves; 4) Thinning the third mask layer and the second mask layer until the imaging mask unit is exposed, and exposing the second mask layer and the third mask layer at the same time, wherein the thinned second mask layer has a size corresponding to the imaging gap, and the first intermediate mask unit of the third mask layer is separated and embedded in the second mask layer; 5) Etching the second mask layer based on the third mask layer to form a first inverse imaging gap on the substrate; 6) Depositing a fourth mask layer on the substrate, wherein the fourth mask layer covers the first mask layer, the third mask layer and the first reverse imaging gap, and the fourth mask layer comprises a plurality of second intermediate mask units positioned in the first reverse imaging gap; 7) Thinning the fourth mask layer until the first mask layer and the third mask layer are exposed, and reserving the second intermediate mask units in the first inverse imaging gaps, wherein the second intermediate mask units are separated and embedded in the first inverse imaging gaps so as to simultaneously expose the first mask layer, the third mask layer and the second intermediate mask units; 8) Selectively etching to remove the first mask layer to form a second inverse imaging gap on the substrate; 9) Selectively etching to remove the third mask layer and the second mask layer to form a third reflective imaging gap on the substrate; 10 Depositing a fifth mask layer on the substrate, wherein the fifth mask layer covers the top surface and the side wall of the second intermediate mask unit, the bottom of the second inverse imaging gap and the bottom of the third inverse imaging gap to form a second groove in the second inverse imaging gap in a self-aligned manner and form a third groove in the third inverse imaging gap in a self-aligned manner, and the bottoms of the second groove and the third groove are lower than the top surface of the second intermediate mask unit; 11 Depositing a sixth mask layer on the fifth mask layer, wherein the sixth mask layer at least fills the second groove and the third groove, and the sixth mask layer comprises a plurality of third intermediate mask units positioned in the second groove and a plurality of fourth intermediate mask units positioned in the third groove; 12 Thinning the sixth mask layer and the fifth mask layer until the fourth mask layer is exposed, wherein the second groove reserves the third intermediate mask unit, and the third groove reserves the fourth intermediate mask unit so as to simultaneously expose the fourth mask layer, the fifth mask layer, the third intermediate mask unit and the fourth intermediate mask unit; and 13) etching the fifth mask layer based on the third and fourth intermediate mask units to form a first and second division gaps on the substrate, wherein the first division gap is located within the second inverse imaging gap and the second division gap is located within the third inverse imaging gap.

Preferably, in step 5), the etching selectivity ratio of the second mask layer to the first mask layer is not less than 10:1, and the etching selectivity ratio of the second mask layer to the third mask layer is not less than 10:1.

Preferably, in step 8), the etching selectivity ratio of the first mask layer to the fourth mask layer is not less than 10:1, and in step 9), the etching selectivity ratio of the second mask layer to the fourth mask layer is not less than 10:1, and the etching selectivity ratio of the third mask layer to the fourth mask layer is not less than 10:1.

Preferably, in step 13), the etching selectivity ratio of the fifth mask layer to the fourth mask layer is not less than 10:1, and the etching selectivity ratio of the fifth mask layer to the sixth mask layer is not less than 10:1.

Preferably, the material of the first mask layer includes one of a group consisting of photoresist, silicon dioxide, silicon nitride, silicon oxynitride and polysilicon; the material of the second mask layer comprises one of the group consisting of photoresist, silicon dioxide, silicon nitride, silicon oxynitride and polysilicon; the material of the third mask layer comprises one of the group consisting of photoresist, silicon dioxide, silicon nitride, silicon oxynitride and polysilicon; the material of the fourth mask layer comprises one of the group consisting of photoresist, silicon dioxide, silicon nitride, silicon oxynitride and polysilicon; the fifth mask layer is made of one of photoresist, silicon dioxide, silicon nitride, silicon oxynitride and polysilicon; the sixth mask layer is made of one of photoresist, silicon dioxide, silicon nitride, silicon oxynitride and polysilicon.

Preferably, the width of the first division gap and the width of the second division gap are adjusted by controlling the thickness of the fifth mask layer deposited on the side wall of the fourth mask layer.

Preferably, the width of the first dividing gap is equal to the width of the second dividing gap.

The invention also provides a manufacturing method of the multiple mask layer, which comprises the following steps: 1) Providing a substrate, forming a bottom mask layer on the substrate, and forming a first mask layer on the bottom mask layer, wherein the first mask layer comprises a plurality of imaging mask units, and imaging gaps on the bottom mask layer are formed between the imaging mask units;

2) Depositing a second mask layer on the bottom mask layer, wherein the second mask layer covers the top surface and the side wall of the imaging mask unit and the bottom of the imaging gap, and simultaneously, a first groove is formed in the imaging gap in a self-aligning manner, and the bottom of the first groove is lower than the top surface of the imaging mask unit; 3) Depositing a third mask layer on the second mask layer, wherein the third mask layer covers the bottom and the side wall of the first groove so as to form a second groove in the first groove in a self-aligned manner; 4) Depositing a fourth mask layer on the third mask layer, wherein the fourth mask layer at least fills the second grooves, and the fourth mask layer comprises a plurality of first intermediate mask units positioned in the second grooves; 5) Thinning the fourth mask layer until the third mask layer is exposed, wherein the first intermediate mask unit is reserved in the second groove; 6) Etching the third mask layer based on the first intermediate mask unit to form a first inverse imaging gap on the second mask layer; 7) Further etching the second mask layer based on the first anti-imaging gap until the bottom mask layer is exposed at the first anti-imaging gap, wherein the second mask layer is reserved on the side wall of the imaging mask unit; 8) Selectively etching to remove the first mask layer to form a second anti-imaging gap on the bottom mask layer, the second anti-imaging gap being larger than the first anti-imaging gap; 9) Selectively etching the bottom mask layer to transfer the first inverse imaging gap into the bottom mask layer to form a first division gap and transfer the second inverse imaging gap into the bottom mask layer to form a third inverse imaging gap; 10 Selectively etching to remove the second mask layer, the third mask layer and the fourth mask layer; 11 Depositing a fifth mask layer on the bottom mask layer, wherein a third groove is formed in the third inverse imaging gap in a self-alignment manner while the fifth mask layer fills the first inverse imaging gap based on the third inverse imaging gap being larger than the first inverse imaging gap, and the bottom of the third groove is lower than the top surface of the bottom mask layer; 12 Depositing a sixth mask layer on the fifth mask layer, wherein the sixth mask layer at least fills the third groove, and the sixth mask layer comprises a plurality of second intermediate mask units positioned in the third groove; 13 Thinning the sixth mask layer and the fifth mask layer until the bottom mask layer is exposed, wherein the third groove is reserved with the second intermediate mask unit so as to simultaneously expose the bottom mask layer, the fifth mask layer and the second intermediate mask unit; and 14) etching the fifth mask layer within the third reflective gap based on the second intermediate mask unit to form a second division gap on the substrate while removing the fifth mask layer within the first division gap to form a first division gap on the substrate.

Preferably, in step 7), the second mask layer is further etched based on the first anti-imaging gap until the second mask layer on the upper surface of the first mask layer is simultaneously removed to expose the first mask layer when the bottom mask layer is exposed at the first anti-imaging gap.

Preferably, in step 6), the etching selectivity ratio of the third mask layer to the fourth mask layer is not less than 10:1, and in step 7), the etching selectivity ratio of the second mask layer to the fourth mask layer is not less than 10:1.

Preferably, the width of the first division gap is adjusted by controlling the thickness of the third mask layer at two sides of the second groove.

Preferably, the width of the second dividing gap is adjusted by controlling the thickness of the fifth mask layer at two sides of the third groove.

The invention also provides a multiple mask layer, which comprises the following steps: the anti-imaging spacers are formed on the substrate at equal intervals, an anti-imaging gap is formed between the anti-imaging spacers, and the width of each anti-imaging spacer is smaller than the minimum exposure development size; and a plurality of spacers formed on the substrate, each of the plurality of spacers having two spaces therebetween, a first plurality of spacers being formed between the plurality of spacers and the plurality of spacers, a second plurality of spacers being formed between the plurality of spacers, and a width of the plurality of spacers being smaller than the minimum exposure development dimension.

Preferably, the width of the inverse imaging spacer is equal to one third of the minimum exposure development dimension, and the width of the multiple-division spacer is equal to one third of the minimum exposure development dimension.

The invention also provides a multiple mask layer, which comprises the following steps: the anti-imaging spacers are formed on the substrate at equal intervals, first anti-imaging gaps and second anti-imaging gaps are alternately arranged among the anti-imaging spacers, and the width of each anti-imaging spacer is smaller than half of the minimum exposure development size; a first division spacer formed on the substrate within the first inverse imaging gap, the first division spacer having a first division gap with the inverse imaging spacer, the first division spacer having a width less than half of the minimum exposure development dimension; and a second division spacer formed on the substrate in the second inverse imaging gap, the second division spacer having a second division gap with the inverse imaging spacer, the second division spacer having a width less than half of the minimum exposure development dimension.

Preferably, the width of the inverse image spacer is equal to one fourth of the minimum exposure development dimension, the width of the first division spacer is equal to one fourth of the minimum exposure development dimension, and the width of the second division spacer is equal to one fourth of the minimum exposure development dimension. .

The invention also provides a multiple mask layer, which comprises the following steps: the anti-imaging spacers are formed on the substrate, each three anti-imaging spacers are in an anti-imaging spacer group, a first doubling gap is formed between the anti-imaging spacers in the group, anti-imaging gaps are formed between two adjacent anti-imaging gap groups, and the width of each anti-imaging spacer is smaller than half of the minimum exposure development size; and a plurality of sub-spacers formed on the substrate, wherein one sub-spacer is formed in each of the plurality of anti-imaging gaps, a second sub-spacer is formed between each sub-spacer and the adjacent anti-imaging spacer, and the width of each sub-spacer is smaller than half of the minimum exposure development dimension.

Preferably, the width of the first dividing gap is not equal to the width of the second dividing gap.

Preferably, the width of the inverse imaging spacer is equal to one-fourth of the minimum exposure development dimension, and the width of the multiple-division spacer is equal to one-fourth of the minimum exposure development dimension.

As described above, the manufacturing method of the multiple mask layer has the following beneficial effects:

1) According to the manufacturing method of the multiple mask layers, a structure similar to a ox horn is not formed in the manufacturing process of space multiplication, and the precise etching of the multiple mask layers can be greatly improved.

2) The invention utilizes the configuration of different lamination of the multi-layer mask layer and the selection of etching rate ratio, and based on the method of forming the groove by self-alignment, the multi-layer mask layer is manufactured, thereby effectively reducing the characteristic size of the device and increasing the characteristic density of the device.

3) The invention can realize 3 times and 4 times of space multiplication, and can realize the width adjustment of the gap by controlling the thickness of each mask layer.

4) The invention can realize gaps with two or more different widths in the same multiple mask layer, and greatly expands the application range of the multiple mask layer.

Drawings

Fig. 1 to 6 are schematic structural diagrams showing steps of a method for fabricating a pitch multiplication mask layer in the prior art.

Fig. 7 to 19 are schematic structural views showing steps of a method for fabricating a multiple mask layer in embodiment 1 of the present invention.

Fig. 20 to 33 are schematic structural views showing steps of a method for fabricating a multiple mask layer in embodiment 2 of the present invention.

Fig. 34 to 48 are schematic structural diagrams showing steps of the method for fabricating a multiple mask layer in embodiment 3 of the present invention.

Fig. 49 is a schematic diagram showing the structure of multiple mask layers in embodiment 4 of the present invention.

Fig. 50 is a schematic diagram showing the structure of multiple mask layers in embodiment 5 of the present invention.

Fig. 51 is a schematic diagram showing the structure of multiple mask layers in embodiment 6 of the present invention.

Description of element reference numerals

101. Substrate

102. Bottom mask layer

103. Photoresist unit

104. First gap

105. Silicon dioxide layer

106. Second gap

201. Substrate

202. Bottom mask layer

203. First mask layer

2031. Imaging mask unit

204. Imaging gap

205. Second mask layer

206. First groove

207. Third mask layer

209. Fourth mask layer

210. Second groove

211. Fifth mask layer

212. First time division gap

213. Second dividing gap

214. Reverse imaging gap

215. First inverse imaging gap

216. Sixth mask layer

217. Second inverse imaging gap

218. Third reflective imaging gap

221. Third groove

301. First intermediate mask unit

302. Second intermediate mask unit

303. Multiple division spacer

304. Third intermediate mask unit

305. Fourth intermediate mask unit

401. Substrate

402. Inverse imaging spacer

403. Multiple division spacer

404. Reverse imaging gap

501. Substrate

502. Inverse imaging spacer

503. First dividing spacer

504. Second dividing spacer

505. First inverse imaging gap

506. Second inverse imaging gap

601. Substrate

602. Inverse imaging spacer

603. Anti-imaging spacer group

604. Multiple division spacer

605. Reverse imaging gap

Detailed Description

Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention.

Please refer to fig. 7-51. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings rather than the number, shape and size of the components in actual implementation, and the form, number and proportion of each component in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.

The present invention may be used in the manufacture of any integrated circuit, which is particularly advantageous for forming a repeating pattern or array of semiconductor devices including arrays of memory cells of volatile and non-volatile memory devices such as DRAM, phase change RAM, programmable Conductors (PCRAM), ROM or flash memory, or integrated circuits having logic arrays.

Examples

As shown in fig. 7 to 19, the present embodiment provides a method for manufacturing a multiple mask layer, where the method includes:

As shown in fig. 7 to 8, step 1) is first performed, a substrate 201 is provided, a first mask layer 203 is formed on the substrate 201, the first mask layer 203 includes a plurality of imaging mask units 2031, and an imaging gap 204 is formed between the imaging mask units 2031 on the substrate 201, and the size of the imaging mask units 2031 depends on the capability of minimum exposure development size.

The substrate 201 includes a layer to be etched, and the layer to be etched may be a semiconductor substrate material, a dielectric material, a metal material, various laminated materials composed of the above materials, and the like.

The material of the first mask layer 203 includes one of a group consisting of photoresist, silicon dioxide, silicon nitride, silicon oxynitride and polysilicon. In this embodiment, the material of the first mask layer 203 may be selected as photoresist, a photoresist layer is first formed on the substrate 201 by using a spin-coating process, and then the photoresist layer is patterned by using a photolithography process to form a plurality of photoresist imaging mask units 2031.

After forming the plurality of imaging mask units 2031 by photolithography, a step of performing mask trimming on the imaging mask units 2031 is further included to reduce the width of the imaging mask units 2031. For example, the mask trimming method includes one or both of the group consisting of isotropic dry etching and anisotropic wet etching.

As shown in fig. 9, step 2) is then performed, and a second mask layer 205 is deposited on the substrate 201, where the second mask layer 205 covers the top surface and the sidewalls of the imaging mask unit 2031 and the bottom of the imaging gap 204, so as to form a first groove 206 in the imaging gap 204 in a self-aligned manner, and the bottom of the first groove 206 is lower than the top surface of the imaging mask unit 2031.

By selecting the deposition process and the deposition rate, the cross-sectional shape of the first groove 206 is controlled to be rectangular, so that the precision of the subsequent mask layer manufacturing can be effectively improved.

The material of the second mask layer 205 includes one of a group consisting of photoresist, silicon dioxide, silicon nitride, silicon oxynitride and polysilicon. Preferably, the second mask layer 205 is selected to have an etching selectivity ratio with respect to the first mask layer 203 of not less than 10:1, for example, the material of the second mask layer 205 may be selected to be silicon dioxide (SiO ₂). The second mask layer 205 may be formed by a vapor deposition process such as sputtering, chemical Vapor Deposition (CVD), and Atomic Layer Deposition (ALD).

The thickness of the second mask layer 205 is controlled such that the second mask layer 205 covers the top surface and the side walls of the imaging mask unit 2031 and the bottom of the imaging gap 204, so as to form a first groove 206 in the imaging gap 204 in a self-aligned manner. In a subsequent process, the width of the first division gap 212 may be adjusted by controlling the thickness of the second mask layer 205 deposited on the sidewall of the imaging mask unit 2031.

As shown in fig. 10, step 3) is performed, a third mask layer 207 is deposited on the second mask layer 205, and the third mask layer 207 fills at least the first recess 206, and the third mask layer 207 includes a plurality of first intermediate mask units 301 located in the first recess.

The material of the third mask layer 207 includes one of a group consisting of photoresist, silicon dioxide, silicon nitride, silicon oxynitride and polysilicon. By selecting the material of the third mask layer 207, the etching selection ratio of the first mask layer 203 to the third mask layer 207 is not less than 10:1, and at the same time, the etching selection ratio of the second mask layer 205 to the third mask layer 207 is not less than 10:1, for example, when the first mask layer 203 is selected as photoresist, the material of the third mask layer 207 may be selected as silicon nitride (SiN) or silicon oxynitride (SiON) or polysilicon (Si poly), and in this embodiment, the material of the third mask layer 207 may be selected as silicon nitride (SiN). The third mask layer 207 may be formed by a vapor deposition process such as sputtering, chemical Vapor Deposition (CVD), and Atomic Layer Deposition (ALD).

As shown in fig. 11, step 4) is performed, where the third mask layer 207 and the second mask layer 205 are thinned until the imaging mask unit 2031 is exposed, and the second mask layer 205 and the third mask layer 207 are exposed, and after the thinning, the second mask layer 205 has a size corresponding to the imaging gap 204, and the first intermediate mask unit 301 of the third mask layer 207 is separated and embedded in the second mask layer 205.

For example, the third mask layer 207 and the second mask layer 205 may be thinned by a chemical mechanical polishing process or an etching process until the first mask layer 203 is exposed, and the first recess 206 remains the first intermediate mask unit 301 after the thinning, because the bottom of the first recess 206 is lower than the top surface of the first mask layer 203.

As shown in fig. 12, step 5) is then performed to selectively etch away the imaging mask unit 2031 to form the anti-imaging gap 214 on the substrate 201.

Since the etching selectivity ratio of the first mask layer 203 to the second mask layer 205 is not less than 10:1, and the etching selectivity ratio of the first mask layer 203 to the third mask layer 207 is not less than 10:1, the second mask layer 205 and the third mask layer 207 can be substantially completely maintained after the first mask layer 203 is completely etched.

As shown in fig. 13, step 6) is performed, and a fourth mask layer 209 is deposited on the substrate 201, where the fourth mask layer 209 covers the top surface and the sidewall of the second mask layer 205, the top surface of the first intermediate mask unit 301, and the bottom of the anti-imaging gap, so as to form a second groove 210 in the anti-imaging gap 214 in a self-aligned manner, and the bottom of the second groove 210 is lower than the top surface of the second mask layer 205 and not higher than the bottom surface of the first intermediate mask unit 301.

The material of the fourth mask layer 209 includes one of a group consisting of photoresist, silicon dioxide, silicon nitride, silicon oxynitride and polysilicon. By selecting the material of the fourth mask layer 209, the etching selection ratio of the second mask layer 205 to the fourth mask layer 209 is not less than 10:1, for example, when the second mask layer 205 is selected to be silicon dioxide (SiO ₂), the material of the fourth mask layer 209 may be selected to be silicon oxynitride (SiON) or polysilicon (Si poly), etc., and in this embodiment, the material of the fourth mask layer 209 may be selected to be silicon oxynitride (SiON). The fourth mask layer 209 may be formed by a vapor deposition process such as sputtering, chemical Vapor Deposition (CVD), and Atomic Layer Deposition (ALD).

By selecting the deposition process and the deposition rate, the cross-sectional shape of the second recess 210 is controlled to be rectangular, so that the precision of the subsequent mask layer manufacturing can be effectively improved.

As shown in fig. 14, step 7) is performed, a fifth mask layer 211 is deposited on the fourth mask layer 209, and the fifth mask layer 211 at least fills the second recess 210, wherein the fifth mask layer 211 includes a plurality of second intermediate mask units 302 located in the second recess 210.

The material of the fifth mask layer 211 includes one of a group consisting of photoresist, silicon dioxide, silicon nitride, silicon oxynitride and polysilicon. For the above materials, the material selection of the fifth mask layer 211 is based on: the etching selectivity ratio of the second mask layer 205 to the fifth mask layer 211 is not less than 10:1, the etching selectivity ratio of the fifth mask layer 211 to the third mask layer 207 is not less than 10:1, and the etching selectivity ratio of the fifth mask layer 211 to the fourth mask layer 209 is not less than 10:1. In this embodiment, the material of the fifth mask layer 211 is polysilicon.

As shown in fig. 15, step 8) is performed, where the fifth mask layer 211 and the fourth mask layer 209 are thinned until the second mask layer 205 is exposed, and the first intermediate mask unit 301, the fourth mask layer 209 and the fifth mask layer 211 are exposed, and after the thinning, the fourth mask layer 209 has a size corresponding to the inverse imaging gap 214, and the second intermediate mask unit 302 of the fifth mask layer 211 is separated and embedded in the fourth mask layer 209.

For example, the fifth mask layer 211 and the fourth mask layer 209 may be thinned by a chemical mechanical polishing process or an etching process until the second mask layer 205 is exposed, and the second recess 210 remains the fifth mask layer 211 after the thinning, because the bottom of the second recess 210 is lower than the top surface of the second mask layer 205.

As shown in fig. 16, step 9) is performed next, in which the second mask layer 205 is patterned and etched based on the first intermediate mask unit 301 of the third mask layer 207, so as to form a first division gap 212 in the imaging gap 204 on the substrate 201, wherein one side of the first division gap 212 includes a sidewall of the first intermediate mask unit 301, and the other side of the first division gap 212 includes a sidewall of the thinned fourth mask layer 209.

The etching selectivity ratio of the second mask layer 205 to the third mask layer 207 is not less than 10:1, the etching selectivity ratio of the second mask layer 205 to the fourth mask layer 209 is not less than 10:1, and the etching selectivity ratio of the second mask layer 205 to the fifth mask layer 211 is not less than 10:1. The second mask layer 205 is etched based on the etching selectivity, and after the first division gap 212 is formed on the substrate 201, the third mask layer 207, the fourth mask layer 209 and the fifth mask layer 211 may remain almost completely, and the second mask layer 205 below the third mask layer 207 may also remain.

As shown in fig. 17, step 10) is performed next, and the second intermediate mask unit 302 of the fifth mask layer 211 in the second recess 210 is selectively etched to be removed.

The etching selectivity ratio of the fifth mask layer 211 to the third mask layer 207 is not less than 10:1, and the etching selectivity ratio of the fifth mask layer 211 to the fourth mask layer 209 is not less than 10:1. Based on the etching selectivity, the third mask layer 207 and the fourth mask layer 209 may remain almost completely after etching to remove the fifth mask layer 211 in the second recess 210.

As shown in fig. 18, step 11) is then performed to self-align etch the fourth mask layer 209 based on the second recess 210 until the substrate 201 is exposed at the second recess 210, such that the fourth mask layer 209 is formed with a plurality of sub-division spacers 303 on the substrate and in the anti-imaging gaps, the sub-division spacers having second sub-division gaps 213 therebetween.

The width of the second dividing gap 213 is adjusted by controlling the width of the second groove 210.

In the above manufacturing process, the thickness of the second mask layer 205 may be controlled to be equal to the width of the second groove 210, so that the width of the first dividing gap 212 is equal to the width of the second dividing gap 213.

Of course, the widths of the first and second dividing gaps 212 and 213 may be different by controlling the thickness of the second mask layer 205 and the width of the second recess 210.

As shown in fig. 19, step 12) is finally performed, and the third mask layer 207 is etched to remove the multiple mask layers including the second mask layer 205 and the fourth mask layer 209.

In the manufacturing process of space multiplication, the embodiment can not form a structure similar to a ox horn, and can greatly improve the precise etching of multiple mask layers. The embodiment can realize 3 times of space multiplication, and can realize width adjustment of the gap by controlling the thickness of each mask layer.

Examples

As shown in fig. 20 to 33, the present embodiment provides a method for manufacturing a multiple mask layer, where the method includes:

As shown in fig. 20 to 21, step 1) is first performed, a substrate 201 is provided, a first mask layer 203 is formed on the substrate 201, the first mask layer 203 includes a plurality of imaging mask units 2031, and imaging gaps 204 on the substrate 201 are provided between the imaging mask units 2031.

As shown in fig. 22, step 2) is then performed, and a second mask layer 205 is deposited on the substrate 201, where the second mask layer 205 covers the top surface and the sidewalls of the imaging mask unit 2031 and the bottom of the imaging gap 204, and simultaneously forms a first groove 206 in the imaging gap 204 in a self-aligned manner, and the bottom of the first groove 206 is lower than the top surface of the imaging mask unit 2031.

By controlling the thickness of the second mask layer 205, the second mask layer 205 covers the imaging mask unit 2031 and the imaging gap 204, and simultaneously forms the first groove 206 in the imaging gap 204 in a self-aligned manner.

As shown in fig. 23, step 3) is performed, a third mask layer 207 is deposited on the second mask layer 205, and the third mask layer 207 fills at least the first recess 206, and the third mask layer 207 includes a plurality of first intermediate mask units 301 located in the first recess.

The material of the third mask layer 207 includes one of a group consisting of photoresist, silicon dioxide, silicon nitride, silicon oxynitride and polysilicon. By selecting the material of the third mask layer 207 so that the etching selectivity ratio of the first mask layer 203 to the third mask layer 207 is not less than 10:1, for example, when the first mask layer 203 is selected to be a photoresist, the material of the third mask layer 207 may be selected to be silicon nitride (SiN) or silicon oxynitride (SiON) or polysilicon (Si poly), etc., and in this embodiment, the material of the third mask layer 207 may be selected to be silicon nitride (SiN). The third mask layer 207 may be formed by a vapor deposition process such as sputtering, chemical Vapor Deposition (CVD), and Atomic Layer Deposition (ALD).

As shown in fig. 24, step 4) is performed, where the third mask layer 207 and the second mask layer 205 are thinned until the imaging mask unit 2031 is exposed, and the second mask layer 205 and the third mask layer 207 are exposed, and after the thinning, the second mask layer 205 has a size corresponding to the imaging gap, and the first intermediate mask unit 301 of the third mask layer 207 is separated and embedded in the second mask layer 205.

For example, the third mask layer 207 and the second mask layer 205 may be thinned by a chemical mechanical polishing process or an etching process until the first mask layer 203 is exposed, and the first recess 206 remains the third mask layer 207 after the thinning, because the bottom of the first recess 206 is lower than the top surface of the first mask layer 203.

As shown in fig. 25, step 5) is performed next, and the second mask layer 205 is etched based on the third mask layer 207 to form a first inverse imaging gap 215 on the substrate 201.

The etching selectivity ratio of the second mask layer 205 to the first mask layer 203 is not less than 10:1, and the etching selectivity ratio of the second mask layer 205 to the third mask layer 207 is not less than 10:1. The second mask layer 205 is etched based on the etching selectivity ratio, so that the third mask layer 207 and the first mask layer 203 may remain almost completely after the first anti-imaging gap 215 is formed on the substrate 201, and the second mask layer 205 that is blocked under the third mask layer 207 may also remain.

As shown in fig. 26, step 6) is performed, a fourth mask layer 209 is deposited on the substrate 201, the fourth mask layer 209 covers the first mask layer 203, the third mask layer 207 and the first inverse imaging gap 215, and the fourth mask layer 209 includes a plurality of second intermediate mask units 302 located in the first inverse imaging gap 215.

The material of the fourth mask layer 209 includes one of a group consisting of photoresist, silicon dioxide, silicon nitride, silicon oxynitride and polysilicon. By selecting the material of the fourth mask layer 209 so that the etching selectivity ratio of the first mask layer 203 to the fourth mask layer 209 is not less than 10:1, the etching selectivity ratio of the second mask layer 205 to the fourth mask layer 209 is not less than 10:1, and the etching selectivity ratio of the third mask layer 207 to the fourth mask layer 209 is not less than 10:1, for example, the material of the fourth mask layer 209 may be selected from silicon oxynitride (SiON) or polysilicon (Si poly), etc., and in this embodiment, the material of the fourth mask layer 209 may be selected from silicon oxynitride (SiON). The fourth mask layer 209 may be formed by a vapor deposition process such as sputtering, chemical Vapor Deposition (CVD), and Atomic Layer Deposition (ALD).

As shown in fig. 27, step 7) is performed, where the fourth mask layer 209 is thinned until the first mask layer 203 and the third mask layer 207 are exposed, and the second intermediate mask unit 302 in the first inverse imaging gap 215 is left, wherein the second intermediate mask unit is separated and embedded in the first inverse imaging gap 215, so as to simultaneously expose the first mask layer 203, the third mask layer 207, and the second intermediate mask unit 302.

For example, a chemical mechanical polishing process or an etching process may be used to thin the fourth mask layer 209 until the first mask layer 203 and the third mask layer 207 are exposed, and the fourth mask layer 209 in the first inverse imaging gap 215 is left.

As shown in fig. 28, step 8) is then performed to selectively etch away the first mask layer 203 to form a second inverse imaging gap 217 on the substrate 201.

The etching selectivity ratio of the first mask layer 203 to the fourth mask layer 209 is not less than 10:1, the etching selectivity ratio of the first mask layer 203 to the third mask layer 207 is not less than 10:1, and after the first mask layer 203 is etched to form the second anti-imaging gap 217 on the substrate 201 based on the etching selectivity ratio, the third mask layer 207 and the fourth mask layer 209 may be almost completely preserved, and the second mask layer 205 below the third mask layer 207 and blocked may also be almost completely preserved.

As shown in fig. 29, step 9) is performed, and the third mask layer 207 and the second mask layer 205 are selectively etched to form a third reflective imaging gap 218 on the substrate 201;

The etching selectivity ratio of the second mask layer 205 to the fourth mask layer 209 is not less than 10:1, the etching selectivity ratio of the third mask layer 207 to the fourth mask layer 209 is not less than 10:1, and the third mask layer 207 and the second mask layer 205 are etched based on the etching selectivity ratio, so that the fourth mask layer 209 can be almost completely maintained after forming a third reflective imaging gap 218 on the substrate 201.

As shown in fig. 30, step 10) is performed, and a fifth mask layer 211 is deposited on the substrate 201, wherein the fifth mask layer 211 covers the top surface and the sidewalls of the second intermediate mask unit 302 and the second inverse imaging gap 217 and the third inverse imaging gap 218 to form a second recess 210 in the second inverse imaging gap 217 and a third recess 219 in the third inverse imaging gap 218 in a self-aligned manner, and the bottoms of the second recess 210 and the third recess 219 are lower than the top surface of the second intermediate mask unit 302.

The material of the fifth mask layer 211 includes one of a group consisting of photoresist, silicon dioxide, silicon nitride, silicon oxynitride and polysilicon. By selecting the material of the fifth mask layer 211 so that the etching selectivity ratio of the fifth mask layer 211 to the fourth mask layer 209 is not less than 10:1, for example, the material of the fifth mask layer 211 may be selected from silicon dioxide (SiO ₂), silicon oxynitride (SiON), polysilicon (Si poly), etc., and in this embodiment, the material of the fifth mask layer 211 may be selected from silicon dioxide (SiO ₂). The fifth mask layer 211 may be formed by a vapor deposition process such as sputtering, chemical Vapor Deposition (CVD), and Atomic Layer Deposition (ALD).

By selecting the deposition process and the deposition rate, the cross-sectional shapes of the second recess 210 and the third recess 219 are controlled to be rectangular, so that the precision of the subsequent mask layer manufacturing can be effectively improved.

As shown in fig. 31, step 11) is performed, a sixth mask layer 216 is deposited on the fifth mask layer 211, and the sixth mask layer 216 at least fills the second recess 210 and the third recess 219, wherein the sixth mask layer 216 includes a plurality of third intermediate mask units 304 located in the second recess 210 and a plurality of fourth intermediate mask units 305 located in the third recess 219.

The sixth mask layer 216 is made of one selected from the group consisting of photoresist, silicon dioxide, silicon nitride, silicon oxynitride and polysilicon. By selecting the material of the sixth mask layer 216 so that the etching selection ratio of the fifth mask layer 211 to the sixth mask layer 216 is not less than 10:1, for example, the material of the sixth mask layer 216 may be selected to be photoresist, polysilicon (Si poly) or the like, and in this embodiment, the material of the sixth mask layer 216 may be selected to be polysilicon. The sixth mask layer 216 may be formed by a vapor deposition process such as sputtering, chemical Vapor Deposition (CVD), and Atomic Layer Deposition (ALD).

As shown in fig. 32, step 12) is performed, where the sixth mask layer 216 and the fifth mask layer 211 are thinned until the fourth mask layer 209 is exposed, the second recess 210 retains the third intermediate mask unit 304, and the third recess 219 retains the fourth intermediate mask unit 305, so as to expose the fourth mask layer 209, the fifth mask layer 211, the third intermediate mask unit 304, and the fourth intermediate mask unit 305 at the same time.

Since the bottoms of the second recess 210 and the third recess 219 are lower than the top surface of the fourth mask layer 209, the sixth mask layer 216 and the fifth mask layer 211 are thinned until the third intermediate mask unit 304 is reserved in the second recess 210 and the fourth intermediate mask unit 305 is reserved in the third recess 219 when the fourth mask layer 209 is exposed.

As shown in fig. 33, step 13) is finally performed, the fifth mask layer 211 is etched based on the third intermediate mask unit 304 and the fourth intermediate mask unit 305 to form a first sub-division gap 212 and a second sub-division gap 213 on the substrate 201, wherein the first sub-division gap 212 is located in the second inverse imaging gap 217 and the second sub-division gap 213 is located in the third inverse imaging gap 218.

The etching selectivity ratio of the fifth mask layer 211 to the fourth mask layer 209 is not less than 10:1, the etching selectivity ratio of the fifth mask layer 211 to the sixth mask layer 216 is not less than 10:1, the fourth mask layer 209 and the sixth mask layer 216 can be almost completely preserved after the fifth mask layer 211 is etched based on the sixth mask layer 216 to form the first and second division gaps 212 and 213 on the substrate 201, and the fifth mask layer 211 hidden under the sixth mask layer can also be almost completely preserved.

In the above manufacturing process, the width of the first dividing gap 212 and the width of the second dividing gap 213 are adjusted by controlling the thickness of the fifth mask layer 211 deposited on the sidewall of the fourth mask layer 209, and the finally obtained width of the first dividing gap 212 is equal to the width of the second dividing gap 213.

In the manufacturing process of space multiplication, the embodiment can not form a structure similar to a ox horn, and can greatly improve the precise etching of multiple mask layers. In the embodiment, the multiple mask layers are manufactured by using different lamination configurations of the multiple mask layers and selection of etching rate ratios and based on a self-alignment groove forming method, so that the feature size of the device can be effectively reduced, and the feature density of the device can be increased. The embodiment can realize 4 times of multiplication at equal intervals, and the width adjustment of the gap can be realized by controlling the thickness of each mask layer.

Examples

As shown in fig. 34 to 48, the present embodiment provides a method for manufacturing a multiple mask layer, where the method includes:

As shown in fig. 34 to 35, step 1) is performed first, a substrate 201 is provided, a bottom mask layer 202 is formed on the substrate 201, a first mask layer 203 is formed on the bottom mask layer 202, the first mask layer 203 includes a plurality of imaging mask units 2031, and imaging gaps 204 on the bottom mask layer 202 are provided between the imaging mask units 2031.

As shown in fig. 36, step 2) is then performed, and a second mask layer 205 is deposited on the bottom mask layer 202, where the second mask layer 205 covers the imaging mask unit 2031 and the imaging gap 204, and simultaneously forms a first groove 206 in the imaging gap 204 in a self-aligned manner, and the bottom of the first groove 206 is lower than the top surface of the first mask layer 203.

The material of the second mask layer 205 includes one of a group consisting of photoresist, silicon dioxide, silicon nitride, silicon oxynitride and polysilicon. For example, the material of the second mask layer 205 may be silicon dioxide (SiO ₂). The second mask layer 205 may be formed by a vapor deposition process such as sputtering, chemical Vapor Deposition (CVD), and Atomic Layer Deposition (ALD).

As shown in fig. 37, step 3) is performed, and a third mask layer 207 is deposited on the second mask layer 205, wherein the third mask layer 207 covers the bottom and the sidewalls of the first recess 206 to form a second recess 210 in the first recess 206 in a self-aligned manner.

The material of the third mask layer 207 includes one of a group consisting of photoresist, silicon dioxide, silicon nitride, silicon oxynitride and polysilicon. For example, the material of the third mask layer 207 may be silicon nitride (SiN). The third mask layer 207 may be formed by a vapor deposition process such as sputtering, chemical Vapor Deposition (CVD), and Atomic Layer Deposition (ALD).

As shown in fig. 38, step 4) is performed, a fourth mask layer 209 is deposited on the third mask layer 207, and the fourth mask layer 209 at least fills the second recess 210, and the fourth mask layer 209 includes a plurality of first intermediate mask units 301 located in the second recess 210.

The material of the fourth mask layer 209 includes one of a group consisting of photoresist, silicon dioxide, silicon nitride, silicon oxynitride and polysilicon. By selecting the material of the fourth mask layer 209, the etching selection ratio of the third mask layer 207 to the fourth mask layer is not less than 10:1, and the etching selection ratio of the second mask layer 205 to the fourth mask layer 209 is not less than 10:1. For example, the material of the fourth mask layer 209 may be silicon oxynitride (SiON) or polysilicon (Si poly), and in this embodiment, the material of the fourth mask layer 209 may be silicon oxynitride (SiON). The fourth mask layer 209 may be formed by a vapor deposition process such as sputtering, chemical Vapor Deposition (CVD), and Atomic Layer Deposition (ALD).

As shown in fig. 39, step 5) is performed, where the fourth mask layer 209 is thinned until the third mask layer 207 is exposed, and the second recess 210 retains the first intermediate mask unit 301.

As shown in fig. 40, step 6) is performed next, and the third mask layer 207 is etched based on the first intermediate mask unit 301 to form a first inverse image gap 215 on the second mask layer 205.

The etching selectivity ratio of the third mask layer 207 to the fourth mask layer is not less than 10:1, and the fourth mask layer 209 and the third mask layer 207 hidden under the fourth mask layer 209 may be almost completely preserved after the third mask layer 207 is etched based on the etching selectivity ratio to form the first inverse imaging gap 215 on the second mask layer 205.

As shown in fig. 41, step 7) is then performed to further etch the second mask layer 205 based on the first anti-imaging gap 215 until the bottom mask layer 202 is exposed at the first anti-imaging gap 215, and the second mask layer 205 remains on the sidewalls of the imaging mask unit 2031.

The etching selectivity ratio of the second mask layer 205 to the fourth mask layer 209 is not less than 10:1, and the second mask layer 205 is etched based on the etching selectivity ratio until the fourth mask layer 209 and the third mask layer 207 and the second mask layer 205 below the fourth mask layer 209 are hidden after the bottom mask layer 202 is exposed at the first inverse imaging gap 215 can be almost completely maintained.

Also, since the height of the second mask layer 205 located at the sidewall of the imaging mask unit 2031 is greater than the height of the second mask layer 205 at the remaining position, the sidewall of the imaging mask unit 2031 remains with the second mask layer 205. Meanwhile, the second mask layer 205 is further etched based on the first anti-imaging gap 215 until the second mask layer 205 of the upper surface of the first mask layer 203 is simultaneously removed to expose the first mask layer 203 when the bottom mask layer 202 is exposed at the first anti-imaging gap 215.

As shown in fig. 42, step 8) is then performed to selectively etch to remove the first mask layer 203 to form a second inverse imaging gap 217 on the bottom mask layer 202, the second inverse imaging gap 217 being larger than the first inverse imaging gap 215.

As shown in fig. 43, step 9) is then performed to selectively etch the bottom mask layer 202 to transfer the first inverse imaging gap 215 into the bottom mask layer 202 to form a first division gap 212 and to transfer the second inverse imaging gap 217 into the bottom mask layer 202 to form a third inverse imaging gap 218.

As shown in fig. 44, step 10) is then performed, and the second mask layer 205, the third mask layer 207, and the fourth mask layer 209 are selectively etched to remove.

As shown in fig. 45, step 11) is performed next to depositing a fifth mask layer 211 on the bottom mask layer 202, wherein the fifth mask layer 211 fills the first sub-division gap 212 while forming a third recess 219 in the third sub-division gap 218 in a self-aligned manner, wherein the bottom of the third recess 219 is lower than the top surface of the bottom mask layer 202, based on the third sub-division gap 218 being larger than the first sub-division gap 212.

Since the third reflective gap 218 is larger than the first sub-gap 212, the fifth mask layer 211 may self-align to form a third recess 219 within the third reflective gap 218 while filling the first sub-gap 212. By selecting the deposition process and the deposition rate, the cross-sectional shape of the third groove 219 is controlled to be rectangular, so that the precision of the subsequent mask layer manufacturing can be effectively improved.

As shown in fig. 46, step 12) is performed, a sixth mask layer 216 is deposited on the fifth mask layer 211, the sixth mask layer 216 at least fills the third recess 219, and the sixth mask layer 216 includes a plurality of second intermediate mask units 302 located in the third recess 219.

As shown in fig. 47, step 13) is performed, where the sixth mask layer 216 and the fifth mask layer 211 are thinned until the bottom mask layer 202 is exposed, and the third recess 219 retains the second intermediate mask unit 302, so as to expose the bottom mask layer 202, the fifth mask layer 211 and the second intermediate mask unit 302 at the same time.

Since the bottom of the third groove 219 is lower than the top surface of the bottom mask layer 202, the sixth mask layer 216 and the fifth mask layer 211 are thinned until the bottom mask layer 202 is exposed, and the third groove 219 remains with the second intermediate mask unit 302.

As shown in fig. 48, step 14) is performed next, etching the fifth mask layer 211 in the third reflective gap 218 based on the second intermediate mask unit 302 to form a second division gap 213 on the substrate 201, and simultaneously removing the fifth mask layer 211 in the first division gap 212 to form a first division gap 212 on the substrate 201.

In the above manufacturing process, the width of the first dividing gap 212 may be adjusted by controlling the thickness of the third mask layer 207 at both sides of the second groove 210, and the width of the second dividing gap 213 may be adjusted by controlling the thickness of the fifth mask layer 211 at both sides of the third groove 219.

In the embodiment, the multiple mask layers are manufactured by using different lamination configurations of the multiple mask layers and selection of etching rate ratios and based on a self-alignment groove forming method, so that the feature size of the device can be effectively reduced, and the feature density of the device can be increased. The embodiment can realize 4 times multiplication of unequal intervals, and the width adjustment of the gap can be realized by controlling the thickness of each mask layer. The embodiment can realize gaps with two or more different widths in the same multiple mask layer, and greatly expands the application range of the multiple mask layer.

Examples

As shown in fig. 49, the present embodiment provides a multiple mask layer, including: anti-imaging spacers 402 formed on the substrate 401 at equal intervals, the anti-imaging spacers 402 having anti-imaging gaps 404 therebetween, the anti-imaging spacers 402 having a width less than the minimum exposure development dimension; and a plurality of sub-spacers 403 formed on the substrate 201, wherein each of the plurality of sub-spacers 403 has two spaces therebetween, a first sub-spacer 212 is formed between the plurality of sub-spacers 403 and the plurality of sub-spacers 402, a second sub-spacer 213 is formed between the plurality of sub-spacers 403, and a width of the sub-spacers 403 is smaller than a minimum exposure development dimension.

As an example, the width of the first dividing gap 212 is equal to the width of the second dividing gap 213.

As an example, the width of the anti-imaging spacer 402 is equal to one third of the minimum exposure development dimension, and the width of the double-divided spacer 403 is equal to one third of the minimum exposure development dimension.

The embodiment can realize 3 times of space multiplication of the mask layer with higher precision.

It should be noted that the multiple mask layer in this embodiment may be manufactured by the manufacturing method of the multiple mask layer as described in embodiment 1.

Examples

As shown in fig. 50, the present embodiment provides a multiple mask layer, including: the anti-imaging spacers 502 are formed on the substrate 501 at equal intervals, the first anti-imaging gaps 505 and the second anti-imaging gaps 506 are alternately arranged among the anti-imaging spacers 502, and the width of the anti-imaging spacers 502 is smaller than half of the minimum exposure development size; a first division spacer 503 formed on the substrate 501 in the first anti-imaging gap 505, the first division spacer 503 and the anti-imaging spacer 502 having a first division gap 212 therebetween, the first division spacer 503 having a width less than half of the minimum exposure development dimension; and a second division spacer 504 formed on the substrate 501 in the second anti-imaging gap 506, the second division spacer 504 and the anti-imaging spacer 502 having a second division gap 213 therebetween, the second division spacer 504 having a width less than half of the minimum exposure development dimension.

Preferably, the width of the first dividing gap 212 is equal to the width of the second dividing gap 213.

Preferably, the width of the anti-imaging spacer 502 is equal to one-fourth of the minimum exposure development dimension, and the widths of the first and second sub-spacers 503 and 504 are equal to one-fourth of the minimum exposure development dimension.

The embodiment can realize 4 times equidistant interval multiplication of the mask layer with higher precision.

It should be noted that the multiple mask layer in this embodiment may be manufactured by the manufacturing method of the multiple mask layer as described in embodiment 2.

Examples

As shown in fig. 51, the present invention further provides a multiple mask layer, including: the anti-imaging spacers 602 are formed on the substrate 601, each three anti-imaging spacers 602 are in an anti-imaging spacer group 603, a first double-divided gap 212 is formed between the anti-imaging spacers 602 in the group, an anti-imaging gap 605 is formed between two adjacent anti-imaging gap groups 603, and the width of each anti-imaging spacer 602 is smaller than half of the minimum exposure development size; and a plurality of sub-spacers 604 formed on the substrate 601, wherein each of the sub-spacers 604 is disposed in each of the counter imaging gaps 605, and a second sub-spacer 213 is disposed between each of the sub-spacers 604 and the adjacent counter imaging spacer 602, and the width of each of the sub-spacers 604 is smaller than half of the minimum exposure development dimension.

Preferably, the width of the first dividing gap 212 is not equal to the width of the second dividing gap 213.

Preferably, the width of the anti-imaging spacer 602 is equal to one-fourth of the minimum exposure development dimension, and the width of the multiple-division spacer 604 is equal to one-fourth of the minimum exposure development dimension.

The embodiment can realize 4 times equal spacing or unequal spacing multiplication of the mask layer with higher precision.

It should be noted that the multiple mask layer in this embodiment may be manufactured by the manufacturing method of the multiple mask layer as described in embodiment 3.

3) The invention can realize pitch multiplication of 2 times, 3 times, 4 times or higher, and can realize the width adjustment of the gap by controlling the thickness of each mask layer.

Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.

The above embodiments are merely illustrative of the principles of the present invention and its effectiveness, and are not intended to limit the invention. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the invention. Accordingly, it is intended that all equivalent modifications and variations of the invention be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims

1. The manufacturing method of the multiple mask layer is characterized by comprising the following steps of:

1) Providing a substrate, forming a first mask layer on the substrate, wherein the first mask layer comprises a plurality of imaging mask units, and imaging gaps on the substrate are formed among the imaging mask units;

2) Depositing a second mask layer on the substrate, wherein the second mask layer covers the top surface and the side wall of the imaging mask unit and the bottom of the imaging gap so as to form a first groove in the imaging gap in a self-aligning mode, and the bottom of the first groove is lower than the top surface of the imaging mask unit;

3) Depositing a third mask layer on the second mask layer, wherein the third mask layer at least fills the first grooves, and the third mask layer comprises a plurality of first intermediate mask units positioned in the first grooves;

4) Thinning the third mask layer and the second mask layer until the imaging mask unit is exposed, and exposing the second mask layer and the third mask layer at the same time, wherein the thinned second mask layer has a size corresponding to the imaging gap, and the first intermediate mask unit of the third mask layer is separated and embedded in the second mask layer;

5) Selectively etching to remove the imaging mask unit of the first mask layer to form an anti-imaging gap on the substrate;

6) Depositing a fourth mask layer on the substrate, wherein the fourth mask layer covers the top surface and the side wall of the second mask layer, the top surface of the first intermediate mask unit and the bottom of the reverse imaging gap so as to form a second groove in the reverse imaging gap in a self-aligning mode, and the bottom of the second groove is lower than the top surface of the second mask layer and not higher than the bottom surface of the first intermediate mask unit;

7) Depositing a fifth mask layer on the fourth mask layer, wherein the fifth mask layer at least fills the second grooves, and the fifth mask layer comprises a plurality of second intermediate mask units positioned in the second grooves;

8) Thinning the fifth mask layer and the fourth mask layer until the second mask layer is exposed, and exposing the first intermediate mask unit, the fourth mask layer and the fifth mask layer at the same time, wherein the thinned fourth mask layer has a size corresponding to the reverse imaging gap, and the second intermediate mask unit of the fifth mask layer is separated and embedded in the fourth mask layer;

9) Patterning and etching the second mask layer based on the first intermediate mask unit of the third mask layer to form a first division gap in the imaging gap on the substrate, wherein one side of the first division gap comprises a side wall of the first intermediate mask unit, and the other side of the first division gap comprises a side wall of the fourth mask layer after thinning;

10 Selectively etching to remove the second intermediate mask unit of the fifth mask layer in the second recess; and

11 Self-aligned etching of the fourth mask layer based on the second recess until the substrate is exposed at the second recess such that the fourth mask layer is formed with a division-multiple spacer on the substrate and in the inverse imaging gap with a second division-multiple gap therebetween.

2. The method for manufacturing the multiple mask layer according to claim 1, wherein: step 1) further comprises the step of performing mask trimming on the imaging mask unit to reduce the width of the imaging mask unit.

3. The method for manufacturing the multiple mask layer according to claim 2, wherein: the mask trimming method comprises one or two of isotropic dry etching and anisotropic wet etching.

4. The method for manufacturing the multiple mask layer according to claim 1, wherein: in the step 5), the etching selection ratio of the first mask layer to the second mask layer is not less than 10:1, and the etching selection ratio of the first mask layer to the third mask layer is not less than 10:1.

5. The method for manufacturing the multiple mask layer according to claim 1, wherein: in the step 9), the etching selection ratio of the second mask layer to the third mask layer is not less than 10:1, the etching selection ratio of the second mask layer to the fourth mask layer is not less than 10:1, and the etching selection ratio of the second mask layer to the fifth mask layer is not less than 10:1.

6. The method for manufacturing the multiple mask layer according to claim 1, wherein: in step 10), the etching selection ratio of the fifth mask layer to the third mask layer is not less than 10:1, and the etching selection ratio of the fifth mask layer to the fourth mask layer is not less than 10:1.

7. The method for manufacturing the multiple mask layer according to claim 1, wherein: the material of the first mask layer comprises one of the group consisting of photoresist, silicon dioxide, silicon nitride, silicon oxynitride and polysilicon; the material of the second mask layer comprises one of the group consisting of photoresist, silicon dioxide, silicon nitride, silicon oxynitride and polysilicon; the material of the third mask layer comprises one of the group consisting of photoresist, silicon dioxide, silicon nitride, silicon oxynitride and polysilicon; the material of the fourth mask layer comprises one of the group consisting of photoresist, silicon dioxide, silicon nitride, silicon oxynitride and polysilicon; the fifth mask layer is made of one of photoresist, silicon dioxide, silicon nitride, silicon oxynitride and polysilicon.

8. The method for manufacturing the multiple mask layer according to claim 1, wherein: and step 12), etching to remove the third mask layer to form a plurality of mask layers of the first division gap and the fourth division spacer, wherein the first division gap and the fourth mask layer are contained in the imaging gap and are separated by the second mask layer, and the division spacers are arranged on the sides of the anti-imaging gap.

9. The method for manufacturing a multiple mask layer according to any one of claims 1 to 8, wherein: the width of the second division gap is adjusted by controlling the thickness of the second mask layer deposited on the side wall of the imaging mask unit, and the width of the second division gap is adjusted by controlling the width of the second groove.

10. The method for manufacturing the multiple mask layer according to claim 9, wherein: and controlling the thickness of the second mask layer to be equal to the width of the second groove so that the width of the first time division gap is equal to the width of the second time division gap.

11. The manufacturing method of the multiple mask layer is characterized by comprising the following steps of:

5) Etching the second mask layer based on the third mask layer to form a first inverse imaging gap on the substrate;

6) Depositing a fourth mask layer on the substrate, wherein the fourth mask layer covers the first mask layer, the third mask layer and the first reverse imaging gap, and the fourth mask layer comprises a plurality of second intermediate mask units positioned in the first reverse imaging gap;

7) Thinning the fourth mask layer until the first mask layer and the third mask layer are exposed, and reserving the second intermediate mask units in the first inverse imaging gaps, wherein the second intermediate mask units are separated and embedded in the first inverse imaging gaps so as to simultaneously expose the first mask layer, the third mask layer and the second intermediate mask units;

8) Selectively etching to remove the first mask layer to form a second inverse imaging gap on the substrate;

9) Selectively etching to remove the third mask layer and the second mask layer to form a third reflective imaging gap on the substrate;

10 Depositing a fifth mask layer on the substrate, wherein the fifth mask layer covers the top surface and the side wall of the second intermediate mask unit, the bottom of the second inverse imaging gap and the bottom of the third inverse imaging gap to form a second groove in the second inverse imaging gap in a self-aligned manner and form a third groove in the third inverse imaging gap in a self-aligned manner, and the bottoms of the second groove and the third groove are lower than the top surface of the second intermediate mask unit;

11 Depositing a sixth mask layer on the fifth mask layer, wherein the sixth mask layer at least fills the second groove and the third groove, and the sixth mask layer comprises a plurality of third intermediate mask units positioned in the second groove and a plurality of fourth intermediate mask units positioned in the third groove;

12 Thinning the sixth mask layer and the fifth mask layer until the fourth mask layer is exposed, wherein the second groove reserves the third intermediate mask unit, and the third groove reserves the fourth intermediate mask unit so as to simultaneously expose the fourth mask layer, the fifth mask layer, the third intermediate mask unit and the fourth intermediate mask unit; and

13 The fifth mask layer is etched based on the third intermediate mask unit and the fourth intermediate mask unit to form a first division gap and a second division gap on the substrate, wherein the first division gap is located in the second inverse imaging gap, and the second division gap is located in the third inverse imaging gap.

12. The method for manufacturing the multiple mask layer according to claim 11, wherein: step 1) further comprises the step of performing mask trimming on the imaging mask unit to reduce the width of the imaging mask unit.

13. The method for manufacturing the multiple mask layer according to claim 12, wherein: the mask trimming method comprises one or two of isotropic dry etching and anisotropic wet etching.

14. The method for manufacturing the multiple mask layer according to claim 11, wherein: in the step 5), the etching selection ratio of the second mask layer to the first mask layer is not less than 10:1, and the etching selection ratio of the second mask layer to the third mask layer is not less than 10:1.

15. The method for manufacturing the multiple mask layer according to claim 11, wherein: in step 8), the etching selectivity ratio of the first mask layer to the fourth mask layer is not less than 10:1, and in step 9), the etching selectivity ratio of the second mask layer to the fourth mask layer is not less than 10:1, and the etching selectivity ratio of the third mask layer to the fourth mask layer is not less than 10:1.

16. The method for manufacturing the multiple mask layer according to claim 11, wherein: in step 13), the etching selectivity ratio of the fifth mask layer to the fourth mask layer is not less than 10:1, and the etching selectivity ratio of the fifth mask layer to the sixth mask layer is not less than 10:1.

17. The method for manufacturing the multiple mask layer according to claim 11, wherein: the material of the first mask layer comprises one of the group consisting of photoresist, silicon dioxide, silicon nitride, silicon oxynitride and polysilicon; the material of the second mask layer comprises one of the group consisting of photoresist, silicon dioxide, silicon nitride, silicon oxynitride and polysilicon; the material of the third mask layer comprises one of the group consisting of photoresist, silicon dioxide, silicon nitride, silicon oxynitride and polysilicon; the material of the fourth mask layer comprises one of the group consisting of photoresist, silicon dioxide, silicon nitride, silicon oxynitride and polysilicon; the fifth mask layer is made of one of photoresist, silicon dioxide, silicon nitride, silicon oxynitride and polysilicon; the sixth mask layer is made of one of photoresist, silicon dioxide, silicon nitride, silicon oxynitride and polysilicon.

18. The method for manufacturing a multiple mask layer according to any one of claims 11 to 17, wherein: and adjusting the width of the first division gap and the width of the second division gap by controlling the thickness of the fifth mask layer deposited on the side wall of the fourth mask layer.

19. The method for fabricating a multiple mask layer according to claim 18, wherein: the width of the first dividing gap is equal to that of the second dividing gap.

20. The manufacturing method of the multiple mask layer is characterized by comprising the following steps of:

1) Providing a substrate, forming a bottom mask layer on the substrate, and forming a first mask layer on the bottom mask layer, wherein the first mask layer comprises a plurality of imaging mask units, and imaging gaps on the bottom mask layer are formed between the imaging mask units;

2) Depositing a second mask layer on the bottom mask layer, wherein the second mask layer covers the top surface and the side wall of the imaging mask unit and the bottom of the imaging gap, and simultaneously, a first groove is formed in the imaging gap in a self-aligning manner, and the bottom of the first groove is lower than the top surface of the imaging mask unit;

3) Depositing a third mask layer on the second mask layer, wherein the third mask layer covers the bottom and the side wall of the first groove so as to form a second groove in the first groove in a self-aligned manner;

4) Depositing a fourth mask layer on the third mask layer, wherein the fourth mask layer at least fills the second grooves, and the fourth mask layer comprises a plurality of first intermediate mask units positioned in the second grooves;

5) Thinning the fourth mask layer until the third mask layer is exposed, wherein the first intermediate mask unit is reserved in the second groove;

6) Etching the third mask layer based on the first intermediate mask unit to form a first inverse imaging gap on the second mask layer;

7) Further etching the second mask layer based on the first anti-imaging gap until the bottom mask layer is exposed at the first anti-imaging gap, wherein the second mask layer is reserved on the side wall of the imaging mask unit;

8) Selectively etching to remove the first mask layer to form a second anti-imaging gap on the bottom mask layer, the second anti-imaging gap being larger than the first anti-imaging gap;

9) Selectively etching the bottom mask layer to transfer the first inverse imaging gap into the bottom mask layer to form a first division gap and transfer the second inverse imaging gap into the bottom mask layer to form a third inverse imaging gap;

10 Selectively etching to remove the second mask layer, the third mask layer and the fourth mask layer;

11 Depositing a fifth mask layer on the bottom mask layer, wherein a third groove is formed in the third inverse imaging gap in a self-alignment manner while the fifth mask layer fills the first inverse imaging gap based on the third inverse imaging gap being larger than the first inverse imaging gap, and the bottom of the third groove is lower than the top surface of the bottom mask layer;

12 Depositing a sixth mask layer on the fifth mask layer, wherein the sixth mask layer at least fills the third groove, and the sixth mask layer comprises a plurality of second intermediate mask units positioned in the third groove;

13 Thinning the sixth mask layer and the fifth mask layer until the bottom mask layer is exposed, wherein the third groove is reserved with the second intermediate mask unit so as to simultaneously expose the bottom mask layer, the fifth mask layer and the second intermediate mask unit; and

14 Etching the fifth mask layer in the third reflective gap based on the second intermediate mask unit to form a second division gap on the substrate while removing the fifth mask layer in the first division gap to form a first division gap on the substrate.

21. The method for fabricating a multiple mask layer according to claim 20, wherein: step 1) further comprises the step of performing mask trimming on the imaging mask unit to reduce the width of the imaging mask unit.

22. The method for fabricating a multiple mask layer according to claim 21, wherein: the mask trimming method comprises one or two of isotropic dry etching and anisotropic wet etching.

23. The method for fabricating a multiple mask layer according to claim 20, wherein: in step 7), the second mask layer is further etched based on the first anti-imaging gap until the second mask layer on the upper surface of the first mask layer is simultaneously removed to expose the first mask layer when the bottom mask layer is exposed at the first anti-imaging gap.

24. The method for fabricating a multiple mask layer according to claim 20, wherein: in step 6), the etching selection ratio of the third mask layer to the fourth mask layer is not less than 10:1, and in step 7), the etching selection ratio of the second mask layer to the fourth mask layer is not less than 10:1.

25. The method for fabricating a multiple mask layer according to claim 20, wherein: the material of the first mask layer comprises one of the group consisting of photoresist, silicon dioxide, silicon nitride, silicon oxynitride and polysilicon; the material of the second mask layer comprises one of the group consisting of photoresist, silicon dioxide, silicon nitride, silicon oxynitride and polysilicon; the material of the third mask layer comprises one of the group consisting of photoresist, silicon dioxide, silicon nitride, silicon oxynitride and polysilicon; the material of the fourth mask layer comprises one of the group consisting of photoresist, silicon dioxide, silicon nitride, silicon oxynitride and polysilicon; the fifth mask layer is made of one of photoresist, silicon dioxide, silicon nitride, silicon oxynitride and polysilicon; the sixth mask layer is made of one of photoresist, silicon dioxide, silicon nitride, silicon oxynitride and polysilicon.

26. The method for manufacturing a multiple mask layer according to any one of claims 20 to 25, wherein: and adjusting the width of the first division gap by controlling the thickness of the third mask layer at two sides of the second groove.

27. The method for manufacturing a multiple mask layer according to any one of claims 20 to 25, wherein: and adjusting the width of the second dividing gap by controlling the thickness of the fifth mask layer at two sides of the third groove.