CN110572343A - Receiving and transmitting control method for multi-path diversity signals - Google Patents
Receiving and transmitting control method for multi-path diversity signals Download PDFInfo
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- CN110572343A CN110572343A CN201910674683.1A CN201910674683A CN110572343A CN 110572343 A CN110572343 A CN 110572343A CN 201910674683 A CN201910674683 A CN 201910674683A CN 110572343 A CN110572343 A CN 110572343A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/0014—Carrier regulation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/26—Systems using multi-frequency codes
- H04L27/2601—Multicarrier modulation systems
- H04L27/2647—Arrangements specific to the receiver only
- H04L27/2655—Synchronisation arrangements
- H04L27/2656—Frame synchronisation, e.g. packet synchronisation, time division duplex [TDD] switching point detection or subframe synchronisation
Abstract
the invention discloses a receiving and transmitting control method of multipath diversity signals, which initializes a DSP hardware platform; automatic hardware identification and automatic software configuration are carried out by using a plug and play algorithm; separating the received multipath sampling signals; processing the sampled multiple paths of signals respectively, and taking out one path of signals to modulate with carriers of different carrier frequencies to obtain frequency diversity signals; finding out a frame synchronization signal of a main AD/DA chip by using a polling mode of a multi-channel buffer serial port; loading a signal to be sent in a sending interrupt service subprogram; and judging whether the whole communication process is finished or not.
Description
Technical Field
The invention belongs to the technical field of multi-path signal control, and particularly relates to a receiving and transmitting control method of multi-path diversity signals.
background
short-wave communication usually carries out long-distance communication by means of reflection of an ionized layer, and signals usually received by a receiving end have fluctuation due to rapid change of the ionized layer and existence of multipath effect in a signal transmission process, so that signal fading is caused. Diversity techniques are well able to combat this multipath fading.
Diversity techniques can be classified into space diversity, time diversity, and frequency diversity. The frequency diversity means that a path of signal to be transmitted is modulated by carriers of different carrier frequencies and then is transmitted by different transmitters, a receiving end receives the signal by different receivers, and the condition that the receiving end obtains a plurality of paths of signals irrelevant to fading characteristics is that the interval between the carrier frequencies is larger than the coherent bandwidth. The more the diversity is not independent, the better, and practice proves that when the number of the receiving independent branches is more than 4, the diversity combining effect is not obvious. Compared with a single branch, the effect of the multiple branches is obviously improved, and therefore the number of the obtained independent branches is usually 2-4.
one conventional method for obtaining signals of multiple independent branches is: based on the cascade mode of a digital-analog/analog-digital chip TLV320AIC10 (Aic 10 for short), a plurality of (at most eight) Aic10 are cascaded, data communication is realized with a Digital Signal Processor (DSP) through a peripheral module multi-channel buffer serial port (McBSP 0 for short) of the DSP, the data receiving and sending are started at the falling edge of a frame synchronization signal, and when the rising edge of a shift clock comes, each bit of data is transmitted corresponding to one shift clock. Of the multiple cascaded Aic10, only one is the master Aic10, and the others are the slave aics 10. When data is sampled, the data bit width sampled in the default condition is 15+1bit format, the upper 15 bits are effective data bits, the lowest bit is a flag bit, the data sampled by the main Aic10 is 1, the data sampled by the Aic10 is 0, and the lowest bit is 0.
At present, the control of multiple signals by using an Aic10 cascade scheme proposed by researchers at home and abroad does not explicitly provide a method for controlling one or more signals in multiple (more than two) signals to be received and sent simultaneously according to needs. A paper entitled "design and implementation of serial communication between a multichannel audio analog interface chip TLV320AIC10 and a DSP" was published in journal "electronic product world" in 2002, shaohua, chenjian, foufenglin, 9 months, and a method was proposed in the paper: three Aic10 are cascaded, and communication with a DSP5402 is realized through a McBSP0 of a TMS320VC5402, wherein a master Aic10 is used as a master control to provide a signal receiving shift clock CLKR, a signal sending shift clock CLKX, a signal receiving frame synchronization signal FSR and a signal sending frame synchronization signal FSX for data transmission of the McBSP0 of other two slave Aic10 and the DSP5402, and a multi-serial-port interrupt source implementation scheme is adopted during signal transceiving control. A paper entitled "design of a multichannel signal interface of TLV320AIC10 and TMS320VC 5402" is published on journal "electronic design application" in 11/2003, and the method for receiving three sampling signals by using DMA ping-pong buffer technology is provided, wherein the size of a ping-pong buffer area is set to be 90, the first third buffer area stores the received data of a channel I, the middle third buffer area stores the received data of a channel II, the last third buffer area stores the received data of a channel III, the source address is not changed, the destination address is increased by 30 after receiving one data every time, and is decreased by 59 after receiving one frame every time, an interrupt is generated after the completion of the movement of one block, informing the DSP to process the data, in such a manner that, although the multi-sampled signal is separated, while avoiding the need to use the CPU frequently when register move data is received from McBSP0, it is not possible to determine whether the signal split in the buffer is from master Aic10 or slave Aic 10.
After Aic10 is powered on, frame synchronization signal FS will continue to be generated in a master-multiple-slave mode regardless of whether there is a receive or transmit signal, and Aic10 shows frame synchronization signal FS in FIG. 4. The above two methods for controlling transmission and reception of a plurality of signals can be used for receiving the same plurality of signals, and have a problem that a reception link is disturbed when receiving different plurality of signals. Here, link scrambling means that the order of sampling data by the plurality of aics 10 in the cascade mode is to start sampling from the main Aic10 and then sequentially sample other slave aics 10, but the McBSP0 does not turn on the received data immediately after the DSP system is powered on, but turns on the received data only when the sampled data is to be received after the initialization of the entire DSP system is completed, and when the McBSP0 is turned on to receive data, the received frame synchronization signal of the McBSP0 is not necessarily the received frame synchronization signal corresponding to the main Aic10, but may correspond to the received frame synchronization signal of one of the slave aics 10, that is, the order of receiving the sampled data by the McBSP0 is not necessarily the order of receiving the sampled data by the main Aic10 first and then sequentially receiving the sampled data by the slave Aic10, or may start receiving the sampled data by one of the slave Aic 10. Thus, when only one or a plurality of specific Aic10 samples a desired signal, it is difficult to determine where the desired sampled signal is received, i.e., to separate the desired signal from unwanted signals. In addition, in the above two methods, when the McBSP0 transmits a digital signal, it is impossible to determine that the signal is transmitted from the main Aic10, that is, there is a problem that the transmission link is disturbed.
disclosure of Invention
in view of the above, the main objective of the present invention is to provide a method for controlling the transmission and reception of multiple paths of diversity signals
In order to achieve the purpose, the technical scheme of the invention is realized as follows:
The embodiment of the invention provides a receiving and transmitting control method of a multipath diversity signal, which comprises the following steps:
Configuring an enhanced direct memory access controller of the DSP chip into a ping-pong mode;
the method comprises the steps that automatic cascade detection is carried out on the connection of a DSP chip and a plurality of AD/DA chips through a plug-and-play algorithm, and four control registers of each AD/DA chip are automatically configured;
The DSP chip separates the received multi-path sampling signals and modulates the separated signals respectively to obtain frequency diversity signals;
and searching a frame synchronization signal FS of the main AD/DA chip in a polling mode, and loading a frequency diversity signal to be sent and sending the frequency diversity signal through the corresponding AD/DA chip in the next communication period.
In the foregoing solution, the configuring the data transfer module enhanced dma controller of the DSP to the ping-pong mode specifically includes: when the multi-channel sampling signals are moved from the receiving end of the multi-channel buffer serial port 0, the source address is set as the address of the data receiving register of the multi-channel buffer serial port 0, the destination address of the received table parameter set is set as the address of the table buffer area, the size of the received table buffer area and the size of the received table buffer area are set to be multiple times of the number of the AD/DA chips, when the data to be sent are moved to the sending end of the multi-channel buffer serial port 0, the destination address is set as the address of the data sending register of the multi-channel buffer serial port 0, the source address of the sent table parameter set is set as the address of the sent table buffer area, and the size of the sent table buffer area is set as the number of the.
In the above scheme, the automatic cascade detection of the connection between the DSP chip and the plurality of AD/DA chips by the plug and play algorithm specifically includes: detecting whether a master AD/DA chip exists in a plurality of cascaded AD/DA chips by checking that the lowest bit of 16-bit data received by a data receiving register is 1, if not, detecting that the automatic cascade detection of the plurality of AD/DA chips fails, if the master AD/DA chip is detected, continuously detecting whether more than two master AD/DA chips exist according to the number of the lowest bits of the plurality of received 16-bit data which is 1, if so, detecting that the automatic cascade detection of the plurality of AD/DA chips fails, if not, determining the number of cascaded slave AD/DA chips according to the number of the lowest bits of the plurality of received 16-bit data which is 0, judging whether the total number of the master AD/DA chips and the slave AD/DA chips is more than eight, if so, detecting that the automatic cascade detection of the plurality of AD/DA chips fails, if not, the automatic cascade detection of several AD/DA chips passes.
In the above scheme, the DSP chip separates the received multiple sampling signals, specifically:
After the interruption of the receiving, determining a main AD/DA chip according to the first N receiving data in the receiving ping buffer area, and determining the sequence of storing N paths of sampling signals in the receiving ping buffer area according to the main AD/DA chip; n is the total number of AD/DA chips;
And when the next receiving interruption comes, separating the N paths of sampling signals in the receiving pong buffer area.
In the foregoing solution, the main AD/DA chip is determined according to the first N pieces of received data in the receiving ping buffer, specifically, the received data with the lowest bit of 1 in the first N pieces of received data is sequentially judged in the receiving ping buffer, and the AD/DA chip corresponding to the received data is the main AD/DA chip.
In the above scheme, the determining the sequence of storing N sampling signals in the receiving ping buffer includes:
and taking out and placing the received data corresponding to the master AD/DA chip into a first receiving bucket, and then sequentially taking out and placing the received data corresponding to a plurality of slave AD/DA chips into the rest receiving buckets in sequence.
In the foregoing scheme, the modulating the separated signals respectively to obtain frequency diversity signals specifically includes: and modulating the N paths of separated signals by 2-4 carrier waves with different carrier frequencies respectively to obtain frequency diversity signals.
in the above scheme, the loading of the frequency diversity signal to be transmitted in the next communication cycle and the transmission of the frequency diversity signal by the corresponding AD/DA chip specifically include: the method comprises the steps of searching a main AD/DA chip in a polling mode, loading a frequency diversity signal to be sent corresponding to the main AD/DA chip to a first sending barrel of a ping-pong buffer area, sequentially loading a plurality of frequency diversity signals to be sent corresponding to slave AD/DA chips to the first sending barrel of the ping-pong buffer area in sequence, sequentially loading the frequency diversity signals to be sent corresponding to the slave AD/DA chips to the remaining sending barrels, and sequentially sending the frequency diversity signals according to the sequence of the sending barrels.
Compared with the prior art, when receiving the multi-channel sampling signals, the receiving mode of the McBSP0 is configured to be an EDMA ping-pong mode, and the multi-channel signals are orderly separated according to the lowest flag bit of the received 16-bit data after the receiving is interrupted, so that on one hand, the CPU is frequently used when receiving the data, and on the other hand, the link is prevented from being disordered when receiving the data;
When the multi-path diversity signal is transmitted, the McBSP0 transmission mode is configured to be an EDMA ping-pong mode, the sizes of ping and pong buffers are both set to be the number of cascaded Aic10, before the multi-path signal is transmitted, the McBSP0 polling mode is used for finding out the frame synchronization signal FS of the main Aic10, then the multi-path signal to be transmitted or some signals in the multi-path signal are sequentially selected to be transmitted by the main AD/DA chip or the AD/DA chip after the transmission interruption, and only then, the multi-path signal can be ensured to be transmitted from the main AD/DA chip, so that the transmission link is not disordered.
Drawings
Fig. 1 is a flowchart of a method for controlling transmission and reception of multiple diversity signals according to an embodiment of the present invention;
Fig. 2 is a block diagram of a short wave integrated services communication system used in the present invention;
FIG. 3 is a flow chart of an implementation of the present invention;
FIG. 4 is a timing diagram of a frame signal FS in the Aic10 cascade mode;
FIG. 5 is a diagram of four sample data stored in the receive ping buffer;
FIG. 6 is a waveform diagram of the four sample data after separation plotted with CCS;
FIG. 7 is a waveform diagram of a sine wave applied to only the master Aic10 and slave Aic10 plotted in CCS;
FIG. 8 is a waveform diagram of four Aic10 sending sine wave signals simultaneously;
figure 9 is a waveform diagram of main Aic10 and the other two Aic10 sending triangular waves sending sine waves from one Aic 10;
fig. 10 is a waveform diagram of a master Aic10 and two other aics 10 sending characters 0x0 sending sine waves from one Aic 10.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
an embodiment of the present invention provides a method for controlling transceiving of a multi-path diversity signal, as shown in fig. 1, the method includes:
step 101: configuring an enhanced direct memory access controller of the DSP chip into a ping-pong mode;
specifically, when the multi-channel sampling signal is moved from the receiving end of the multi-channel buffer serial port 0, the source address is set as the address of the data receiving register of the multi-channel buffer serial port 0, the destination address of the received ping parameter set is set as the address of the ping buffer area, the destination address of the received pong parameter set is set as the address of the pong buffer area, the size of the received ping buffer area and the pong buffer area is set as the multiple of the number of the AD/DA chips, when the data to be sent is moved to the sending end of the multi-channel buffer serial port 0, the destination address is set as the address of the data sending register of the multi-channel buffer serial port 0, the source address of the sent ping parameter set is set as the address of the sent ping buffer area, and the size of the sent ping buffer area is set as the number of the AD/DA chips.
Step 102: the method comprises the steps that automatic cascade detection is carried out on the connection of a DSP chip and a plurality of AD/DA chips through a plug-and-play algorithm, and four control registers of each AD/DA chip are automatically configured;
specifically, whether a master AD/DA chip exists in a plurality of cascaded AD/DA chips is detected by checking that the lowest bit of 16-bit data received by a data receiving register is 1, if not, the automatic cascade detection of the plurality of AD/DA chips is failed, if the master AD/DA chip is detected, whether more than two master AD/DA chips exist is continuously detected according to the number of the lowest bits of the plurality of 16-bit data received as 1, if so, the automatic cascade detection of the plurality of AD/DA chips is failed, if not, the number of cascaded slave AD/DA chips is determined according to the number of the lowest bits of the plurality of 16-bit data received as 0, whether the total number of the master AD/DA chips and the slave AD/DA chips is more than eight is judged, if so, the automatic cascade detection of the plurality of AD/DA chips is failed, if not, the automatic cascade detection of a plurality of AD/DA chips passes.
step 103: the DSP chip separates the received multi-path sampling signals and modulates the separated signals respectively to obtain frequency diversity signals;
Specifically, after the reception interruption, determining a main AD/DA chip according to the first N received data in the reception ping buffer, and determining the sequence of storing N paths of sampling signals in the reception ping buffer according to the main AD/DA chip; n is the total number of AD/DA chips;
and when the next receiving interruption comes, separating the N paths of sampling signals in the receiving pong buffer area.
And taking out and placing the received data corresponding to the master AD/DA chip into a first receiving bucket, and then sequentially taking out and placing the received data corresponding to a plurality of slave AD/DA chips into the rest receiving buckets in sequence.
and modulating the N paths of separated signals by 2-4 carrier waves with different carrier frequencies respectively to obtain frequency diversity signals.
step 104: and searching a frame synchronization signal FS of the main AD/DA chip in a polling mode, and loading a frequency diversity signal to be sent and sending the frequency diversity signal through the corresponding AD/DA chip in the next communication period.
specifically, the received data with the lowest bit of 1 in the first N received data is sequentially judged in the reception ping buffer, and the AD/DA chip corresponding to the received data is the main AD/DA chip.
and loading the frequency diversity signals to be sent corresponding to the master AD/DA chip to a first sending bucket of the ping-pong buffer area, sequentially loading a plurality of frequency diversity signals to be sent corresponding to the slave AD/DA chips to the remaining sending buckets of the ping-pong buffer area in sequence, and then sequentially sending the frequency diversity signals according to the sequence of the sending buckets.
Taking the application of the invention in a short wave integrated service communication system as an example, the short wave integrated service communication system comprises a short wave radio station, four Aic10, a DSP6455 chip, an FPGA chip, a FLASH, an SBSRAM and an upper computer. The DSP6455 chip is a TI6000 series high-performance fixed-point DSP, has the advantages of large-capacity storage space and rapid data processing capacity, is used for signal processing, and a module McBSP0 of the DSP6455 chip is used for data interaction with Aic 10; the FPGA is used for realizing an asynchronous serial port of the DSP6455 chip, so that the DSP6455 chip can perform data transmission with an upper computer; in addition, the FPGA is also used for the receiving end to decode, balance, combine and the like the multipath signals; the FLASH is used for programming the storage program; SBSRAM is used as external memory; the four Aic10 are used for realizing analog-digital/digital-analog conversion of data transmitted between the DSP6455 and the short-wave radio station.
the embodiment of the invention provides another multipath diversity signal receiving and transmitting control method, which is realized by the following steps:
step (1): initializing internal function modules of the DSP chip:
specifically, (1a) configuring a phase-locked loop controller of the DSP chip to provide clocks for other internal modules;
(1b) closing the global interrupt of the CPU, closing all the CPUs to shield the interrupt, and clearing all interrupt flag bits;
(1c) Configuring an internal module external memory interface, a multi-channel buffer serial port 0 and a universal input/output interface of the DSP;
(1d) the enhanced direct memory access controller of the data moving module of the DSP is configured to be in a ping-pong mode, when a plurality of sampling signals are moved from the receiving end of the multi-channel buffer serial port 0, the source address is set as the address of the data receiving register of the multichannel buffer serial port 0, the destination address of the table-tennis parameter set is set as the address of the table-tennis buffer area, the destination address of the pong parameter set is set as the address of the pong buffer area, the size of the table-tennis and pong buffer areas is set as the multiple of the number of the AD/DA chips, when the data to be transmitted is moved to the transmitting end of the multichannel buffer serial port 0, the destination address is set as the address of a data sending register of the multichannel buffer serial port 0, the source address of the table-tennis parameter set is set as the address of the table-tennis buffer area, the source address of the pong parameter set is set as the address of the pong buffer area, and the size of the ping buffer area and the pong buffer area is set as the number of the AD/DA chips.
step (2): the connection between the AD/DA chip and the DSP chip is automatically cascade-connected and detected through a plug-and-play algorithm, and four control registers of the AD/DA chip are automatically configured:
specifically, (2a) the AD/DA chip is reset by the high-low level output from the general input/output pin 15;
(2b) Opening a multi-channel buffer serial port by setting a control bit of a serial port control register to receive sampling data;
(2c) Detecting whether a master AD/DA chip exists in a plurality of cascaded AD/DA chips by checking that the lowest bit of 16-bit data received by a data receiving register is 1, if not, detecting that automatic cascade detection of a plurality of AD/DA chips fails, if the master AD/DA chip is detected, continuously detecting whether more than two master AD/DA chips exist according to the number of the lowest bit of the plurality of 16-bit data received as 1, if so, detecting that the automatic cascade detection of the plurality of AD/DA chips fails, if not, determining the number of cascaded slave AD/DA chips according to the number of the lowest bit of the plurality of 16-bit data received as 0, judging whether the total number of the master AD/DA chips and the slave AD/DA chips is more than eight, if so, detecting that the automatic cascade detection of the plurality of AD/DA chips fails, if not, the AD/DA chip cascade detection is passed;
(2d) opening a multi-channel buffer serial port to send data by setting a control bit of a serial port control register;
(2e) Four complete communication cycles are needed for configuring four control registers of the AD/DA chip, each communication cycle is that primary communication sends four secondary communication requests, secondary communication sends control words, and the sampling rate of the AD/DA chip is set to be 9.6 k;
(2f) the control bit of the serial port control register is set to close the multichannel buffering serial port to send data and close the receiving data;
step (3) opening a multichannel buffer serial port 0 to receive data and enabling thirteen events of the enhanced direct memory access controller;
and (4): separating the received multi-path sampling signals in a receiving interrupt service subprogram:
specifically, (4a) clearing a flag bit of an enhanced direct memory access controller that receives an interrupt trigger event;
(4b) setting initial values of write pointers Rxd0, Rxd1, Rxd2 and Rxd3 of the four receiving buckets to 0;
(4c) judging whether the lowest bit of 16-bit data r _ ping [0] in a receiving ping buffer short _ ping [192] is 1 or not, if not, jumping to a step (4d), if so, sequentially taking out the sampled data in the r _ ping [192] and putting the sampled data into a receiving bucket short mhibt0[0x2000], mhibt1[0x2000], mhibt2[0x2000], and mhibt3[0x2000], adding one to each write pointer of four receiving buckets when putting a group of data, judging whether the write pointers Rxd0, Rxd1, Rxd2 and Rxd3 are all larger than or equal to 0x2000 after 192 data are taken out, and if so, setting the four write pointers to be 0;
(4d) Judging whether the lowest bit of 16-bit data r _ ping [1] in a receiving ping buffer short _ ping [192] is 1 or not, if not, jumping to a step (4e), if so, sequentially taking out and putting the sampled data in the r _ ping [192] into a receiving bucket short mhibt3[192], mhibt0[192], mhibt1[192] and mhibt2[192], adding one to the write pointers of four receiving buckets respectively after 192 data are taken out, judging whether the write pointers Rxd0, Rxd1, Rxd2 and Rxd3 are all larger than or equal to 0x2000 or not, and if so, setting the four write pointers to 0;
(4e) Judging whether the lowest bit of 16-bit data r _ ping [2] in a receiving ping buffer short _ ping [192] is 1 or not, if not, jumping to a step (4f), if so, sequentially taking out the sampled data in the r _ ping [192] and putting the sampled data into receiving buckets short mhibt2[192], mhibt3[192], mhibt0[192] and mhibt1[192], adding one to the write pointers of four receiving buckets respectively after completing 192 data, judging whether the write pointers Rxd0, Rxd1, Rxd2 and Rxd3 are all larger than or equal to 0x2000 or not, and if so, setting the four write pointers to 0;
(4f) sequentially taking out the sampled data in the r _ ping [192] and placing the sampled data into short mmhibt1[182], mmhibt2[192], mmhibt3[192] and mmhibt0[192], adding one to each write pointer of four receiving buckets when placing a group of data, judging whether the write pointers Rxd0, Rxd1, Rxd2 and Rxd3 are all more than or equal to 0x2000 after 192 data are taken out, and if so, setting the four write pointers to 0;
Separating four-way sampling data in a receiving pong buffer short _ pong [192] according to steps (4a) - (4f) when next receiving interruption comes;
and (5): processing the four paths of signals separated in the step (4) to obtain diversity signals:
specifically, taking out four separated paths of signals, and modulating the signals by using 2-4 carriers with different carrier frequencies respectively to obtain frequency diversity signals;
And (6): finding a frame synchronization signal FS of a main AD/DA chip in a polling mode;
Specifically, the addresses of the McBSP0 data receiving and sending registers accessed by the CPU and the EDMA are different, so that when the data are received in a polling mode, no influence is caused on the EDMA carrying number, the main Aic10 is found according to the lowest bit of the received 16-bit data being 1, namely the FS of the main Aic10 is found, then a complete communication cycle is executed, and the step (7) is executed when the next communication cycle comes;
and (7): opening a multichannel buffer serial port 0 to send a signal and enabling a twelve-numbered sending event of the enhanced direct memory access controller;
and (8): loading the diversity signals to be transmitted in the transmission interrupt service subroutine:
Specifically, (8a) clearing a flag bit of a transmission interrupt trigger event of the enhanced direct memory access controller;
(8b) Setting initial values of read pointers Txd0, Txd1, Txd2 and Txd3 of the four transmission buckets to be 0;
(8c) sequentially loading four paths of diversity signals to x _ pong [0], x _ pong [1], x _ pong [2] and x _ pong [3] of a sending ping buffer short [4], and respectively adding one to read pointers Txd0, Txd1, Txd2 and Txd3 of four sending buckets when sending a group of data;
(8d) judging whether the read pointers Txd0, Txd1, Txd2 and Txd3 are respectively larger than 0x2000, and if so, respectively resetting;
When next transmission interruption comes, sequentially loading four paths of signals into a transmission pong buffer short x _ pong [4] according to the steps (8a) - (8 d);
and (9): judging whether the signal transmission is finished:
specifically, if the transmission is finished, the entire communication process is stopped, otherwise, the entire communication process is continued.
according to the illustration of fig. 5, the order in which the sampled data from Aic10 is stored in the receiving ping buffer is from one Aic10, from zero Aic10, from the master Aic10, from two Aic10, i.e., the order in which McBSP0 receives sampled data is not from the master Aic 10. As shown in fig. 6, the multipath signals in the receiving buffer can be well separated according to step (4); according to fig. 7, some specific signals in the multiple signals in the receiving buffer can be separated according to step (4); as shown in fig. 8-10, after finding the frame synchronization signal FS of the main Aic10 according to step (6) before transmitting the multiplex signal according to step (8), the signal to be transmitted can be loaded according to step (8) as necessary.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention.
Claims (8)
1. a method for controlling the transmission and reception of a plurality of diversity signals, the method comprising:
configuring an enhanced direct memory access controller of the DSP chip into a ping-pong mode;
the method comprises the steps that automatic cascade detection is carried out on the connection of a DSP chip and a plurality of AD/DA chips through a plug-and-play algorithm, and four control registers of each AD/DA chip are automatically configured;
the DSP chip separates the received multi-path sampling signals and modulates the separated signals respectively to obtain frequency diversity signals;
and searching a frame synchronization signal FS of the main AD/DA chip in a polling mode, and loading a frequency diversity signal to be sent and sending the frequency diversity signal through the corresponding AD/DA chip in the next communication period.
2. the method for controlling transceiving of a multi-channel diversity signal according to claim 1, wherein the data migration module enhanced direct memory access controller of the DSP is configured in a ping-pong mode, specifically: when the multi-channel sampling signals are moved from the receiving end of the multi-channel buffer serial port 0, the source address is set as the address of the data receiving register of the multi-channel buffer serial port 0, the destination address of the received table parameter set is set as the address of the table buffer area, the size of the received table buffer area and the size of the received table buffer area are set to be multiple times of the number of the AD/DA chips, when the data to be sent are moved to the sending end of the multi-channel buffer serial port 0, the destination address is set as the address of the data sending register of the multi-channel buffer serial port 0, the source address of the sent table parameter set is set as the address of the sent table buffer area, and the size of the sent table buffer area is set as the number of the.
3. The method for controlling transceiving of a multi-channel diversity signal according to claim 1 or 2, wherein the automatic cascade detection of the connection of the DSP chip and the plurality of AD/DA chips is performed by a plug and play algorithm, specifically: detecting whether a master AD/DA chip exists in a plurality of cascaded AD/DA chips by checking that the lowest bit of 16-bit data received by a data receiving register is 1, if not, detecting that the automatic cascade detection of the plurality of AD/DA chips fails, if the master AD/DA chip is detected, continuously detecting whether more than two master AD/DA chips exist according to the number of the lowest bits of the plurality of received 16-bit data which is 1, if so, detecting that the automatic cascade detection of the plurality of AD/DA chips fails, if not, determining the number of cascaded slave AD/DA chips according to the number of the lowest bits of the plurality of received 16-bit data which is 0, judging whether the total number of the master AD/DA chips and the slave AD/DA chips is more than eight, if so, detecting that the automatic cascade detection of the plurality of AD/DA chips fails, if not, the automatic cascade detection of several AD/DA chips passes.
4. the method for controlling transceiving of a multi-channel diversity signal according to claim 3, wherein the DSP chip separates the received multi-channel sampling signal, specifically:
After the interruption of the receiving, determining a main AD/DA chip according to the first N receiving data in the receiving ping buffer area, and determining the sequence of storing N paths of sampling signals in the receiving ping buffer area according to the main AD/DA chip; n is the total number of AD/DA chips;
and when the next receiving interruption comes, separating the N paths of sampling signals in the receiving pong buffer area.
5. the method according to claim 4, wherein the determining of the main AD/DA chip is performed according to the first N received data in the receiving ping buffer, and specifically, the receiving data with the lowest bit of 1 in the first N received data is sequentially determined in the receiving ping buffer, and the AD/DA chip corresponding to the receiving data is the main AD/DA chip.
6. the method for controlling transceiving of a multi-path diversity signal according to claim 5, wherein the determining the order of storing the N paths of sampling signals in the reception ping buffer comprises:
and taking out and placing the received data corresponding to the master AD/DA chip into a first receiving bucket, and then sequentially taking out and placing the received data corresponding to a plurality of slave AD/DA chips into the rest receiving buckets in sequence.
7. The method for controlling transmission and reception of a multipath diversity signal according to claim 6, wherein the modulating the separated signals respectively to obtain frequency diversity signals comprises: and modulating the N paths of separated signals by 2-4 carrier waves with different carrier frequencies respectively to obtain frequency diversity signals.
8. the method for controlling transceiving of a multi-channel diversity signal according to claim 7, wherein the loading of the frequency diversity signal to be transmitted in the next communication cycle is performed by using a corresponding AD/DA chip, and specifically comprises: the method comprises the steps of searching a main AD/DA chip in a polling mode, loading a frequency diversity signal to be sent corresponding to the main AD/DA chip to a first sending barrel of a ping-pong buffer area, sequentially loading a plurality of frequency diversity signals to be sent corresponding to slave AD/DA chips to the first sending barrel of the ping-pong buffer area in sequence, sequentially loading the frequency diversity signals to be sent corresponding to the slave AD/DA chips to the remaining sending barrels, and sequentially sending the frequency diversity signals according to the sequence of the sending barrels.
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