CN112702135A - Signal processing method, device, system, medium and electronic equipment - Google Patents
Signal processing method, device, system, medium and electronic equipment Download PDFInfo
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Abstract
The present disclosure relates to the field of communications technologies, and in particular, to a method, an apparatus, a system, a medium, and an electronic device for processing a signal, where the method includes: acquiring first signals output by a plurality of network elements, wherein each first signal is from the same source signal and has a first chip rate; sampling and converting each first signal to obtain a corresponding second signal, wherein each second signal has a second chip rate, and the second chip rate is greater than the first chip rate; and aligning each second signal after sampling conversion and then adding the aligned second signals to form a path of signal. According to the embodiment of the disclosure, the alignment and addition processing are performed on the signals on the basis of improving the chip rate, so that the signal alignment delay precision can be improved, the signal delay after the addition is more accurate, and the situation that the corresponding signals are cut and cannot be normally processed due to the fact that the signal delay exceeds the standard is greatly reduced.
Description
Technical Field
Embodiments of the present disclosure relate to the field of communications technologies, and in particular, to a signal processing method, a signal processing apparatus, a communication system including the signal processing apparatus, and a computer-readable storage medium and an electronic device for implementing the signal processing method.
Background
In a communication system, for example, multiple carrier signals transmitted or received on either a downlink or an uplink must be aligned with an air interface antenna to ensure that the carrier signals are transmitted or received at the time when the air interface is aligned.
Because of the existence of the wireless communication protocol with the time synchronization requirement, the wireless communication protocol defines the air interface time synchronization requirement for the data transmission of air interface antennas, for example, the air interface time synchronization means that the data with the same frame number of each antenna in a station or each antenna between stations needs to be transmitted at the time point of air interface alignment. Therefore, the transmission or the reception of the carrier signals at the moment of aligning the empty ports is ensured to be in accordance with the performance index defined by the wireless communication protocol, so that the signals can be normally transmitted or received.
However, in the prior art, when multiple carrier signals are aligned and combined, the delay precision is poor, so that the problem that the delay of a certain signal exceeds the standard is easily caused, and the corresponding signal cannot be normally processed.
Disclosure of Invention
In order to solve the technical problem described above or at least partially solve the technical problem described above, the present disclosure provides a signal processing method, a signal processing apparatus, a communication system including the signal processing apparatus, and a computer-readable storage medium and an electronic device implementing the signal processing method.
In a first aspect, an embodiment of the present disclosure provides a signal processing method, including:
acquiring first signals output by a plurality of network elements, wherein each first signal is from the same source signal and has a first chip rate;
sampling and converting each first signal to obtain a corresponding second signal, wherein each second signal has a second chip rate, and the second chip rate is greater than the first chip rate;
and aligning each second signal after sampling conversion and then adding the aligned second signals to form a path of signal.
In some embodiments of the present disclosure, each of the first signals comprises multiple channels of signal data;
the sampling conversion processing is performed on each first signal to obtain a corresponding second signal, and the sampling conversion processing includes:
and respectively carrying out sampling conversion processing on the multi-channel signal data of each first signal to obtain a corresponding second signal, wherein the second signal comprises the corresponding converted multi-channel signal data.
In some embodiments of the present disclosure, the aligning and adding each of the second signals after sample conversion to form a path of signal includes:
aligning the signal data of the plurality of channels of each of the second signals with reference to the signal data of any one channel of each of the second signals;
and adding the signal data of one channel corresponding to each second signal until the signal data of all the channels corresponding to each second signal are added, so as to form a path of signal.
In some embodiments of the present disclosure, further comprising:
when signal data of a channel corresponding to each second signal is subjected to addition processing, judging whether the bit width of the signal data subjected to the addition processing of the channel is larger than a preset bit width;
if yes, the signal data after the channel addition processing is subjected to cyclic truncation processing.
In some embodiments of the present disclosure, further comprising:
before the cyclic truncation processing is performed on the signal data after the channel addition processing, the truncation start bit of the signal data after the channel addition processing is determined based on the configuration information.
In some embodiments of the disclosure, before the sampling conversion processing is performed on each of the first signals to obtain the corresponding second signal, the method further includes:
judging whether each first signal is a signal with the first chip rate in a preset counting period;
if yes, sampling and converting each first signal to obtain a corresponding second signal;
if not, clearing the preset counting period, and counting again to judge whether each first signal is a signal with the first chip rate in the preset counting period.
In some embodiments of the present disclosure, the first signal is a carrier signal received by a receiving end, or a carrier signal to be transmitted by a transmitting end.
In some embodiments of the present disclosure, the one-way signal formed by the adding process has the second chip rate; the method further comprises the following steps:
and carrying out sampling conversion processing on the path of signals so as to restore the path of signals after sampling conversion to have the first chip rate.
In a second aspect, an embodiment of the present disclosure provides a signal processing apparatus, including:
a signal obtaining module, configured to obtain first signals output by multiple network elements, where each of the first signals is from a same source signal and has a first chip rate;
a signal conversion module, configured to perform sampling conversion processing on each first signal to obtain a corresponding second signal, where each second signal has a second chip rate, and the second chip rate is greater than the first chip rate;
and the signal combining module is used for aligning and adding each second signal after sampling conversion to form a path of signal.
In a third aspect, an embodiment of the present disclosure provides a communication system, including the signal processing apparatus described in any of the foregoing embodiments.
In a fourth aspect, the disclosed embodiments provide a computer-readable storage medium, on which a computer program is stored, which, when executed by a processor, implements the steps of the signal processing method according to any of the above embodiments.
In a fifth aspect, an embodiment of the present disclosure provides an electronic device, including:
a processor; and
a memory for storing executable instructions of the processor;
wherein the processor is configured to perform the steps of the signal processing method of any of the above embodiments via execution of the executable instructions.
Compared with the prior art, the technical scheme provided by the embodiment of the disclosure has the following advantages:
in the embodiment of the disclosure, first signals output by a plurality of network elements are first obtained, each first signal is from a same source signal and has a first chip rate, then each first signal is subjected to sampling conversion to obtain a corresponding second signal, each second signal has a second chip rate, the second chip rate is greater than the first chip rate, and finally, each second signal after sampling conversion is aligned and then added to form a path of signal. In this way, in the delay measurement of combining signals of multiple network elements, by aligning and adding the signals based on increasing the chip rate, the scheme of this embodiment can improve the accuracy of signal alignment delay, so that the signal delay after addition is more accurate, and the situation that the corresponding signal is cut and cannot be normally processed due to the exceeding of the signal delay is greatly reduced.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure.
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present disclosure, the drawings used in the description of the embodiments or prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without inventive exercise.
FIG. 1 is a flow chart of a signal processing method according to an embodiment of the disclosure;
fig. 2 is a schematic diagram of an exemplary application scenario of a signal processing method according to an embodiment of the disclosure;
FIG. 3 is a schematic diagram of a first signal alignment in an embodiment of the present disclosure;
FIG. 4 is a schematic diagram comparing a first signal and a second signal in an embodiment of the disclosure;
FIG. 5 is a second signal alignment schematic in an embodiment of the present disclosure;
FIG. 6 is a schematic diagram of a signal processing apparatus according to an embodiment of the disclosure;
fig. 7 is a schematic diagram of a communication system shown in an embodiment of the present disclosure;
fig. 8 is a schematic diagram of an electronic device implementing a signal processing method according to an embodiment of the disclosure.
Detailed Description
In order that the above objects, features and advantages of the present disclosure may be more clearly understood, aspects of the present disclosure will be further described below. It should be noted that the embodiments and features of the embodiments of the present disclosure may be combined with each other without conflict.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure, but the present disclosure may be practiced in other ways than those described herein; it is to be understood that the embodiments disclosed in the specification are only a few embodiments of the present disclosure, and not all embodiments.
It is to be understood that, hereinafter, "at least one" means one or more, "a plurality" means two or more. "and/or" is used to describe the association relationship of the associated objects, meaning that there may be three relationships, for example, "a and/or B" may mean: only A, only B and both A and B are present, wherein A and B may be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship. "at least one of the following" or similar expressions refer to any combination of these items, including any combination of single item(s) or plural items. For example, at least one (one) of a, b, or c, may represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", wherein a, b, c may be single or plural.
Fig. 1 is a flowchart illustrating a signal processing method according to an embodiment of the disclosure, where the signal processing method may be applied to a delay measurement in which signals of multiple network elements are combined in a communication system. Specifically, the signal processing method may include the steps of:
step S101: first signals output by a plurality of network elements are obtained, and each first signal is from the same source signal and has a first chip rate.
Specifically, the network element is an element in a communication system network, such as a device in the network, for example, for a long Term evolution lte (long Term evolution) system architecture, the network element includes many network elements, for example, a base station is a network element, and may further include a mobility Management entity mme (mobility Management entity), a serving gateway sgw (serving gateway), a public Data network pdn (public Data network), and the like. In other embodiments, the network element may also be a switch, a router, etc.
The chip rate, also called symbol rate, is the rate of the user data symbol after spreading, and is usually divided into two IQ paths, which are respectively and sequentially spread and scrambled at the same time. In W-CDMA systems, the rate at which the user data symbols are spread, i.e., the chip rate, is typically 3.84 Mcps. In the embodiment, the W-CDMA system is taken as an example, so the first chip rate Fp1 may be 3.84Mcps, but is not limited thereto.
In an exemplary application scenario, each network element may configure an optical fiber interface (hereinafter, referred to as an optical port) for signal transceiving, as shown in fig. 2, there are N optical ports configured by N network elements, so that first signals from the same source signal output by a corresponding plurality of network elements may be obtained from each optical port, that is, each first signal is a complete source signal. For example, in a signaling link of a communication system, the first signal may be a carrier signal to be transmitted by a transmitting end. For example, in a signal receiving chain of the communication system, the first signal may be a carrier signal received by a receiving end, but the specific selection of the first signal is not limited thereto.
In an embodiment of the disclosure, each optical port may perform sequential logic control on the first signal based on the first clock signal. Illustratively, the first clock frequency Clk1 of the first clock signal may be 184.32MHz, but is not limited thereto.
Step S102: and sampling and converting each first signal to obtain a corresponding second signal, wherein each second signal has a second chip rate, and the second chip rate is greater than the first chip rate.
Illustratively, after acquiring first signals, such as carrier signals, from the same source signal output by a corresponding plurality of network elements from each optical port shown in fig. 2, each of the first signals may be subjected to a sampling conversion process to obtain corresponding second signals, each of the second signals has a second chip rate Fp2, and the second chip rate Fp2 is greater than the first chip rate Fp 1.
In an embodiment of the present disclosure, the second signal may be subjected to sequential logic control based on the matched second clock signal. Illustratively, the second clock signal has a second clock frequency Clk2, and in order to match the second signal with a high processing chip rate, the second clock frequency Clk2 is greater than the first clock frequency Clk1, for example, the value of the second clock frequency Clk2 may be M times the value of the second chip rate Fp2, that is, Clk2 is M × Fp2, and M is a natural number greater than or equal to 1. In an example embodiment, the second chip rate Fp2 may be 115.2Mcps, and the second clock frequency Clk2 of the second clock signal may be 230.4MHz, i.e., M is 2, but is not limited thereto.
Step S103: and aligning each second signal after sampling conversion and then adding the aligned second signals to form a path of signal.
After the above sampling conversion, the first chip rate Fp1 of the first signal is increased to the second chip rate Fp2 to form the second signal, Fp2 is greater than Fp1, and the second clock frequency Clk2 of the corresponding second clock signal is also increased to adapt the corresponding processing to the second signal with the higher chip rate.
In the signal processing method in the embodiment of the disclosure, in the time delay measurement of combining signals of multiple network elements, alignment and addition processing can be performed on the signals on the basis of increasing the chip rate, so that the signal alignment time delay precision can be improved, the signal time delay after addition is more accurate, and the situation that the corresponding signal is cut and cannot be normally processed due to the exceeding of the signal time delay is greatly reduced. For example, the signal alignment and combination processing can be performed within a range with small delay error of each path of signal, and the problems that the signal cannot be normally processed, such as normal demodulation and the like, due to exceeding of delay caused by certain factors such as data jitter of an optical fiber interface are solved.
In some embodiments of the present disclosure, each of the first signals may include multiple channels of signal data. For example, in the above exemplary application scenario, each network element configures an optical port to perform signal transceiving. Each optical port may include a plurality of channels, and when the first signal enters or exits the optical port of each network element, the first signal may be formed of signal data of the plurality of channels of the optical port. Correspondingly, in step S102, sampling and converting each of the first signals to obtain a corresponding second signal, which may specifically include the following steps:
and respectively carrying out sampling conversion processing on the multi-channel signal data of each first signal to obtain a corresponding second signal, wherein the second signal comprises the corresponding converted multi-channel signal data.
Illustratively, as shown in fig. 3, each optical port may include, but is not limited to, four channels, such as channel 1, channel 2, channel 3, and channel 4, and the corresponding first signal, such as a signal having a chip rate of 3.84Mcps, may include signal data of the four channels, such as the signal data corresponding to each of channel 1, channel 2, channel 3, and channel 4 shown in fig. 3. Therefore, the sampling conversion processing may be performed on the signal data of each first signal, such as channel 1, channel 2, channel 3, and channel 4, to obtain a corresponding second signal, where the second signal may include the signal data of the corresponding converted channel 1, channel 2, channel 3, and channel 4. Referring collectively to the illustration in fig. 4, the sample-converted second signal 200 has a chip rate of 115.2Mcps, while the first signal 100 has a chip rate of 3.84Mcps, the chip rate of the second signal 200 being significantly greater than the chip rate of the first signal 100.
Optionally, on the basis of the foregoing embodiments, in some embodiments of the present disclosure, aligning each of the second signals after sampling conversion in step S103, and then performing addition processing to form a path of signal, specifically, the method may include the following steps:
step 1): and aligning the signal data of the plurality of channels of each of the second signals with reference to the signal data of any one channel of each of the second signals.
Illustratively, referring to the illustration in FIG. 5, each second signal has N channels of signal data, and for each second signal, the remaining (N-1) channels of signal data may be aligned with the channel 1 signal data with reference to the channel 1 signal data. In this embodiment, the value of N may be 4, but is not limited to this, which is matched with the signal data of the four channels of the first signal.
Step 2): and adding the signal data of one channel corresponding to each second signal until the signal data of all the channels corresponding to each second signal are added, so as to form a path of signal.
For example, 2 second signals are taken as an example, and each of the 2 second signals includes signal data of N channels, then the signal data of the i (i ═ 1, 2, …, N) channel of one of the second signals and the signal data of the i channel of the other second signal may be added together, until the signal data of all N channels corresponding to the 2 second signals are added together to form one signal.
To better illustrate the technical effects of the solutions of the above embodiments of the present disclosure, please refer to fig. 3 and fig. 5, when the signals of the channels shown in fig. 3 are aligned, for example, when the signals of the channel 1 are aligned with reference to the current time, the signal delay of the channel 2 is L1, the signal delay of the channel 3 is L2, and the signal delay of the channel 4 is L3. In this example, L2 is greater than L3, and L3 is greater than L1. When the signals are aligned after the chip rate is increased by the scheme of the embodiment of the present disclosure, as shown in fig. 5, for example, when the alignment is performed with reference to the channel 1, the delay of the signal of the channel N is L4, in this embodiment, since the signal alignment is performed after the chip rate of the signal is increased, L4 is much smaller than L1, that is, the accuracy of the signal alignment delay is higher. Therefore, in the signal processing method in the embodiment of the present disclosure, in the time delay measurement of combining signals of multiple network elements, the signals may be aligned and added on the basis of increasing the chip rate, so that the signal alignment time delay accuracy may be increased, the signal time delay after adding is more accurate, and the situation that the corresponding signal is cut and cannot be normally processed due to the signal time delay exceeding is greatly reduced. For example, the signal alignment and combination processing can be performed within a range with small delay error of each path of signal, and the problems that the signal cannot be normally processed, such as normal demodulation and the like, due to exceeding of delay caused by certain factors such as data jitter of an optical port are solved.
Optionally, on the basis of any one of the above embodiments, in some embodiments of the present disclosure, the method further includes the following steps:
step a): and when the signal data of one channel corresponding to each second signal is subjected to addition processing, judging whether the bit width of the signal data subjected to the addition processing of the channel is greater than the preset bit width.
For example, when the signal data of the ith (i ═ 1, 2, …, N) channel of one second signal and the signal data of the ith channel of another second signal are added, it is determined whether the bit width of the signal data after the addition processing of the ith channel is greater than the preset bit width. Wherein the preset bit width may be a maximum data bit width of the ith channel.
Step b): if yes, the signal data after the channel addition processing is subjected to cyclic truncation processing.
For example, when it is determined that the bit width of the signal data after the addition processing of the ith channel is greater than the preset bit width, the signal data after the addition processing of the ith channel is subjected to the cyclic truncation processing.
The main function of the data truncation processing is to implement processing of data bit width, for example, the data width after the digital signal processing is truncated for subsequent processing of the digital signal. The bit-cutting processing of the data mainly includes, but is not limited to, performing high bit-cutting on the signal output of the digital signal processing, performing low bit-cutting on the signal output of the digital signal processing, and the like. In this embodiment, taking an example that each optical port includes 4 channels, that is, the first signal includes signal data of four channels, first, signal data of one channel (4 channels in total) corresponding to the 4 optical ports is sequentially extracted for addition, and assuming that each original channel has a data bit width of 16 bits, when that bit is added to signal data of one channel corresponding to the 4 optical ports, in order to retain a data sign bit thereof, the bit width of the combined data is greater than 16 bits, and in order to prevent an effective signal from overflowing, so that the added data is also guaranteed to be output with a data bit width of 16 bits, the added signal data may be subjected to cyclic truncation processing, and if the truncation start bit during each truncation processing is dynamically changed in sequence according to a time sequence change, the truncation start bit is different.
According to the scheme of the embodiment, the influence of noise signals such as stray signals can be reduced through cyclic bit truncation instead of bit truncation of fixed data bits, so that the quality of signals obtained after combination processing is better.
Optionally, on the basis of the above embodiments, in some embodiments of the present disclosure, the following steps may also be included: before the cyclic truncation processing is performed on the signal data after the channel addition processing, the truncation start bit of the signal data after the channel addition processing is determined based on the configuration information.
For example, the configuration information may be a value of a register, for example, the truncation start bits of the signal data after the combining and adding process may be flexibly selected by the value of the configuration register, and the truncation start bits of the signal data are different if the values of the configured registers are different, so that the scheme of this embodiment may flexibly configure the truncation start bits, and the application range is wider.
Optionally, on the basis of any of the foregoing embodiments, in some embodiments of the present disclosure, before performing sampling conversion processing on each of the first signals in step S102 to obtain a corresponding second signal, the method may further include the following steps:
step i): and judging whether each first signal is a signal with the first chip rate in a preset counting period.
For example, it may be determined whether each of the first signals is a signal having a chip rate of 3.84Mcps within a preset count period.
Step ii): and if so, sampling and converting each first signal to obtain a corresponding second signal.
For example, when each first signal is a signal having a chip rate of 3.84Mcps within a preset counting period, the step S102 may be skipped to perform a sampling conversion process on each first signal to obtain a corresponding second signal.
Step iii): if not, clearing the preset counting period, and counting again to judge whether each first signal is a signal with the first chip rate in the preset counting period.
Illustratively, when each first signal is not a signal with the chip rate of 3.84Mcps at least once in a preset counting period, clearing the preset counting period, and counting again to judge whether each first signal is a signal with the chip rate of 3.84Mcps in the preset counting period.
The above-mentioned solution of this embodiment can implement stability determination on the original first signal output by each optical port, for example, if the signals have a chip rate of 3.84Mcps in the preset counting period, it is determined that the first signal is a stable periodic signal having a chip rate of 3.84Mcps, and if at least one time of the current determination that the chip rate is not 3.84Mcps, the first signal is not a stable periodic signal, it is necessary to perform zero clearing and recounting determination on all counting periods until a stable periodic signal occurs in a specified preset counting period. The preset counting period can be set according to specific needs, and is not particularly limited. In this embodiment, the jitter problem of the signal can be substantially eliminated in advance through the above-described implementation, and then the clock domain and chip rate conversion of the original first signal can be completed to prepare for the alignment combining process based on the converted second signal. According to the scheme, the jitter problem of the signal is substantially eliminated in advance, the alignment delay precision of the subsequent signal is further improved, the signal delay after subsequent addition is more accurate, and the delay precision of the signal is further improved on the whole.
Optionally, on the basis of any one of the foregoing embodiments, in some embodiments of the present disclosure, the one path of signal formed by the adding process has the second chip rate, for example, the chip rate of the one path of signal is 115.2 Mcps. Accordingly, the method may further comprise the steps of: and carrying out sampling conversion processing on the path of signals so as to restore the path of signals after sampling conversion to have the first chip rate.
For example, as shown in fig. 2, in the present embodiment, the signal after aligned combination may be further recovered by sampling rate conversion to a signal with a chip rate of 3.84Mcps, for example, which corresponds to a clock frequency of the matched clock signal being 184.32MHz, for example, so that the processing complexity of the downstream processing module, such as a processor, can be reduced, and thus the performance requirement of the processing module can be reduced to save the device cost.
In one embodiment of the present disclosure, as shown in fig. 2, a sampling rate conversion module is used to convert a received signal with a clock frequency of 184.32MHz and a chip rate of 3.84Mcps into a signal with a clock frequency of 230.4MHz and a chip rate of 115.2Mcps, so as to increase the chip rate of the signal.
On the basis that the chip rate of the received signal is increased, the signal data of each channel corresponding to each optical port are added and circularly truncated, so that the received signals of a plurality of optical ports are aligned, added and combined into one optical port signal.
And recovering the aligned and combined signals into a path of signals with the clock frequency of 184.32MHz and the chip rate of 3.84Mcps through a sampling rate conversion module, wherein the path of signals can be aligned with an air interface frame header and then reach an upper physical layer for demodulation. The signal with relatively high code chip rate can improve the time delay precision of signal alignment of each optical port, and the alignment addition of signal data is carried out under higher precision time delay, so that the signal time delay precision after the combination can be improved, and the problem that the signal is cut and cannot be normally demodulated due to the fact that the time delay exceeds the standard caused by data jitter of certain optical ports is solved. In addition, the processing complexity of the downstream processing unit can be reduced by recovering to a signal with a lower chip rate.
The scheme of this embodiment adopts a signal with a relatively high chip rate, which may improve the delay accuracy of signal alignment of each optical port, and perform alignment and summation of signal data under a higher accuracy delay, which may improve the delay accuracy of the signal after being combined, and reduce the delay error caused by the data jitter of individual optical ports after being combined, thereby causing problems such as uplink demodulation failure. That is, the scheme of this embodiment increases the signal sampling rate and then performs alignment addition, which effectively solves the problem of poor delay accuracy during signal alignment addition at the original chip rate of, for example, 3.84Mcps, and the signal alignment delay accuracy is improved by nearly 30 times after being processed by the scheme of this embodiment through experiments.
It should be noted that although the various steps of the methods of the present disclosure are depicted in the drawings in a particular order, this does not require or imply that these steps must be performed in this particular order, or that all of the depicted steps must be performed, to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken down into multiple step executions, etc. Additionally, it will also be readily appreciated that the steps may be performed synchronously or asynchronously, e.g., among multiple modules/processes/threads.
Based on the same concept, an embodiment of the present disclosure further provides a signal processing apparatus, such as the signal processing apparatus 60 shown in fig. 6, which may include a signal obtaining module 601, a signal converting module 602, and a signal combining module 603, where:
a signal obtaining module 601, configured to obtain first signals output by multiple network elements, where each of the first signals is from a same source signal and has a first chip rate.
A signal conversion module 602, configured to perform sampling conversion processing on each first signal to obtain a corresponding second signal, where each second signal has a second chip rate, and the second chip rate is greater than the first chip rate.
A signal combining module 603, configured to align each of the sampled and converted second signals and then add the aligned second signals to form a signal.
In the delay measurement for combining signals of multiple network elements, the signal processing apparatus 60 in the embodiment of the present disclosure may perform alignment and add processing on signals on the basis of increasing the chip rate, so as to improve the signal alignment delay precision, so that the signal delay after adding is more accurate, and further, it may perform signal alignment and add processing within a range where the delay error of each signal is very small, and solve the problem that the subsequent signal cannot be normally processed due to the exceeding of the delay caused by some factors.
Optionally, in some embodiments of the present disclosure, each of the first signals includes multiple channels of signal data. The signal conversion module 602 performs sampling conversion processing on each first signal to obtain a corresponding second signal, and specifically includes: and respectively carrying out sampling conversion processing on the multi-channel signal data of each first signal to obtain a corresponding second signal, wherein the second signal comprises the corresponding converted multi-channel signal data.
Optionally, in some embodiments of the present disclosure, the signal combining module 603 aligns each of the second signals after sampling and converting, and then adds the aligned second signals to form a signal, which specifically includes: aligning the signal data of the plurality of channels of each of the second signals with reference to the signal data of any one channel of each of the second signals; and adding the signal data of one channel corresponding to each second signal until the signal data of all the channels corresponding to each second signal are added, so as to form a path of signal.
Optionally, in some embodiments of the present disclosure, the signal combining module 603 is further configured to: when signal data of a channel corresponding to each second signal is subjected to addition processing, judging whether the bit width of the signal data subjected to the addition processing of the channel is larger than a preset bit width; if yes, the signal data after the channel addition processing is subjected to cyclic truncation processing.
Optionally, in some embodiments of the present disclosure, the signal combining module 603 is further configured to: before the cyclic truncation processing is performed on the signal data after the channel addition processing, the truncation start bit of the signal data after the channel addition processing is determined based on the configuration information.
Optionally, in some embodiments of the present disclosure, the apparatus may further include a signal determining module, configured to determine whether each of the first signals is a signal with the first chip rate within a preset counting period before the signal converting module 602 performs sampling conversion on each of the first signals to obtain a corresponding second signal; if yes, the signal conversion module 602 performs sampling conversion processing on each first signal to obtain a corresponding second signal; if not, clearing the preset counting period, and counting again to judge whether each first signal is a signal with the first chip rate in the preset counting period.
Optionally, in some embodiments of the present disclosure, the first signal may be a carrier signal received by the receiving end, or a carrier signal to be transmitted by the transmitting end, but is not limited thereto.
Optionally, in some embodiments of the present disclosure, the one-way signal formed by the adding process has the second chip rate. The device may further include a signal recovery module, configured to perform sampling conversion processing on the one path of signal, so that the one path of signal after sampling conversion is recovered to have the first chip rate.
In a specific application scenario, the above signal processing apparatus 60 can be implemented on a programmable logic device such as an FPGA, so that the processing cost of the peripheral chip can be reduced.
In addition, some embodiments of the present disclosure provide a communication system, such as the communication system shown in fig. 7, and the communication system 70 may include the signal processing apparatus 60 described in any of the embodiments above. Illustratively, the communication system 70 may include a plurality of network elements (not shown), and the signal processing device 60 may be communicatively connected to the plurality of network elements, respectively.
In the delay measurement for combining signals of multiple network elements, the communication system 70 in the embodiment of the present disclosure may perform alignment and add processing on signals on the basis of increasing the chip rate, so as to improve the signal alignment delay precision, so that the signal delay after adding is more accurate, and further, may perform signal alignment and combining processing within a range where the delay error of each signal is very small, and eliminate the problem that the subsequent signal cannot be normally processed due to the delay exceeding caused by some factors.
The specific manner in which each module performs operations and other corresponding technical effects have been described in detail in the embodiments related to the method, and will not be described in detail herein.
It should be noted that although in the above detailed description several modules or units of the device for action execution are mentioned, such a division is not mandatory. Indeed, the features and functionality of two or more modules or units described above may be embodied in one module or unit, according to embodiments of the present disclosure. Conversely, the features and functions of one module or unit described above may be further divided into embodiments by a plurality of modules or units. The components shown as modules or units may or may not be physical units, i.e. may be located in one place or may also be distributed over a plurality of network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the wood-disclosed scheme. One of ordinary skill in the art can understand and implement it without inventive effort.
The disclosed embodiments also provide a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the following signal processing method:
acquiring first signals output by a plurality of network elements, wherein each first signal is from the same source signal and has a first chip rate;
sampling and converting each first signal to obtain a corresponding second signal, wherein each second signal has a second chip rate, and the second chip rate is greater than the first chip rate;
and aligning each second signal after sampling conversion and then adding the aligned second signals to form a path of signal.
Optionally, in some embodiments of the present disclosure, each of the first signals includes multiple channels of signal data. Correspondingly, the sampling and converting each of the first signals to obtain a corresponding second signal includes:
and respectively carrying out sampling conversion processing on the multi-channel signal data of each first signal to obtain a corresponding second signal, wherein the second signal comprises the corresponding converted multi-channel signal data.
Optionally, in some embodiments of the present disclosure, the aligning and adding each of the second signals after sampling conversion to form a path of signal includes:
aligning the signal data of the plurality of channels of each of the second signals with reference to the signal data of any one channel of each of the second signals;
and adding the signal data of one channel corresponding to each second signal until the signal data of all the channels corresponding to each second signal are added, so as to form a path of signal.
Optionally, in some embodiments of the present disclosure, the method further comprises the steps of:
when signal data of a channel corresponding to each second signal is subjected to addition processing, judging whether the bit width of the signal data subjected to the addition processing of the channel is larger than a preset bit width;
if yes, the signal data after the channel addition processing is subjected to cyclic truncation processing.
Optionally, in some embodiments of the present disclosure, the method further comprises the steps of:
before the cyclic truncation processing is performed on the signal data after the channel addition processing, the truncation start bit of the signal data after the channel addition processing is determined based on the configuration information.
Optionally, in some embodiments of the present disclosure, before performing sampling conversion processing on each of the first signals to obtain a corresponding second signal, the method further includes the following steps:
judging whether each first signal is a signal with the first chip rate in a preset counting period;
if yes, sampling and converting each first signal to obtain a corresponding second signal;
if not, clearing the preset counting period, and counting again to judge whether each first signal is a signal with the first chip rate in the preset counting period.
Optionally, in some embodiments of the present disclosure, the first signal is a carrier signal received by a receiving end, or a carrier signal to be transmitted by a transmitting end.
Optionally, in some embodiments of the present disclosure, the one-way signal formed by the adding process has the second chip rate; the method further comprises the steps of:
and carrying out sampling conversion processing on the path of signals so as to restore the path of signals after sampling conversion to have the first chip rate.
The readable storage medium may be, for example but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples (a non-exhaustive list) of the readable storage medium include: an electrical connection having one or more wires, a portable disk, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
The computer readable storage medium may include a propagated data signal with readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated data signal may take many forms, including, but not limited to, electro-magnetic, optical, or any suitable combination thereof. A readable storage medium may also be any readable medium that is not a readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a readable storage medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
The embodiment of the present disclosure also provides an electronic device, as shown in fig. 8, including a processor 802 and a memory 801, where the memory 801 is used to store executable instructions of the processor 802. Wherein the processor 802 is configured to perform the steps of the signal processing method in any of the above embodiments, such as the steps of the signal processing method shown in fig. 1, via execution of the executable instructions.
In some embodiments, the electronic device may be a base station, but is not so limited. It should be understood that although not shown in the figures, the electronic device 80 may use other hardware and/or software modules, including but not limited to: bus, microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems, to name a few.
Through the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein may be implemented by software, or by software in combination with necessary hardware. Therefore, the technical solution according to the embodiments of the present disclosure may be embodied in the form of a software product, which may be stored in a non-volatile storage medium (which may be a CD-ROM, a usb disk, a removable hard disk, etc.) or on a network, and includes several instructions to enable a computing device (which may be a personal computer, a base station, or a network device, etc.) or perform the steps of the above-mentioned signal processing method according to the embodiments of the present disclosure.
It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The foregoing are merely exemplary embodiments of the present disclosure, which enable those skilled in the art to understand or practice the present disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (12)
1. A signal processing method, comprising:
acquiring first signals output by a plurality of network elements, wherein each first signal is from the same source signal and has a first chip rate;
sampling and converting each first signal to obtain a corresponding second signal, wherein each second signal has a second chip rate, and the second chip rate is greater than the first chip rate;
and aligning each second signal after sampling conversion and then adding the aligned second signals to form a path of signal.
2. The signal processing method according to claim 1, wherein each of the first signals includes signal data of a plurality of channels;
the sampling conversion processing is performed on each first signal to obtain a corresponding second signal, and the sampling conversion processing includes:
and respectively carrying out sampling conversion processing on the multi-channel signal data of each first signal to obtain a corresponding second signal, wherein the second signal comprises the corresponding converted multi-channel signal data.
3. The signal processing method according to claim 2, wherein the aligning and adding each of the second signals after sample conversion to form a single signal comprises:
aligning the signal data of the plurality of channels of each of the second signals with reference to the signal data of any one channel of each of the second signals;
and adding the signal data of one channel corresponding to each second signal until the signal data of all the channels corresponding to each second signal are added, so as to form a path of signal.
4. The signal processing method of claim 3, further comprising:
when signal data of a channel corresponding to each second signal is subjected to addition processing, judging whether the bit width of the signal data subjected to the addition processing of the channel is larger than a preset bit width;
if yes, the signal data after the channel addition processing is subjected to cyclic truncation processing.
5. The signal processing method of claim 4, further comprising:
before the cyclic truncation processing is performed on the signal data after the channel addition processing, the truncation start bit of the signal data after the channel addition processing is determined based on the configuration information.
6. The signal processing method according to any one of claims 1 to 5, wherein before the sampling conversion processing is performed on each of the first signals to obtain a corresponding second signal, the method further comprises:
judging whether each first signal is a signal with the first chip rate in a preset counting period;
if yes, sampling and converting each first signal to obtain a corresponding second signal;
if not, clearing the preset counting period, and counting again to judge whether each first signal is a signal with the first chip rate in the preset counting period.
7. The signal processing method of claim 6, wherein the first signal is a carrier signal received by a receiving end or a carrier signal to be transmitted by a transmitting end.
8. The signal processing method of claim 6, wherein the one-way signal formed by the addition processing has the second chip rate; the method further comprises the following steps:
and carrying out sampling conversion processing on the path of signals so as to restore the path of signals after sampling conversion to have the first chip rate.
9. A signal processing apparatus, characterized by comprising:
a signal obtaining module, configured to obtain first signals output by multiple network elements, where each of the first signals is from a same source signal and has a first chip rate;
a signal conversion module, configured to perform sampling conversion processing on each first signal to obtain a corresponding second signal, where each second signal has a second chip rate, and the second chip rate is greater than the first chip rate;
and the signal combining module is used for aligning and adding each second signal after sampling conversion to form a path of signal.
10. A communication system comprising the signal processing apparatus of claim 9.
11. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the signal processing method according to any one of claims 1 to 8.
12. An electronic device, comprising:
a processor; and
a memory for storing executable instructions of the processor;
wherein the processor is configured to perform the steps of the signal processing method of any one of claims 1 to 8 via execution of the executable instructions.
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