CN112702135B - Signal processing method, device, system, medium and electronic equipment - Google Patents
Signal processing method, device, system, medium and electronic equipment Download PDFInfo
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Abstract
The disclosure relates to the technical field of communication, in particular to a signal processing method, a device, a system, a medium and electronic equipment, wherein the method comprises the following steps: acquiring first signals output by a plurality of network elements, wherein each first signal is from the same source signal and has a first chip rate; sampling and converting each first signal to obtain a corresponding second signal, wherein each second signal has a second chip rate, and the second chip rate is larger than the first chip rate; and aligning each second signal after sampling conversion, and then adding to form a signal. According to the embodiment of the disclosure, the signal alignment delay precision can be improved by performing alignment and addition processing on the signals on the basis of improving the chip rate, so that the signal delay after addition is more accurate, and the situation that the corresponding signals are cut and cannot be processed normally due to exceeding of the signal delay is greatly reduced.
Description
Technical Field
The embodiment of the disclosure relates to the technical field of communication, in particular to a signal processing method, a signal processing device, a communication system comprising the signal processing device, a computer readable storage medium and electronic equipment for realizing the signal processing method.
Background
In a communication system, whether downlink or uplink, for example, a transmitted or received multipath carrier signal must be aligned with an air interface antenna to ensure that the carrier signal is transmitted or received at the time of air interface alignment.
Because there is a wireless communication protocol with a time synchronization requirement, the wireless communication protocol defines a time synchronization requirement of air interface for data transmission of, for example, air interface antennas, and the time synchronization of the air interface means that the data of the same frame number of each antenna in a station or each antenna between stations needs to be transmitted at an air interface alignment time point. Therefore, the carrier signal is ensured to be transmitted or received at the time of air interface alignment, which accords with the performance index defined by the wireless communication protocol, so that the signal can be normally transmitted or received.
However, the delay precision of the alignment Lu Shishi of the multi-path carrier signals in the related art is poor, so that the problem that the delay of a certain path of signal exceeds the standard is easily caused, and the corresponding signal is cut and cannot be processed normally.
Disclosure of Invention
To solve or at least partially solve the above technical problems, the present disclosure provides a signal processing method, a signal processing apparatus, a communication system including the signal processing apparatus, and a computer-readable storage medium and an electronic device implementing the signal processing method.
In a first aspect, an embodiment of the present disclosure provides a signal processing method, including:
acquiring first signals output by a plurality of network elements, wherein each first signal is from the same source signal and has a first chip rate;
sampling and converting each first signal to obtain a corresponding second signal, wherein each second signal has a second chip rate, and the second chip rate is larger than the first chip rate;
and aligning each second signal after sampling conversion, and then adding to form a signal.
In some embodiments of the disclosure, each of the first signals comprises multichannel signal data;
the step of performing sampling conversion processing on each first signal to obtain a corresponding second signal includes:
and respectively carrying out sampling conversion processing on the multi-channel signal data of each first signal to obtain a corresponding second signal, wherein the second signal comprises the corresponding converted multi-channel signal data.
In some embodiments of the disclosure, the aligning and adding each of the second signals after the sample conversion to form a signal includes:
aligning the signal data of the multiple channels of each second signal with the signal data of any channel of each second signal as a reference;
And adding the signal data of one channel corresponding to each second signal until the signal data of all channels corresponding to each second signal are added, so as to form one channel of signal.
In some embodiments of the present disclosure, further comprising:
when adding signal data of each second signal corresponding to one channel, judging whether the bit width of the signal data after the channel adding process is larger than a preset bit width;
if yes, the signal data after the channel addition processing is subjected to cyclic bit cutting processing.
In some embodiments of the present disclosure, further comprising:
before performing cyclic truncating processing on the signal data after the channel addition processing, a truncating start bit of the signal data after the channel addition processing is determined based on the configuration information.
In some embodiments of the present disclosure, before the performing sampling conversion processing on each of the first signals to obtain a corresponding second signal, the method further includes:
judging whether each first signal is a signal with the first chip rate in a preset counting period;
if yes, sampling and converting each first signal to obtain a corresponding second signal;
If not, resetting the preset counting period, and re-counting to judge whether each first signal is a signal with the first chip rate in the preset counting period.
In some embodiments of the present disclosure, the first signal is a carrier signal received by the receiving end, or a carrier signal to be transmitted by the transmitting end.
In some embodiments of the present disclosure, the one-way signal formed by the adding process has the second chip rate; the method further comprises the steps of:
and carrying out sampling conversion processing on the one path of signal so as to recover the sampled and converted one path of signal to have the first chip rate.
In a second aspect, an embodiment of the present disclosure provides a signal processing apparatus, including:
the signal acquisition module is used for acquiring first signals output by a plurality of network elements, wherein each first signal is from the same source signal and has a first chip rate;
the signal conversion module is used for carrying out sampling conversion processing on each first signal to obtain corresponding second signals, and each second signal has a second chip rate which is larger than the first chip rate;
and the signal combining module is used for aligning each second signal after sampling conversion and then adding the second signals to form one path of signal.
In a third aspect, an embodiment of the present disclosure provides a communication system, including a signal processing apparatus as described in any one of the above embodiments.
In a fourth aspect, an embodiment of the present disclosure provides a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the signal processing method according to any of the above embodiments.
In a fifth aspect, embodiments of the present disclosure provide an electronic device, including:
a processor; and
a memory for storing executable instructions of the processor;
wherein the processor is configured to perform the steps of the signal processing method of any of the embodiments described above via execution of the executable instructions.
Compared with the prior art, the technical scheme provided by the embodiment of the disclosure has the following advantages:
in this embodiment of the present disclosure, first signals output by a plurality of network elements are obtained first, each of the first signals is from a same source signal and has a first chip rate, then each of the first signals is subjected to sampling conversion processing to obtain a corresponding second signal, each of the second signals has a second chip rate, the second chip rate is greater than the first chip rate, and finally each of the second signals after sampling conversion is aligned and then added to form a signal. In this way, in the solution of this embodiment, in the delay measurement for combining signals of multiple network elements, by aligning and adding signals on the basis of increasing the chip rate, the delay precision of signal alignment can be increased, so that the delay of signals after addition is more accurate, and the situation that the corresponding signals are cut and cannot be processed normally due to exceeding of the delay of signals is greatly reduced.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure.
In order to more clearly illustrate the embodiments of the present disclosure or the solutions in the prior art, the drawings that are required for the description of the embodiments or the prior art will be briefly described below, and it will be obvious to those skilled in the art that other drawings can be obtained from these drawings without inventive effort.
FIG. 1 is a flow chart of a signal processing method according to an embodiment of the disclosure;
fig. 2 is a schematic diagram of an example application scenario of a signal processing method according to an embodiment of the disclosure;
FIG. 3 is a schematic diagram of a first signal alignment in an embodiment of the disclosure;
FIG. 4 is a schematic diagram of comparing the first signal and the second signal in an embodiment of the disclosure;
FIG. 5 is a second signal alignment diagram of an embodiment of the present disclosure;
FIG. 6 is a schematic diagram of a signal processing apparatus according to an embodiment of the disclosure;
FIG. 7 is a schematic diagram of a communication system shown in an embodiment of the disclosure;
fig. 8 is a schematic diagram of an electronic device implementing a signal processing method according to an embodiment of the disclosure.
Detailed Description
In order that the above objects, features and advantages of the present disclosure may be more clearly understood, a further description of aspects of the present disclosure will be provided below. It should be noted that, without conflict, the embodiments of the present disclosure and features in the embodiments may be combined with each other.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure, but the present disclosure may be practiced otherwise than as described herein; it will be apparent that the embodiments in the specification are only some, but not all, embodiments of the disclosure.
It should be understood that, hereinafter, "at least one (item)" means one or more, and "a plurality" means two or more. "and/or" is used to describe association relationships of associated objects, meaning that there may be three relationships, e.g., "a and/or B" may mean: only a, only B and both a and B are present, wherein a, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b or c may represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", wherein a, b, c may be single or plural.
Fig. 1 is a flowchart of a signal processing method according to an embodiment of the present disclosure, where the signal processing method may be applied to delay measurement of a communication system for performing a combining process on signals of a plurality of network elements. Specifically, the signal processing method may include the steps of:
step S101: first signals output by a plurality of network elements are obtained, wherein each first signal is from the same source signal and has a first chip rate.
Specifically, the network element is an element in a communication system network, such as a device in the network, for example, for a long term evolution LTE (Long Term Evolution) system architecture, where the network element includes many, for example, the base station is a network element, and may further include a mobility management entity MME (Mobility Management Entity), a service gateway SGW (Serving GateWay), a public data network PDN (Public Data Network), and so on. In other embodiments, the network element may also be a switch, router, or the like.
The chip (chip) rate is also called symbol rate, which refers to the rate of spread user data symbols, and is usually divided into two paths of IQ, where the two paths simultaneously and sequentially perform spreading and scrambling operations. In a wideband code division multiple access W-CDMA system, the rate at which user data symbols are spread, i.e., the chip rate, is typically 3.84Mcps. In this embodiment, the W-CDMA system is taken as an example, and thus the first chip rate Fp1 may be 3.84Mcps, but is not limited thereto.
In an example application scenario, each network element may configure an optical fiber interface (hereinafter simply referred to as an optical port) to perform signal transceiving, as shown in fig. 2, there are N optical ports configured by N network elements, so that first signals from the same source signal output by a corresponding plurality of network elements may be obtained from each optical port, that is, each first signal is a complete source signal. For example, in a signal transmission link of a communication system, the first signal may be a carrier signal to be transmitted by a transmitting end. For example, the first signal may be a carrier signal received by the receiving end in a signal receiving link of the communication system, and the specific choice of the first signal is not limited thereto.
In embodiments of the present disclosure, each optical port may perform sequential logic control on the first signal based on the first clock signal. Illustratively, the first clock frequency Clk1 of the first clock signal may be 184.32MHz, but is not limited thereto.
Step S102: and carrying out sampling conversion processing on each first signal to obtain corresponding second signals, wherein each second signal has a second chip rate, and the second chip rate is larger than the first chip rate.
For example, after the first signals, such as carrier signals, from the same source signal, which are output by the corresponding multiple network elements, are obtained from each optical port shown in fig. 2, sampling conversion processing may be performed on each first signal to obtain a corresponding second signal, where each second signal has a second chip rate Fp2, and the second chip rate Fp2 is greater than the first chip rate Fp1.
In embodiments of the present disclosure, the second signal may be clocked based on a matched second clock signal. For example, the second clock signal has a second clock frequency Clk2, and in order to match the second signal with a high processing chip rate, the second clock frequency Clk2 is greater than the first clock frequency Clk1, for example, the value of the second clock frequency Clk2 may be M times the value of the second chip rate Fp2, that is, clk2=mxfp 2, where M is a natural number greater than or equal to 1. In an exemplary embodiment, the second chip rate Fp2 may be 115.2Mcps, and the second clock frequency Clk2 of the second clock signal may be 230.4MHz, i.e., M has a value of 2, but is not limited thereto.
Step S103: and aligning each second signal after sampling conversion, and then adding to form a signal.
In this embodiment, after the sampling conversion is performed, the first chip rate Fp1 of the first signal is increased to the second chip rate Fp2 to form the second signal, fp2 is greater than Fp1, and the second clock frequency Clk2 of the corresponding second clock signal is also increased to match the corresponding processing of the second signal with the higher chip rate.
In the signal processing method in the embodiment of the disclosure, in the delay measurement of combining signals of a plurality of network elements, the signal alignment and addition processing can be performed on the basis of improving the chip rate, so that the signal alignment delay precision can be improved, the signal delay after addition is more accurate, and the situation that the corresponding signal is cut and cannot be normally processed due to the fact that the signal delay exceeds the standard is greatly reduced. For example, signal alignment and combination processing can be realized within a range with small delay error of each signal, and the problems that the signal cannot be normally processed, such as normal demodulation, and the like, due to the fact that delay exceeds standard caused by certain factors, such as data jitter of an optical fiber interface, are solved.
In some embodiments of the present disclosure, each of the first signals may include multichannel signal data. For example, in the above example application scenario, each network element configures an optical port to transmit and receive signals. Each optical port may include a plurality of channels, and the first signal may be formed of signal data of the plurality of channels of the optical port when the first signal enters or exits the optical port of each network element. Correspondingly, in step S102, sampling and converting each first signal to obtain a corresponding second signal may specifically include the following steps:
and respectively carrying out sampling conversion processing on the multi-channel signal data of each first signal to obtain corresponding second signals, wherein the second signals comprise corresponding converted multi-channel signal data.
Illustratively, as shown in FIG. 3, each optical port may include, but is not limited to, four channels, such as channel 1, channel 2, channel 3, and channel 4, and the corresponding first signal, such as a signal having a chip rate of 3.84Mcps, may include signal data for the four channels, such as the signal data for each of channel 1, channel 2, channel 3, and channel 4 shown in FIG. 3. Therefore, the signal data of each first signal, such as the channel 1, the channel 2, the channel 3 and the channel 4, may be subjected to sampling conversion processing respectively to obtain a corresponding second signal, where the second signal may include the signal data of the corresponding converted channel 1, channel 2, channel 3 and channel 4. Referring in conjunction to fig. 4, the sample-converted second signal 200 has a chip rate of 115.2Mcps, while the first signal 100 has a chip rate of 3.84Mcps, the chip rate of the second signal 200 being significantly greater than the chip rate of the first signal 100.
Optionally, based on the foregoing embodiments, in some embodiments of the present disclosure, the aligning and adding processing of each second signal after the sample conversion in step S103 to form a signal may specifically include the following steps:
step 1): and aligning the signal data of the multiple channels of each second signal by taking the signal data of any channel of each second signal as a reference.
Illustratively, referring to the illustration in fig. 5, each second signal has N channels of signal data, for each second signal, the remaining (N-1) channels of signal data may be aligned with the channel 1 of signal data, with reference to the channel 1 of signal data. In this embodiment, the value of N may be 4, but is not limited to this, which matches with the signal data of the four channels of the first signal.
Step 2): and adding the signal data of one channel corresponding to each second signal until the signal data of all channels corresponding to each second signal are added, so as to form one channel of signal.
For example, taking 2 second signals as an illustration, the 2 second signals each include signal data of N channels, then the signal data of the i (i=1, 2, …, N) th channel of one of the second signals and the signal data of the i th channel of the other second signal may be added until all of the signal data of N channels corresponding to the 2 second signals are added to form one signal after the addition processing.
For better illustrating the technical effects of the solution according to the foregoing embodiments of the present disclosure, please refer to fig. 3 and fig. 5 in comparison, when signals of the channels shown in fig. 3 are aligned, for example, when signals of the channel 1 at the current moment are aligned with reference to the signal of the channel 1, the signal delay of the channel 2 is L1, the signal delay of the channel 3 is L2, and the signal delay of the channel 4 is L3. In this example, L2 is greater than L3, and L3 is greater than L1. In contrast, when signal alignment is performed after the chip rate is increased according to the embodiment of the present disclosure, as shown in fig. 5, for example, when alignment is performed based on the channel 1, the delay of the signal of the channel N is L4, and in this embodiment, since signal alignment is performed after the chip rate of the signal is increased, L4 is much smaller than L1, that is, the signal alignment delay precision is higher. Therefore, in the signal processing method in the embodiment of the disclosure, in the delay measurement of combining signals of a plurality of network elements, the signal alignment and addition processing can be performed on the basis of increasing the chip rate, so that the signal alignment delay precision can be improved, the signal delay after addition is more accurate, and the situation that the corresponding signal is cut and cannot be normally processed due to the exceeding of the signal delay is greatly reduced. For example, signal alignment and combination processing can be realized within a range with small delay error of each signal, and the problems that the signal cannot be normally processed, such as normal demodulation, and the like in the follow-up process due to the fact that delay exceeds standard caused by certain factors, such as data jitter of an optical port, are eliminated.
Optionally, on the basis of any embodiment, in some embodiments of the disclosure, the method further includes the following steps:
step a): and when the signal data of each second signal corresponding to one channel is subjected to addition processing, judging whether the bit width of the signal data after the channel addition processing is larger than a preset bit width.
For example, when signal data of an i (i=1, 2, …, N) th channel of one second signal is added to signal data of an i th channel of another second signal, it is determined whether or not a bit width of the signal data after the i th channel addition processing is larger than a preset bit width. Wherein the predetermined bit width may be a maximum data bit width of the ith channel.
Step b): if yes, the signal data after the channel addition processing is subjected to cyclic bit cutting processing.
For example, when it is determined that the bit width of the signal data after the i-th channel addition processing described above is larger than the preset bit width, for example, cyclic bit cutting processing is performed on the signal data after the i-th channel addition processing.
The main function of the data truncating process is to realize the data bit width process, for example, the data width after the digital signal process is truncated for the subsequent process of the digital signal. The bit cutting process of the data mainly comprises, but is not limited to, high-order cutting of the signal output of the digital signal processing, low-order cutting of the signal output of the digital signal processing, and the like. In this embodiment, taking an example that each optical port contains 4 channels, that is, the first signal includes signal data of four channels, firstly, signal data of a channel (4 channels in total) corresponding to the 4 optical ports is sequentially taken out for addition, if each original channel is 16 bits of data bit width, when the signal data of the channel corresponding to the 4 optical ports is added, in order to preserve the data symbol bit width, the split data bit width will be greater than 16 bits, in order to prevent the effective signal from overflowing, the added data is ensured to be output with 16 bits of data bit width, and then cyclic bit cutting processing can be performed on the added signal data, for example, according to time sequence change, the bit cutting start bit dynamic changes in sequence during each bit cutting processing.
According to the scheme of the embodiment, through cyclic bit cutting processing instead of bit cutting processing of fixed data bits, influence of noise signals such as spurious signals and the like can be reduced, and the quality of signals obtained after combining processing is better.
Optionally, on the basis of the above embodiments, in some embodiments of the disclosure, the method may further include the following steps: before performing cyclic truncating processing on the signal data after the channel addition processing, a truncating start bit of the signal data after the channel addition processing is determined based on the configuration information.
For example, the configuration information may be a value of a register, for example, the truncated start bit of the signal data after the combined addition processing may be flexibly selected by configuring the value of the register, and if the configured value of the register is different, the truncated start bit of the signal data is different, so that the scheme of the embodiment may flexibly configure the truncated start bit, and the application range is wider.
Optionally, on the basis of any one of the foregoing embodiments, in some embodiments of the present disclosure, before performing the sampling conversion processing on each of the first signals in step S102 to obtain a corresponding second signal, the method may further include the following steps:
step i): and judging whether each first signal is a signal with the first chip rate in a preset counting period.
By way of example, it may be determined whether each first signal is a signal having a chip rate of 3.84Mcps for a preset count period.
Step ii): and if yes, sampling and converting each first signal to obtain a corresponding second signal.
For example, when each first signal is a signal with a chip rate of 3.84Mcps in the preset counting period, the method may jump to step S102 to perform sampling conversion processing on each first signal to obtain a corresponding second signal.
Step iii): if not, resetting the preset counting period, and re-counting to judge whether each first signal is a signal with the first chip rate in the preset counting period.
Illustratively, when each first signal is not a signal having a chip rate of 3.84Mcps at least once within a preset count period, the preset count period is cleared, and counting is repeated to determine whether each first signal is a signal having a chip rate of 3.84Mcps within the preset count period.
The above scheme of this embodiment may implement stability determination on the original first signal output by, for example, each optical port, where the first signal is a signal having a chip rate of 3.84Mcps in the preset counting period, and determine that the first signal is a stable periodic signal having a chip rate of 3.84Mcps, if at least one chip rate in the current determination is not 3.84Mcps, the first signal is not a stable periodic signal, and the counting period needs to be cleared and recounting all until the stable periodic signal appears in the preset counting period. The preset counting period may be set according to specific needs, which is not particularly limited. In this embodiment, the jitter problem of the signal can be substantially eliminated in advance by the above embodiment, and then the clock domain and the chip rate conversion of the original first signal can be completed, so as to prepare for the alignment and combining process based on the converted second signal. According to the scheme of the embodiment, the jitter problem of the signals is generally eliminated in advance, the alignment delay precision of the subsequent signals is further improved, the signal delay after subsequent addition is more accurate, and the delay precision of the signals is further improved as a whole.
Alternatively, based on any of the foregoing embodiments, in some embodiments of the present disclosure, the one signal formed by the adding process has the second chip rate, for example, the chip rate of the one signal is 115.2Mcps. Accordingly, the method may further comprise the steps of: and carrying out sampling conversion processing on the one path of signal so as to recover the sampled and converted one path of signal to have the first chip rate.
For example, as shown in fig. 2, the aligned and combined signals may be converted to a signal with a chip rate of 3.84Mcps, and the clock frequency of the corresponding matched clock signal is 184.32MHz, so that the processing complexity of the downstream processing module, such as a processor, may be reduced, thereby reducing the performance requirement of the processing module to save the device cost.
In one embodiment of the disclosure, as shown in fig. 2, a sampling rate conversion module is first used to convert a received signal with a clock frequency of 184.32MHz and a chip rate of 3.84Mcps into a signal with a clock frequency of 230.4MHz and a chip rate of 115.2Mcps, so as to increase the chip rate of the signal.
On the basis that the chip rate of the received signals is improved, signal data of channels corresponding to all the optical ports are subjected to operations such as addition, cyclic bit cutting and the like, so that the received signals of a plurality of optical ports are aligned, added and combined into one optical port signal.
And the aligned and combined signals are recovered into a path of signals with the clock frequency of 184.32MHz and the chip rate of 3.84Mcps through a sampling rate conversion module, and the path of signals can reach an upper physical layer for demodulation after being aligned with an air interface frame head. The signal with relatively higher chip rate can improve the time delay precision of signal alignment of each optical port, and the alignment of signal data is added under higher precision time delay, so that the signal time delay precision after combining can be improved, and the problem that the signal is cut and cannot be demodulated normally due to the fact that the time delay exceeds standard caused by data jitter of certain optical ports is solved. In addition, the processing complexity of the downstream processing unit can be reduced by recovering the signal with lower chip rate.
The scheme of the embodiment adopts the signals with relatively higher chip rate to improve the time delay precision of the signal alignment of each optical port, and performs alignment addition of signal data under higher precision time delay, so that the time delay precision of the signals after combining can be improved, and the time delay error caused by the data jitter of individual optical ports after combining is reduced, thereby causing the problems such as uplink demodulation failure and the like. That is, the scheme of the embodiment improves the signal sampling rate and then performs alignment addition, so that the problem that the signal alignment addition time delay precision is poor at the original chip rate of, for example, 3.84Mcps is effectively solved, and the signal alignment time delay precision is improved by approximately 30 times after the signal alignment addition time delay precision is processed through the scheme of the embodiment through experiments.
It should be noted that although the steps of the methods of the present disclosure are illustrated in the accompanying drawings in a particular order, this does not require or imply that the steps must be performed in that particular order or that all of the illustrated steps be performed in order to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step to perform, and/or one step decomposed into multiple steps to perform, etc. In addition, it is also readily understood that these steps may be performed synchronously or asynchronously, for example, in a plurality of modules/processes/threads.
Based on the same concept, the embodiments of the present disclosure also provide a signal processing apparatus, such as the signal processing apparatus 60 shown in fig. 6, which may include a signal acquisition module 601, a signal conversion module 602, and a signal combining module 603, wherein:
the signal acquisition module 601 is configured to acquire first signals output by a plurality of network elements, where each of the first signals is from a same source signal and has a first chip rate.
The signal conversion module 602 is configured to perform sampling conversion processing on each of the first signals to obtain corresponding second signals, where each of the second signals has a second chip rate, and the second chip rate is greater than the first chip rate.
The signal combining module 603 is configured to align, add and process each of the second signals after sampling and converting to form a signal.
In the signal processing device 60 in the embodiment of the present disclosure, in the delay measurement of combining signals of multiple network elements, the signal alignment addition processing can be performed on the basis of increasing the chip rate, so that the signal alignment delay precision can be improved, the signal delay after addition is more accurate, and further the signal alignment combination processing can be performed within a range with small delay error of each path of signal, so that the problems that the signal cannot be normally processed subsequently due to the delay exceeding caused by certain factors are solved.
Optionally, in some embodiments of the disclosure, each of the first signals includes multichannel signal data. The signal conversion module 602 performs sampling conversion processing on each of the first signals to obtain corresponding second signals, and specifically includes: and respectively carrying out sampling conversion processing on the multi-channel signal data of each first signal to obtain a corresponding second signal, wherein the second signal comprises the corresponding converted multi-channel signal data.
Optionally, in some embodiments of the present disclosure, the signal combining module 603 aligns and adds each of the second signals after the sampling conversion to form a signal, which specifically includes: aligning the signal data of the multiple channels of each second signal with the signal data of any channel of each second signal as a reference; and adding the signal data of one channel corresponding to each second signal until the signal data of all channels corresponding to each second signal are added, so as to form one channel of signal.
Optionally, in some embodiments of the present disclosure, the signal combining module 603 is further configured to: when adding signal data of each second signal corresponding to one channel, judging whether the bit width of the signal data after the channel adding process is larger than a preset bit width; if yes, the signal data after the channel addition processing is subjected to cyclic bit cutting processing.
Optionally, in some embodiments of the present disclosure, the signal combining module 603 is further configured to: before performing cyclic truncating processing on the signal data after the channel addition processing, a truncating start bit of the signal data after the channel addition processing is determined based on the configuration information.
Optionally, in some embodiments of the present disclosure, the apparatus may further include a signal determining module, configured to determine, before the signal converting module 602 performs sampling conversion processing on each of the first signals to obtain a corresponding second signal, whether each of the first signals is a signal having the first chip rate in a preset counting period; if yes, the signal conversion module 602 performs sampling conversion processing on each first signal to obtain a corresponding second signal; if not, resetting the preset counting period, and re-counting to judge whether each first signal is a signal with the first chip rate in the preset counting period.
Alternatively, in some embodiments of the present disclosure, the first signal may be a carrier signal received by the receiving end, or a carrier signal to be transmitted by the transmitting end, but is not limited thereto.
Optionally, in some embodiments of the disclosure, the one-way signal formed by the adding process has the second chip rate. The apparatus may further include a signal recovery module configured to perform sampling conversion processing on the one signal, so as to recover the sampled and converted one signal to have the first chip rate.
In a specific application scenario, the above signal processing device 60 may be implemented on a programmable logic device, such as an FPGA, so that the processing cost of the peripheral chip may be reduced.
In addition, some embodiments of the present disclosure provide a communication system, such as the communication system shown in fig. 7, the communication system 70 may include the signal processing apparatus 60 described in any of the embodiments above. For example, the communication system 70 may include a plurality of network elements (not shown), and the signal processing device 60 may be respectively communicatively connected to the plurality of network elements.
In the above-mentioned communication system 70 in the embodiment of the disclosure, in the delay measurement of combining signals of a plurality of network elements, the signal alignment addition processing can be performed on the basis of increasing the chip rate, so that the signal alignment delay precision can be improved, the signal delay after addition is more accurate, and further the signal alignment combination processing can be performed within a range with small delay errors of each path of signal, so that the problems that the signal cannot be normally processed subsequently due to the delay exceeding caused by certain factors are solved.
The specific manner in which the respective modules perform the operations and the corresponding technical effects thereof in the above-described apparatuses and systems in the embodiments are described in detail in the embodiments related to the method, and will not be described in detail herein.
It should be noted that although in the above detailed description several modules or units of a device for action execution are mentioned, such a division is not mandatory. Indeed, the features and functionality of two or more modules or units described above may be embodied in one module or unit in accordance with embodiments of the present disclosure. Conversely, the features and functions of one module or unit described above may be further divided into a plurality of modules or units to be embodied. The components shown as modules or units may or may not be physical units, may be located in one place, or may be distributed across multiple network elements. Some or all of the modules can be selected according to actual needs to achieve the purpose of the wood disclosure scheme. Those of ordinary skill in the art will understand and implement the present invention without undue burden.
The disclosed embodiments also provide a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the signal processing method of:
acquiring first signals output by a plurality of network elements, wherein each first signal is from the same source signal and has a first chip rate;
sampling and converting each first signal to obtain a corresponding second signal, wherein each second signal has a second chip rate, and the second chip rate is larger than the first chip rate;
and aligning each second signal after sampling conversion, and then adding to form a signal.
Optionally, in some embodiments of the disclosure, each of the first signals includes multichannel signal data. Correspondingly, the sampling conversion processing is performed on each first signal to obtain a corresponding second signal, which includes:
and respectively carrying out sampling conversion processing on the multi-channel signal data of each first signal to obtain a corresponding second signal, wherein the second signal comprises the corresponding converted multi-channel signal data.
Optionally, in some embodiments of the disclosure, the aligning and adding each of the second signals after the sampling conversion to form a signal includes:
Aligning the signal data of the multiple channels of each second signal with the signal data of any channel of each second signal as a reference;
and adding the signal data of one channel corresponding to each second signal until the signal data of all channels corresponding to each second signal are added, so as to form one channel of signal.
Optionally, in some embodiments of the present disclosure, the method further comprises the steps of:
when adding signal data of each second signal corresponding to one channel, judging whether the bit width of the signal data after the channel adding process is larger than a preset bit width;
if yes, the signal data after the channel addition processing is subjected to cyclic bit cutting processing.
Optionally, in some embodiments of the present disclosure, the method further comprises the steps of:
before performing cyclic truncating processing on the signal data after the channel addition processing, a truncating start bit of the signal data after the channel addition processing is determined based on the configuration information.
Optionally, in some embodiments of the present disclosure, before the performing sampling conversion processing on each first signal to obtain a corresponding second signal, the method further includes the following steps:
Judging whether each first signal is a signal with the first chip rate in a preset counting period;
if yes, sampling and converting each first signal to obtain a corresponding second signal;
if not, resetting the preset counting period, and re-counting to judge whether each first signal is a signal with the first chip rate in the preset counting period.
Optionally, in some embodiments of the disclosure, the first signal is a carrier signal received by a receiving end or a carrier signal to be transmitted by a transmitting end.
Optionally, in some embodiments of the disclosure, the one-way signal formed by the adding process has the second chip rate; the method further comprises the steps of:
and carrying out sampling conversion processing on the one path of signal so as to recover the sampled and converted one path of signal to have the first chip rate.
The above-described readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or a combination of any of the foregoing. More specific examples (a non-exhaustive list) of the readable storage medium would include the following: an electrical connection having one or more wires, a portable disk, a hard disk, random Access Memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
The computer readable storage medium may include a data signal propagated in baseband or as part of a carrier wave, with readable program code embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing. A readable storage medium may also be any readable medium that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. Program code embodied on a readable storage medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.
The embodiment of the disclosure further provides an electronic device, as shown in fig. 8, including a processor 802 and a memory 801, where the memory 801 is configured to store executable instructions of the processor 802. Wherein the processor 802 is configured to perform the steps of the signal processing method described in any of the above embodiments, e.g. the steps of the signal processing method shown in fig. 1, via execution of the executable instructions.
In some embodiments, the electronic device may be a base station, but is not limited thereto. It should be appreciated that although not shown, electronic device 80 may employ other hardware and/or software modules, including, but not limited to: buses, microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, data backup storage systems, and the like.
From the above description of embodiments, those skilled in the art will readily appreciate that the example embodiments described herein may be implemented in software, or may be implemented in software in combination with the necessary hardware. Thus, the technical solution according to the embodiments of the present disclosure may be embodied in the form of a software product, which may be stored in a non-volatile storage medium (may be a CD-ROM, a usb disk, a mobile hard disk, etc.) or on a network, including several instructions to cause a computing device (may be a personal computer, a base station, or a network device, etc.) or to perform the steps of the above-described signal processing method according to the embodiments of the present disclosure.
It should be noted that in this document, relational terms such as "first" and "second" and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The foregoing is merely a specific embodiment of the disclosure to enable one skilled in the art to understand or practice the disclosure. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the disclosure. Thus, the present disclosure is not intended to be limited to the embodiments shown and described herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (12)
1. A signal processing method, comprising:
acquiring first signals output by a plurality of network elements, wherein each first signal is from the same source signal and has a first chip rate;
judging whether each first signal is a signal with the first chip rate in a preset counting period;
if yes, sampling and converting each first signal to obtain a corresponding second signal, wherein each second signal has a second chip rate, and the second chip rate is larger than the first chip rate;
and aligning each second signal after sampling conversion, and then adding to form a signal.
2. The signal processing method of claim 1, wherein each of the first signals comprises multichannel signal data;
the step of performing sampling conversion processing on each first signal to obtain a corresponding second signal includes:
and respectively carrying out sampling conversion processing on the multi-channel signal data of each first signal to obtain corresponding second signals, wherein the second signals comprise corresponding converted multi-channel signal data.
3. The signal processing method according to claim 2, wherein the aligning and adding each of the second signals after the sample conversion to form a signal includes:
aligning the signal data of the multiple channels of each second signal with the signal data of any channel of each second signal as a reference;
and adding the signal data of one channel corresponding to each second signal until the signal data of all channels corresponding to each second signal are added, so as to form one channel of signal.
4. A signal processing method according to claim 3, further comprising:
when adding signal data of each second signal corresponding to one channel, judging whether the bit width of the signal data after the channel adding process is larger than a preset bit width;
If yes, the signal data after the channel addition processing is subjected to cyclic bit cutting processing.
5. The signal processing method of claim 4, further comprising:
before performing cyclic truncating processing on the signal data after the channel addition processing, a truncating start bit of the signal data after the channel addition processing is determined based on the configuration information.
6. The signal processing method according to any one of claims 1 to 5, wherein after said determining whether each of said first signals is a signal having said first chip rate within a preset count period, said method further comprises:
if not, resetting the preset counting period, and re-counting to judge whether each first signal is a signal with the first chip rate in the preset counting period.
7. The signal processing method according to claim 6, wherein the first signal is a carrier signal received by a receiving end or a carrier signal to be transmitted by a transmitting end.
8. The signal processing method according to claim 6, wherein the one-way signal formed by the addition processing has the second chip rate; the method further comprises the steps of:
And carrying out sampling conversion processing on the one path of signal so as to recover the sampled and converted one path of signal to have the first chip rate.
9. A signal processing apparatus, comprising:
the signal acquisition module is used for acquiring first signals output by a plurality of network elements, wherein each first signal is from the same source signal and has a first chip rate;
the signal conversion module is used for carrying out sampling conversion processing on each first signal to obtain corresponding second signals, and each second signal has a second chip rate which is larger than the first chip rate;
the signal combining module is used for aligning each second signal after sampling conversion and then adding the second signals to form a path of signal;
the apparatus further comprises:
the signal judging module is used for judging whether each first signal is a signal with the first chip rate in a preset counting period; if yes, the signal conversion module performs sampling conversion processing on each first signal to obtain a corresponding second signal.
10. A communication system comprising the signal processing apparatus of claim 9.
11. A computer-readable storage medium, on which a computer program is stored, characterized in that the computer program, when being executed by a processor, implements the steps of the signal processing method according to any one of claims 1 to 8.
12. An electronic device, comprising:
a processor; and
a memory for storing executable instructions of the processor;
wherein the processor is configured to perform the steps of the signal processing method of any of claims 1 to 8 via execution of the executable instructions.
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