CN104768189A - Real-time communication method and system between DSP and FPGA - Google Patents
Real-time communication method and system between DSP and FPGA Download PDFInfo
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Abstract
The invention discloses a real-time communication method and system between a DSP and an FPGA. The real-time communication method between the DSP and the FPGA includes the steps that all data, stored in the DSP, to be transmitted are moved and stored in a data transmitting register every time one transmitting frame synchronizing signal of the FPGA is received, the data, temporarily stored in the data transmitting register, to be transmitted are transmitted to the data transmitting flow of the FPGA at the same time when the next transmitting frame synchronizing signal of the FPGA is received, one part of received data of a specific data length, which are input by the FPGA at the same time, are received every time one receiving frame synchronizing signal of the FPGA is received, the part of received data are stored in a data receiving register, and accordingly the part of received data stored in the data receiving register are transmitted to the data receiving flow of the DSP. By means of the real-time communication method and system between the DSP and the FPGA, the data exchange rate between the DSP and the FPGA is greatly increased, bothway, real-time and efficient transmission of the data between the DSP and the FPGA is achieved, and the requirement for acquiring instant messaging services of users is met.
Description
Technical field
The present invention relates to communication technical field, more particularly, relate to the real-time communication method between a kind of DSP and FPGA and real-time communication system.
Background technology
In data processing chip field, DSP has high data processing rate, fpga chip, because of can overprogram and have higher flexibility, adopts in the industry the mode combined by DSP and FPGA to build the signal processing system that has high data-handling efficiency usually.Because there is strict restriction in the processing time of communication system (such as GSM, TD-SCDMA) to transmission data, to reaching the real-time process of transmission data, meet the requirement of user for instant messaging.And in above-mentioned signal processing system, still there is certain delay in the data exchange process between DSP and FPGA.Be limited to the exchanges data efficiency between DSP and FPGA, above-mentioned signal processing system is still difficult to the requirement meeting user's instant messaging.
Summary of the invention
The technical problem to be solved in the present invention is the above-mentioned defect for prior art, provides a kind of and realizes that data are two-way between DSP and FPGA, real-time, real-time communication method between DSP and FPGA of high efficiency of transmission and real-time communication system.
The technical solution adopted for the present invention to solve the technical problems is: construct the real-time communication method between a kind of DSP and FPGA, comprising:
When often receiving a transmission frame synchronizing signal of FPGA, to the data-moving all to be sent of DSP be stored in and deposit in data transmitter register, and the data to be sent being temporary in data transmitter register will be sent to the data transmission flow of FPGA when receiving the next transmission frame synchronizing signal of FPGA simultaneously;
And when often receiving the received frame synchronizing signal of FPGA, the part receiving the specific data length simultaneously inputted by FPGA receives data, this part is received deposit data in data receive register, and then this part depositing in data receive register is received the data receiver flow process that data are sent to DSP.
State in the real-time communication method between DSP and FPGA on the invention, described in be applied to DSP and FPGA data transmission flow comprise the steps:
When S1, McBSP carry out real time scan to FSX pin and judge a transmission frame synchronizing signal that it receives from FPGA, trigger and perform the first data-moving operation once moving to data transmitter register for a part of data of specific data length in the data to be sent of the RAM by being stored in DSP;
When first data-moving operation is finished by S2, McBSP, then this part is sent data and move to inner buffer from data transmitter register;
S3, judge whether the data to be sent being stored in RAM have been moved complete all; As complete in data-moving to be sent, then perform next step S4;
The data all to be sent being temporary in buffer memory are sent to FPGA when carrying out real time scan to FSX pin and judge next transmission frame synchronizing signal that it receives from FPGA by S4, McBSP simultaneously.
State in the real-time communication method between DSP and FPGA on the invention, trigger described in described step S1 and perform and once comprise for the step of the first data-moving operation a part of data of designated length in the data to be sent being stored in RAM being moved to data transmitter register:
S11, McBSP receive a transmission frame synchronizing signal of FPGA during by FSX pin, trigger and generate the first data-moving instruction, and sending the first data-moving instruction to memory management module;
S12, memory management module receive the first data-moving instruction, and the part choosing specific data length from the data to be sent being stored in RAM sends data, and this part is sent data conversion storage to data transmitter register.
State in the real-time communication method between DSP and FPGA on the invention, described step S3 also comprises the steps:
S31, as judged, the data to be sent in RAM are not yet moved complete, then trigger and perform the first data-moving operation, and when the first data-moving operation is finished, return step S2.
State in the real-time communication method between DSP and FPGA on the invention, also comprise the steps: after described step S4
S5, stop this secondary data transmission flow, produce interrupt signal, at intercourse, reprovision is carried out to the parameters of memory management module, and when the operation of memory management module parameter reconfiguration is finished, return step S1.
State in the real-time communication method between DSP and FPGA on the invention, described in be applied to DSP and FPGA data receiver flow process comprise the steps:
When S1 ', McBSP carry out real time scan to FSR pin and a received frame synchronizing signal from FPGA detected, receive simultaneously and receive data from a part for the specific data length of DR pin input, and this part reception data are stored in data receive register;
S2 ', McBSP, while this part reception data are stored in data receive register, perform and this part are received the second data-moving operation that data move to DSP.
State in the real-time communication method between DSP and FPGA on the invention, the step triggering and perform the second data-moving operation this part reception data being moved to DSP described in described step S2 ' comprises:
S21 ', McBSP are when this part receives data stored in data receive register, trigger and generate and be used for this part being received data move to RAM the second data-moving instruction from data receive register, and send the second data-moving instruction to memory management module;
When S22 ', memory management module receive the second data-moving instruction, this part being temporary in data receive register is received data-moving and dumps to RAM.
State in the real-time communication method between DSP and FPGA on the invention, also comprise the steps: afterwards at described step S22 '
S23 ', real time scan is carried out to judge whether to continue to receive the received frame synchronizing signal from FPGA to FSR pin; Receive the received frame synchronizing signal from FPGA as continued, then return step S1 '; Otherwise, stop this secondary data to receive flow process.
State in the real-time communication method between DSP and FPGA on the invention, also comprise the steps: afterwards at described step S23 '
S24 ', generation interrupt signal, carry out reprovision at intercourse to the parameters of memory management module, and when the parameter reconfiguration operation of memory management module is finished, return step S1 '.
The present invention also constructs the real-time communication system between a kind of DSP and FPGA, comprise DSP and FPGA, described DSP is configured with at least one McBSP and is established a communications link by McBSP and described FPGA, and described McBSP comprises data transmitter register and data receive register;
When McBSP described in each is all for receiving the transmission frame synchronizing signal of described FPGA, to the data-moving all to be sent of described DSP be stored in and deposit in described data transmitter register, and when receiving the next transmission frame synchronizing signal provided by described FPGA, the data to be sent be temporary in described data transmitter register being sent to described FPGA simultaneously;
McBSP described in each is also for when often receiving a received frame synchronizing signal of described FPGA, the part receiving the specific data length simultaneously inputted by described FPGA receives data, this part is received deposit data in described data receive register, and then this part reception data depositing in described data receive register are sent to described DSP.
Implement the real-time communication method between DSP and FPGA of the present invention and real-time communication system, following beneficial effect can be realized:
1, the present invention is using the McBSP in DSP as the data transmit-receive terminal between DSP and FPGA, drastically increases the exchanges data efficiency between DSP and the FPGA of outside.
2, EDMA technology is applied in DSP between McBSP and RAM exchanges data by the present invention, have employed the data synchronization processing mechanism of McBSP and memory management module simultaneously.On the one hand, the work of the memory management module in DSP, without the need to taking the processor resource of DSP, reduces the operating load of DSP; On the other hand, the above-mentioned data synchronization processing mechanism of the present invention drastically increases the data exchange rate between DSP inner member (i.e. McBSP and RAM), achieves two-way, the real-time Transmission of data between DSP and FPGA.
3, arrange interruption controlling mechanism in the data transmit-receive process of the present invention between DSP/FPGA, this interruption controlling mechanism can closely be connected with the data handling procedure of DSP by the present invention, to be adapted to require harsh communication system to the data process limited.
Accompanying drawing explanation
Fig. 1 is the structured flowchart of the real-time communication system between first DSP and FPGA that preferred embodiment provides of the present invention;
Fig. 2 is the structured flowchart of the DSP of the real-time communication system between DSP and the FPGA shown in Fig. 1;
Fig. 3 is the structured flowchart of the McBSP of the DSP shown in Fig. 2;
Fig. 4 is the flow chart of the data transmission flow from DSP to FPGA comprised in the real-time communication method between the present invention second DSP and FPGA that preferred embodiment provides;
Fig. 5 is the flow chart of the data receiver flow process from FPGA to DSP comprised in the real-time communication method between the present invention the 3rd DSP and FPGA that preferred embodiment provides.
Embodiment
There is certain data transmission delay to solve between existing DSP100 and the FPGA200 being applied to the signal processing system of communication base station, cause the defect that communication base station cannot provide instant messaging to serve for user, innovative point of the present invention is:
1, by McBSP101 (the Multichannel Buffered Serial Port in DSP100, i.e. multichannel buffer serial port) as the data transmit-receive terminal between communicating pair DSP100 and FPGA200, improve the exchanges data efficiency between DSP100 and the FPGA200 of outside.
2, EDMA (Enhanced Direct MemoryAccess) technology is applied in DSP100 between McBSP101 and RAM103 exchanges data by the present invention, have employed the data synchronization processing mechanism of McBSP101 and memory management module 102 simultaneously.
This data synchronization processing mechanism is as follows: in the data transmission flow from DSP100 to FPGA200, McBSP101 is once a transmission frame synchronizing signal from FPGA200 be detected, then first the data to be sent in RAM103 are all moved to inner buffer, trigger and generate an EDMA event again, thus the data to be sent being temporary in inner buffer are all dumped to FPGA200; In the data receiver flow process from FPGA200 to DSP100, when McBSP101 often detects a received frame synchronizing signal from FPGA200, the part that receive is provided by FPGA200 simultaneously receives data, and trigger and generate an EDMA event, thus this part is received data dump to DSP100 RAM103 from McBSP101.
Thus, on the one hand, the work of the memory management module 102 of DSP100 is without the need to taking the processor resource of DSP100, reduce the operating load of DSP100, on the other hand, the data synchronization processing mechanism that the present invention is applied to DSP100 drastically increases the data exchange rate between DSP100 inner member (i.e. McBSP101 and RAM103), reaches the technique effect of data real-time Transmission between DSP100 and FPGA200.
3, in the data transmit-receive process between DSP100/FPGA200, interruption controlling mechanism is set, and is closely connected with the data handling procedure of DSP100 by this interruption controlling mechanism, to be adapted to require harsh communication system to the data process limited.
Owing to present invention employs the McBSP101 in DSP100 as the data transmit-receive terminal between communicating pair DSP100 and FPGA200, and EDMA technology is applied to the design of the exchanges data between DSP100 inner member, so there is certain data transmission delay between DSP100 and the FPGA200 solving in prior art the signal processing system being applied to communication base station, cause the technical problem that communication base station cannot provide instant messaging to serve for user, achieve two-way between DSP100 and FPGA200 of data, in real time, high efficiency of transmission, and achieve the object providing instant messaging to serve for user by base station.
Below in conjunction with drawings and Examples, the invention will be further described:
First, for first better embodiment of the present invention, the system architecture that the 3 couples of the present invention of 1 to accompanying drawing are applied to the communication system of DSP100 and FPGA200 is by reference to the accompanying drawings described:
As shown in Figure 1, DSP100 (Digital Signal Processor is applied in the present invention, i.e. digital signal processor) and FPGA200 (Field-Programable Gate Array, i.e. field programmable gate array) communication system in, this DSP100 is configured with at least one McBSP101 (Multichannel Buffered Serial Port, i.e. multichannel buffer serial port), and established a communications link by McBSP101 and FPGA200.Each McBSP101 includes data transmitter register 1019 (DXR) and data receive register 1018 (DRR).
When each McBSP101 above-mentioned is all for receiving the transmission frame synchronizing signal of FPGA200, the data to be sent being stored in DSP100 all moved and deposits in data transmitter register 1019, and when receiving the next transmission frame synchronizing signal of FPGA200, the data all to be sent be temporary in data transmitter register 1019 being sent to FPGA200 simultaneously.
Each McBSP101 above-mentioned is also for when often receiving a received frame synchronizing signal from FPGA200, the part receiving the specific data length simultaneously inputted by FPGA200 receives data, this part is received deposit data in data receive register 1018, and then this part reception data depositing in data receive register 1018 are sent to DSP100.
As shown in Figure 2, in the present invention, DSP100 comprises at least one McBSP101, memory management module 102 and the RAM103 (RandomAccess Memory) that connect successively.
This RAM103 is for storing data to be sent and the reception data from FPGA200.
When this McBSP101 is for receiving a transmission frame synchronizing signal from FPGA200, triggers and generating the first data-moving instruction, and sending the first data-moving instruction to memory management module 102.
This memory management module 102 is for performing the first data-moving instruction, the part choosing specific data length from the data to be sent being stored in RAM103 sends data (i.e. 32bit data), and by this part transmission data-moving and the data transmitter register 1019 depositing in McBSP101.
When this McBSP101 is also for judging that this part transmission data move to buffer memory, triggers and generating the first data-moving instruction, and sending the first data-moving instruction to memory management module 102.
This McBSP101 also moves to buffer memory for this part being temporary in data transmitter register 1019 is sent data, and when the data to be sent judging in RAM103 have moved to buffer memory all, the data to be sent in buffer memory is sent to FPGA200 together.
This part also for being received the received frame synchronizing signal inputted by FPGA200 and the part being received the specific data length inputted by FPGA200 by DR pin reception data (i.e. 32bit data) by FSR pin simultaneously, and is received data temporary storage in data receive register 1018 by this McBSP101.
This processing module, also for generating the second data-moving instruction, controlling memory management module 102 and this part being temporary in data receive register 1018 is received data-moving and dumps to RAM103.
EDMA (Enhanced Direct Memory Access) technology has been applied to the data-moving process in DSP100 between McBSP101 and RAM103 by the present invention, substantially increases the exchanges data efficiency of DSP100 inner member.
As shown in Figure 3, McBSP101 of the present invention comprises FSR pin one 011 (accepting frame synchronization), FSX pin one 012 (transmission frame is synchronous), DR pin one 013 (Serial data receiving), DX pin one 014 (serial data transmission), CLKR pin one 015 (receive clock), CLKX pin one 016 (tranmitting data register), buffer memory 1017, data receive register 1018 (DRR) and data transmitter register 1019 (DXR).
Below will for second better embodiment of the present invention, the data transmission flow of composition graphs 4 couples of the present invention from DSP100 to FPGA200 is described:
As shown in Figure 4, in step S101, McBSP101 wait-receiving mode is from the tranmitting data register signal of FPGA200 and transmission frame synchronizing signal.
In step s 102, McBSP101 carries out real time scan to judge whether it receives tranmitting data register signal from FPGA200 and transmission frame synchronizing signal to FSX pin one 012.As McBSP101 receives the transmission frame synchronizing signal of FPGA200, then perform step S103.Otherwise, return previous step S101.
In step s 103, McBSP101 triggers and generates the first data-moving instruction, and sends the first data-moving instruction to memory management module 102.
In step S104, memory management module 102 receives the first data-moving instruction, the part choosing specific data length from the data to be sent being stored in RAM103 sends data (i.e. the transmission data of 32bit), and by the transmission data-moving of this 32bit and the data transmitter register 1019 being stored into McBSP101.
In step S105, the transmission data being temporary in this 32bit of data transmitter register 1019 are moved to its inner buffer by McBSP101.
In step s 106, by memory management module 102, McBSP101 judges whether the data to be sent in RAM103 have moved to the buffer memory of McBSP101 all.As the data to be sent in RAM103 all do not move to the buffer memory of McBSP101, then circulation performs step S103 to step S105, until the data to be sent in RAM103 all move to the inner buffer of McBSP101.Otherwise, perform next step S107.
In step s 107, the data that McBSP101 receives DSP100 send instruction, and the data to be sent being temporary in buffer memory are sent to FPGA200 together.
In step S108, real-time communication system between DSP100 and FPGA200 of the present invention completes the data transmit operation data to be sent of this batch (amounting to the data of 16 32bit) being sent to FPGA200 from DSP100, stop the data transmission flow from DSP100 to FPGA200, and produce interrupt signal by McBSP101.
In step S109, DSP100 reconfigures at the parameters of intercourse to memory management module 102, so that the carrying out smoothly of the data transmission flow of the next one from DSP100 to FPGA200.
Rebound step S101 after step S109 is finished.
Below will for the 3rd better embodiment of the present invention, the data receiver flow process of composition graphs 5 couples of the present invention from FPGA200 to DSP100 is described:
As shown in Figure 5, in step S101 ', McBSP101 wait-receiving mode is from the receive clock signal of FPGA200 and received frame synchronizing signal.
In step S102 ', McBSP101 carries out real time scan to judge whether it receives a received frame synchronizing signal from FPGA200 to FSR pin one 011.As McBSP101 does not receive receive clock from FPGA200 and received frame synchronizing signal, then return step S101 '.As McBSP101 has received receive clock from FPGA200 and received frame synchronizing signal, then perform next step S103 '.
In step S103 ', McBSP101 receives the specific data length simultaneously inputted by a FPGA200 part by DR pin receives data (namely 32bit receives data).
In step S104 ', this 32bit is received data-moving and keeps in data receive register 1018 by McBSP101.
In step S105 ', McBSP101 triggers and generates and is used for this 32bit being temporary in data receive register 1018 to receive the second data-moving instruction that data move to RAM103, and sends the second data-moving instruction to memory management module 102.
In step S106 ', memory management module 102 receives the second data-moving instruction, and this 32bit being temporary in data receive register 1018 is received data-moving and dumps to RAM103.
In step S107 ', McBSP101 carries out real time scan to judge whether it receives the next received frame synchronizing signal from FPGA200 to FSR pin.As McBSP101 receives the next received frame synchronizing signal from FPGA200, then circulation performs step S103 ' to S107 '.Otherwise, perform next step S108 '.
In step S108 ', real-time communication system between DSP100 and FPGA200 of the present invention completes the data reception operation data to be received of this batch (amounting to 156 32bit data) being sent to DSP100 from FPGA200, stop this secondary data from FPGA200 to DSP100 to receive flow process, and produce interrupt signal by FPGA200.
In step S109 ', DSP100 reconfigures at the parameters of intercourse to memory management module 102, so that the carrying out smoothly of the data receiver flow process of the next one from FPGA200 to DSP100.
Rebound step S101 ' after step S109 ' is finished.
By reference to the accompanying drawings embodiments of the invention are described above; but the present invention is not limited to above-mentioned embodiment; above-mentioned embodiment is only schematic; instead of it is restrictive; those of ordinary skill in the art is under enlightenment of the present invention; do not departing under the ambit that present inventive concept and claim protect, also can make a lot of form, these all belong within protection of the present invention.
Claims (10)
1. the real-time communication method between DSP and FPGA, is characterized in that, comprising:
When often receiving a transmission frame synchronizing signal of FPGA, to the data-moving all to be sent of DSP be stored in and deposit in data transmitter register, and the data to be sent being temporary in data transmitter register will be sent to the data transmission flow of FPGA when receiving the next transmission frame synchronizing signal of FPGA simultaneously;
And when often receiving the received frame synchronizing signal of FPGA, the part receiving the specific data length simultaneously inputted by FPGA receives data, this part is received deposit data in data receive register, and then this part depositing in data receive register is received the data receiver flow process that data are sent to DSP.
2. the real-time communication method between DSP and FPGA according to claim 1, is characterized in that, described in be applied to DSP and FPGA data transmission flow comprise the steps:
When S1, McBSP carry out real time scan to FSX pin and judge a transmission frame synchronizing signal that it receives from FPGA, trigger and perform the first data-moving operation once moving to data transmitter register for a part of data of specific data length in the data to be sent of the RAM by being stored in DSP;
When first data-moving operation is finished by S2, McBSP, then this part is sent data and move to inner buffer from data transmitter register;
S3, judge whether the data to be sent being stored in RAM have been moved complete all; As complete in data-moving to be sent, then perform next step S4;
The data all to be sent being temporary in buffer memory are sent to FPGA when carrying out real time scan to FSX pin and judge next transmission frame synchronizing signal that it receives from FPGA by S4, McBSP simultaneously.
3. the real-time communication method between DSP and FPGA according to claim 2, it is characterized in that, trigger described in described step S1 and perform and once comprise for the step of the first data-moving operation a part of data of designated length in the data to be sent being stored in RAM being moved to data transmitter register:
S11, McBSP receive a transmission frame synchronizing signal of FPGA during by FSX pin, trigger and generate the first data-moving instruction, and sending the first data-moving instruction to memory management module;
S12, memory management module receive the first data-moving instruction, and the part choosing specific data length from the data to be sent being stored in RAM sends data, and this part is sent data conversion storage to data transmitter register.
4. the real-time communication method between DSP and FPGA according to claim 2, is characterized in that, described step S3 also comprises the steps:
S31, as judged, the data to be sent in RAM are not yet moved complete, then trigger and perform the first data-moving operation, and when the first data-moving operation is finished, return step S2.
5. the real-time communication method between DSP and FPGA according to claim 2, is characterized in that, also comprises the steps: after described step S4
S5, stop this secondary data transmission flow, produce interrupt signal, at intercourse, reprovision is carried out to the parameters of memory management module, and when the operation of memory management module parameter reconfiguration is finished, return step S1.
6. the real-time communication method between DSP and FPGA according to claim 1, is characterized in that, described in be applied to DSP and FPGA data receiver flow process comprise the steps:
When S1 ', McBSP carry out real time scan to FSR pin and a received frame synchronizing signal from FPGA detected, receive simultaneously and receive data from a part for the specific data length of DR pin input, and this part reception data are stored in data receive register;
S2 ', McBSP, while this part reception data are stored in data receive register, perform and this part are received the second data-moving operation that data move to DSP.
7. the real-time communication method between DSP and FPGA according to claim 5, is characterized in that, the step triggering and perform the second data-moving operation this part reception data being moved to DSP described in described step S2 ' comprises:
S21 ', McBSP, when this part receives data stored in data receive register, trigger and generate the second data-moving instruction being used for this part reception data being moved to RAM from data receive register, and send the second data-moving instruction to memory management module;
When S22 ', memory management module receive the second data-moving instruction, this part being temporary in data receive register is received data-moving and dumps to RAM.
8. the real-time communication method between DSP and FPGA according to claim 5, is characterized in that, also comprises the steps: afterwards at described step S22 '
S23 ', real time scan is carried out to judge whether to continue to receive the received frame synchronizing signal from FPGA to FSR pin; Receive the received frame synchronizing signal from FPGA as continued, then return step S1 '; Otherwise, stop this secondary data to receive flow process.
9. the real-time communication method between DSP and FPGA according to claim 7, is characterized in that, also comprises the steps: afterwards at described step S23 '
S24 ', generation interrupt signal, carry out reprovision at intercourse to the parameters of memory management module, and when the parameter reconfiguration operation of memory management module is finished, return step S1 '.
10. an application is as the real-time communication system of the real-time communication method between DSP and FPGA as described in arbitrary in claim 1 to 9, comprise DSP and FPGA, described DSP is configured with at least one McBSP and is established a communications link by McBSP and described FPGA, it is characterized in that, described McBSP comprises data transmitter register and data receive register;
When McBSP described in each is all for receiving the transmission frame synchronizing signal of described FPGA, to the data-moving all to be sent of described DSP be stored in and deposit in described data transmitter register, and when receiving the next transmission frame synchronizing signal provided by described FPGA, the data to be sent be temporary in described data transmitter register being sent to described FPGA simultaneously;
McBSP described in each is also for when often receiving a received frame synchronizing signal of described FPGA, the part receiving the specific data length simultaneously inputted by described FPGA receives data, this part is received deposit data in described data receive register, and then this part reception data depositing in described data receive register are sent to described DSP.
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| CN108242958A (en) * | 2016-12-27 | 2018-07-03 | 中国船舶重工集团公司七五○试验场 | A kind of FPGA Underwater acoustic signal processings method and device |
| CN108242958B (en) * | 2016-12-27 | 2021-05-18 | 中国船舶重工集团公司七五○试验场 | FPGA underwater acoustic signal processing method and device |
| CN110572343A (en) * | 2019-07-25 | 2019-12-13 | 西安电子科技大学 | Receiving and transmitting control method for multi-path diversity signals |
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