CN110571358B - Semiconductor device and method for manufacturing the same - Google Patents
Semiconductor device and method for manufacturing the same Download PDFInfo
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Abstract
The invention provides a method for manufacturing a semiconductor device, which comprises the steps of firstly forming a step alleviation layer exposing the top of a first electrode on the whole surface of the device after the first electrode is formed, and then forming an inter-electrode dielectric layer and a second electrode on the surfaces of the first electrode and the step alleviation layer, wherein the step alleviation layer can reduce the step height of the top of the first electrode relative to the upper surface of an interlayer dielectric layer, and provides a relatively flat process surface for covering the inter-electrode dielectric layer, so that the formed inter-electrode dielectric layer and the second electrode can be prevented from cracking, product defects are avoided, and the product yield is improved. Furthermore, the step relaxation layer is an organic compound with anti-sticking performance, so that the stripping of the top of the first electrode and the bottom of the opening of the bonding pad can be facilitated, the surface of the first electrode and the surface of the opening of the bonding pad can not be damaged, and the product performance is ensured. The invention also provides a semiconductor device formed by the manufacturing method of the semiconductor device.
Description
Technical Field
The present invention relates to the field of integrated circuit manufacturing technologies, and in particular, to a semiconductor device and a method for manufacturing the same.
Background
In the fabrication of some semiconductor devices, it is necessary to fabricate an integrated circuit on a wafer substrate, the integrated circuit including electronic components such as a driving transistor and/or a switching transistor and a multi-layer metal interconnection structure electrically connecting the electronic components with functional components on an upper layer through a multi-layer metal interconnection process, and a TOP-most interconnection metal (TOP metal (TM)) in the multi-layer metal interconnection structure of some semiconductor devices needs to be patterned (i.e., pattern-etched) to serve as one electrode of the functional components on the upper layer, and then fabricate the functional components on the upper layer on the integrated circuit chip. However, when the functional elements of the upper layer are directly fabricated on the integrated circuit, product defects easily occur, which affects the yield of the product.
Disclosure of Invention
The present invention provides a semiconductor device and a method for manufacturing the same, which can reduce the relative step height of a first electrode, avoid the material above the first electrode from cracking, and provide the product yield.
In order to achieve the above object, the present invention provides a method of manufacturing a semiconductor device, comprising the steps of:
providing a substrate with an interlayer dielectric layer, wherein a first electrode is formed on the surface of the interlayer dielectric layer, and a pad opening is formed in the interlayer dielectric layer on one side of the first electrode;
Exposing a step alleviation layer at the top of the first electrode on the surfaces of the interlayer dielectric layer and the pad opening, wherein the step alleviation layer is used for reducing the height of the top of the first electrode relative to the upper surface of the interlayer dielectric layer;
and sequentially forming an inter-electrode dielectric layer and a second electrode corresponding to the first electrode on the top of the first electrode and the surface of the step relaxation layer.
Optionally, the step of providing the substrate comprises:
providing a substrate, and forming at least one transistor on the substrate by adopting a CMOS (complementary metal oxide semiconductor) process;
forming a multilayer metal interconnection structure electrically connected with the transistor on the surface of the substrate and the surface of the transistor by adopting a multilayer metal interconnection process, wherein the multilayer metal interconnection structure comprises a topmost interconnection metal layer, a next topmost interconnection metal layer positioned below the topmost interconnection metal layer, an interlayer dielectric layer positioned between the topmost interconnection metal layer and the next topmost interconnection metal layer, and a top conductive plug structure positioned in the interlayer dielectric layer and electrically connected with the topmost interconnection metal layer and the next topmost interconnection metal layer;
patterning the topmost interconnection metal layer to form a first electrode and expose the surface of an area, used for forming the pad opening, of the interlayer dielectric layer;
And etching the exposed interlayer dielectric layer to form the surface of the area of the bonding pad opening so as to form the bonding pad opening, wherein the bonding pad opening exposes the top of the secondary top layer interconnection metal layer.
Optionally, the inter-electrode dielectric layer includes an organic light emitting layer, and the step alleviating layer is made of an organic compound.
Optionally, the material of the step alleviating layer includes at least one of polytetrafluoroethylene, parylene, perfluorodecanoic acid, perfluorooctyltrichlorosilane, perfluoroquinyltrichlorosilane, octadecyltrichlorosilane, dichlorodimethylsilane, chlorosilane, chlorofluorosilane, methoxysilane, trichlorosilane, silicone, polystyrene, polyurethane, and polysilazane.
Optionally, the material of the anode includes one of indium tin oxide and indium zinc oxide.
Optionally, the step alleviating layer is formed by a process including:
covering a step relaxation layer material on the surfaces of the interlayer dielectric layer, the first electrode and the pad opening;
removing the step relaxation layer material on top of the first electrode to form the step relaxation layer.
Optionally, the step of sequentially forming an inter-electrode dielectric layer and a second electrode on the surfaces of the first electrode and the step relaxing layer includes:
Covering an inter-electrode dielectric layer on the surfaces of the first electrode and the step alleviation layer;
patterning the inter-electrode dielectric layer to expose the pad opening;
covering the inter-electrode dielectric layer and the surface of the pad opening with a second electrode layer;
and patterning the second electrode layer to form a second electrode exposing the pad opening.
Optionally, after patterning the inter-electrode dielectric layer, surface cleaning is performed to remove the step buffer layer material remaining in the pad opening.
Optionally, before the surfaces of the first electrode, the interlayer dielectric layer, and the pad opening are covered with the step relaxing layer material, an aluminum pad is formed in the pad opening; alternatively, after the second electrode is formed, an aluminum pad is formed in the pad opening.
The present invention also provides a semiconductor device formed by the above-described method of manufacturing a semiconductor device, the semiconductor device including:
the substrate is provided with an interlayer dielectric layer, a first electrode is formed on the surface of the interlayer dielectric layer, and a pad opening is formed in the interlayer dielectric layer on one side of the first electrode;
the step alleviation layer covers the interlayer dielectric layer and exposes the top of the first electrode, and is used for reducing the height of the top of the first electrode relative to the upper surface of the interlayer dielectric layer;
An inter-electrode dielectric layer covering the first electrode and the step relaxing layer;
and the second electrode is formed on the surface of the inter-electrode dielectric layer and corresponds to the first electrode.
Optionally, at least one transistor and a multilayer metal interconnection structure located above the transistor and electrically connected to the transistor are formed in the substrate; the multilayer metal interconnection structure comprises a topmost interconnection metal layer, a next topmost interconnection metal layer, an interlayer dielectric layer and a top conductive plug structure, wherein the topmost interconnection metal layer is used as the first electrode in whole or in part, the next topmost interconnection metal layer is positioned below the topmost interconnection metal layer, the interlayer dielectric layer is positioned between the topmost interconnection metal layer and the next topmost interconnection metal layer, and the top conductive plug structure is positioned on the interlayer dielectric layer and electrically connected with the topmost interconnection metal layer and the next topmost interconnection metal layer; the bottom of the pad opening exposes the top of the next-to-top interconnect metal layer.
Optionally, the semiconductor device is an organic light emitting device, the inter-electrode dielectric layer includes an organic light emitting layer, and the step relaxing layer is made of an organic compound.
Optionally, the material of the step alleviating layer includes at least one of polytetrafluoroethylene, parylene, perfluorodecanoic acid, perfluorooctyltrichlorosilane, perfluoroquinoneditrichlorosilane, octadecyltrichlorosilane, dichlorodimethylsilane, chlorosilane, chlorofluorosilane, methoxysilane, trichlorosilane, silicone, polystyrene, polyurethane, and polysilazane.
Optionally, the semiconductor device is an organic light emitting display device, and the anode includes one of indium tin oxide and indium zinc oxide.
Optionally, an aluminum pad is formed in the pad opening.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
1. the manufacturing method of the semiconductor device comprises the steps of firstly forming a step alleviation layer exposing the top of the first electrode on the whole surface of the device after the first electrode is formed, and then forming an inter-electrode dielectric layer and a second electrode on the surfaces of the first electrode and the step alleviation layer, wherein the step alleviation layer can reduce the step height of the top of the first electrode relative to the upper surface of the inter-electrode dielectric layer, and provides a relatively flat process surface for covering the inter-electrode dielectric layer, so that the formed inter-electrode dielectric layer and the second electrode can be prevented from being broken, product defects are avoided, and the product yield is improved. Furthermore, the step relaxation layer is an organic compound, so that the stripping on the top of the first electrode and the bottom of the pad opening can be facilitated, the surfaces of the first electrode and the pad opening cannot be damaged, and the product performance is ensured.
2. The semiconductor device is formed by the manufacturing method of the semiconductor device, the height of the step of the top of the first electrode relative to the upper surface of the interlayer dielectric layer is reduced through the step alleviation layer, the breakage of the inter-electrode dielectric layer and the second electrode on the surface of the first electrode is avoided, and the product performance is improved.
Drawings
FIG. 1A is a flow chart of a method of fabricating an OLED display;
FIG. 1B is a schematic cross-sectional view of the device structure in the method of manufacturing shown in FIG. 1A;
FIG. 2 is a flow chart of a method of fabricating a semiconductor device in accordance with an embodiment of the present invention;
fig. 3A to 3F are schematic cross-sectional views of the device structure in the manufacturing method shown in fig. 2.
Detailed Description
As described in the background, TOP-most interconnect metal (TOP metal) in a multi-level metal interconnect structure of some semiconductor devices needs to be patterned (i.e., pattern etched) to serve as one electrode of an overlying functional element, which is prone to product defects when fabricated directly on the integrated circuit, affecting product yield. The problems of the prior art will be described in detail below by taking an Organic Light Emitting Display (OLED) as an example. The OLED display is a thin film light emitting device driven by a direct current voltage, which is made of an organic semiconductor material, is a self-light emitting display device unlike a conventional Liquid Crystal Display (LCD), does not require a backlight, can be made lighter and thinner, has advantages in power consumption, and is excellent in color realization, response speed, viewing angle, and contrast, and can be used for various electronic products such as a mobile phone, a PDA, a camcorder, and the like. Each organic light emitting diode in an OLED display includes an anode, a cathode, and an organic compound layer between the anode and the cathode, and each organic light emitting diode typically has a patterned topmost layer of interconnect metal as its cathode. Referring to fig. 1A and 1B, the current manufacturing process of the OLED display includes the following steps:
S10, forming a top layer conductive plug (top via): firstly, sequentially manufacturing an integrated circuit chip layer 101 and a secondary top layer interconnection metal 102 electrically connected with the integrated circuit chip layer 101 on a wafer substrate 100, wherein the integrated circuit chip layer 101 comprises an electronic element including a driving transistor (MOS) and/or a switching transistor, and a lower metal interconnection structure positioned between the electronic element and the secondary top layer interconnection metal 102, and the lower metal interconnection structure electrically connects the secondary top layer interconnection metal 102 with the electronic element; then, forming an interlayer dielectric layer 103 on the surface of the next-to-top interconnection metal 102, and etching the interlayer dielectric layer 103 (i.e. top via etch) to form a via (via) penetrating through the interlayer dielectric layer 103 to the surface of the next-to-top interconnection metal 102; then, tungsten (W) is deposited on the surfaces of the interlayer dielectric layer 103 and the through hole until the through hole is filled with the deposited tungsten, and then the deposited tungsten is subjected to chemical mechanical polishing until the surface of the interlayer dielectric layer 103 is exposed, thereby forming a top conductive plug 104.
S11, forming a cathode (cathode): firstly, depositing a topmost interconnection metal layer (cathode Dep) on the surfaces of the interlayer dielectric layer 103 and the top layer conductive plug 104 by sputtering and other processes; then, a photoresist Pattern with a cathode Pattern is formed on the topmost interconnection metal layer, and the topmost interconnection metal layer (cathode Dry etch) is etched by using the photoresist with the cathode Pattern as a mask through a Dry etching process, and a small amount of over-etching is performed to Pattern the topmost interconnection metal layer to be used as a cathode 105 of the organic light emitting diode.
S12, forming a PAD opening (PAD formation): the interlayer dielectric layer 103 exposed at one side of the cathode is etched to form a pad opening in the interlayer dielectric layer 103, wherein the region where the cathode 105 is located may be referred to as a pixel region or a display region, and the region where the pad opening is located may be referred to as a non-display region or a pad region, and then an aluminum pad 106 may be formed in the pad opening.
S13, forming an organic light emitting diode structure (OLED formats): that is, an organic compound layer and an anode layer (not shown) are sequentially formed on the surfaces of the cathode 105 (i.e., the patterned topmost interconnect metal layer) and the interlayer dielectric layer 103, and both the organic compound layer and the anode layer expose the region where the pad 106 is located (i.e., the non-display region).
In order to reasonably utilize resources and improve production efficiency, steps S10 to S12 in the above-mentioned OLED display manufacturing process are usually performed by the OLED design manufacturer by wafer foundry (wafer foundry), and when the topmost interconnection metal layer is over-etched to form the cathode 105 in step S11, the interlayer dielectric layer 103 under the cathode 105 is etched to a certain degree to generate a step high, so that the cathode 105 becomes relatively high (as the height H marked in fig. 1B), the aspect ratio of the process window for subsequently manufacturing the organic diode becomes larger, the process Margin (process Margin) becomes smaller, and when the OLED design manufacturer directly covers the organic compound layer on the surface of the interlayer dielectric layer 103 and the cathode 105, the relatively high cathode 105 may cause the organic compound layer to break, thereby causing product defects and reducing yield.
Therefore, the invention provides a semiconductor device and a manufacturing method thereof, which can reduce the relative step height of the patterned topmost interconnection metal, avoid the material above the patterned topmost interconnection metal from being broken due to overhigh step and provide the product yield.
The present invention will be described in more detail with reference to the accompanying drawings, but the present invention can be implemented in various forms and should not be limited to the embodiments described below.
Referring to fig. 2, the present invention provides a method for manufacturing a semiconductor device, comprising the steps of:
s21, providing a substrate with an interlayer dielectric layer, forming a first electrode on the surface of the interlayer dielectric layer, and forming a pad opening in the interlayer dielectric layer at one side of the first electrode;
s22, exposing the step alleviating layer at the top of the first electrode on the surfaces of the interlayer dielectric layer and the pad opening, wherein the step alleviating layer is used for reducing the height of the top of the first electrode relative to the upper surface of the interlayer dielectric layer;
and S23, sequentially forming an inter-electrode dielectric layer and a second electrode corresponding to the first electrode on the top of the first electrode and the surface of the step reducing layer.
Referring to fig. 3A, in step S21, a TOP-most interconnect metal (TOP metal) in the multi-layered metal interconnect structure may be directly used as the first electrode 318 on the surface of the interlayer dielectric layer 316, and thus the step of providing the substrate may specifically include the following steps:
first, a substrate 300 is provided, wherein the substrate 300 may be any semiconductor wafer material known to those skilled in the art, such as silicon, germanium, silicon carbon, gallium arsenide, etc., bulk silicon, bulk germanium, etc., and semiconductor-on-insulator material such as silicon-on-insulator, germanium-on-insulator, silicon germanium-on-insulator, etc. At least one transistor, such as the NMOS transistor 303A and the PMOS transistor 303b in fig. 3A, may be formed on the substrate 300 using a CMOS process, wherein the CMOS process includes: the field oxide isolation structure 301 for isolating adjacent transistors is formed through device isolation processes such as a shallow trench isolation process, a P-well 302a is formed through well injection of P-type ions, an N-well 302b is formed through well injection of N-type ions, stacked gate oxides and polysilicon gates are formed through a polysilicon gate process, side walls are formed on the side walls of the stacked gate oxides and polysilicon gates through a side wall process, and source and drain electrodes are formed through a source and drain electrode forming process.
Then, a metal silicide for reducing contact resistance is formed on the tops of the source and drain electrodes of each transistor and the polysilicon gate electrode through a metal silicide process, wherein the metal in the metal silicide can be titanium, cobalt, nickel, tungsten and the like, and an etching stop layer 304 is deposited on the surface of the substrate 300 including the transistors, the metal silicide and the field oxide isolation structure to protect the transistors from being damaged in the subsequent process, so that the device wafer 30 including at least one transistor is manufactured.
Then, a multilayer metal interconnection process may be adopted to form a multilayer metal interconnection structure 31 electrically connected to each transistor on the surface of the device wafer 30, specifically, a bottom interlayer dielectric layer 310 is deposited on the surface of the device wafer 30, the interlayer dielectric layer 310 is etched and etched to form a contact hole (contact) exposing at least one of a source metal silicide, a drain metal silicide and a gate metal silicide of the corresponding transistor, and a conductive material such as tungsten or copper is filled in the contact hole through a contact hole filling process and a Chemical Mechanical Polishing (CMP) process to form a bottom conductive contact hole structure 311; next, each layer of metal interconnection structure including a conductive plug structure and an interconnection metal layer may be sequentially formed on the surfaces of the bottom interlayer dielectric layer 310 and the bottom conductive contact hole structure 311 through a copper interconnection process, for example, the multilayer metal interconnection structure in this embodiment includes four interconnection metal layers, and the specific structure includes a first interconnection metal layer M1 (which is a copper material), an inter-metal interlayer dielectric layer 312 (which may be a low K dielectric having a dielectric constant K less than 4), a conductive plug structure 313 (which is a copper material), a second interconnection metal layer M2 (which is a copper material), an inter-metal interlayer dielectric layer 314 (which may be a low K dielectric having a dielectric constant K less than 4), a conductive plug structure 315 (which is a copper material), a next top interconnection metal layer M3 (which is a copper material), an interlayer dielectric layer 316, a top conductive plug structure 317, and a top interconnection metal layer TM (which may be a copper, and a copper, a metal, a copper, a metal, and a metal, a, Titanium, etc.); wherein the first layer of interconnect metal layer M1 is located on the surfaces of the bottom interlayer dielectric layer 310 and the bottom conductive contact hole structure 311, and the bottom is in electrical contact with the bottom conductive contact hole structure 311; the intermetallic interlayer dielectric layer 312 covers the surfaces of the first interconnection metal layer M1, the bottom interlayer dielectric layer 310 and the bottom conductive contact hole structure 311; conductive plug structure 313 is located in inter-metal interlayer dielectric layer 312, and electrically contacts first level interconnect metal layer M1 at the bottom and electrically contacts second level interconnect metal layer M2 at the top; a second interconnect metal layer M2 is located on the surface of the intermetal interlayer dielectric layer 312 and the conductive plug structure 313; the inter-metal interlayer dielectric layer 314 covers the second interconnect metal layer M2, the conductive plug structure 313 and the surface of the inter-metal interlayer dielectric layer 312; the conductive plug structure 315 is located in the inter-metal interlayer dielectric layer 314, and the bottom electrically contacts the second-level interconnect metal layer M2 and the top electrically contacts the bottom of the next-to-top-level interconnect metal layer M3; a second-top interconnection metal layer M3 is positioned on the surface of the inter-metal interlayer dielectric layer 314 and the conductive plug structure 315; the interlayer dielectric layer 316 covers the surfaces of the next-to-top interconnection metal layer M3, the conductive plug structure 315, and the inter-metal interlayer dielectric layer 314, and the material of the interlayer dielectric layer 316 may be different from the materials of the inter-metal interlayer dielectric layers 312 and 314, and is a material commonly used as a passivation layer, such as silicon oxide, silicon nitride, or silicon oxynitride; top conductive plug structure 317 is located in interlayer dielectric layer 316 and has a bottom electrically contacting next-to-top interconnect metal layer M3 and a top electrically contacting the bottom of topmost interconnect metal layer TM; the topmost interconnect metal layer 318 may now completely cover the entire device surface, completely unpatterned.
Then, the topmost interconnection metal layer TM may be subjected to corresponding photolithography and etching, that is, the topmost interconnection metal layer TM is patterned, so that all or part of the remaining topmost interconnection metal layer TM (that is, the patterned topmost interconnection metal layer TM) serves as the first electrode 318, and the remaining topmost interconnection metal layer TM also exposes the surface of the region where the interlayer dielectric layer 316 is used to form the pad, where a certain over-etching may be performed during etching the topmost interconnection metal layer TM, so as to immediately remove the interlayer dielectric layer 316 with a certain thickness by etching, so as to ensure that the topmost interconnection metal layer TM is etched in place, and prevent the problem that the device fails due to adhesion of two adjacent first electrodes 318.
Thereafter, the surface of the region where interlayer dielectric layer 316 is exposed for forming a pad opening may be subjected to photolithography and etching to form a pad opening 319, the bottom of pad opening 319 exposing the top of next-to-top interconnect metal layer M3. After forming the pad opening 319 and before covering the subsequent step buffer layer material 32, an aluminum pad may be formed in the pad opening 319 through an aluminum pad process, or after forming the second electrode, an aluminum pad may be formed in the pad opening 319 through an aluminum pad process, as shown by 35 in fig. 3F, where an area where the pad opening 319 is located may be a peripheral area (for example, a non-display area of a display), and an area where the first electrode 318 is located may be a device area (for example, a display area or a pixel area of the display).
Referring to fig. 3B, in step S22, a step buffer layer material 32 with a certain thickness is first formed on the entire device surface including the first electrode 318 by plasma enhanced chemical vapor deposition, low pressure chemical vapor deposition, hot filament chemical vapor deposition or vacuum coating. The step-relaxation layer 32 is preferably an organic compound with anti-adhesion property, which has strong adhesion with the interlayer dielectric layer 316 and the second electrode 318 and the second top-level interconnection metal M3 at the bottom of the pad opening 319Has relatively weak adhesion, facilitates subsequent stripping on the bottom surface of the pad opening 319 (i.e., the surface of the next-to-top interconnect metal M3) and the top surface of the first electrode 318, and does not damage the bottom surface of the pad opening 319 and the top surface of the first electrode 318 during the stripping process; on the other hand, the remaining step-relaxing layer material 32 can reduce the step height of the first electrode 318 relative to the interlayer dielectric layer 316, and at the same time, can improve the adhesion with the subsequent inter-electrode dielectric layer (especially when the inter-electrode dielectric layer is an organic light-emitting layer), thereby improving the coverage of the inter-electrode dielectric layer. Wherein the organic compound having anti-sticking property includes at least one of polytetrafluoroethylene, parylene, perfluorodecacarboxylic acid, perfluorooctyltrichlorosilane, perfluoroquinoneshlorosilane, octadecyltrichlorosilane, dichlorodimethylsilane, chlorosilane, chlorofluorosilane, methoxysilane, trichlorosilane, silicone, polystyrene, polyurethane and polysilazane, for example. In one embodiment of the present invention, the surface of the device is coated with perfluorooctyl trichlorosilane (CF) by vacuum coating 3(CF2)5(CH2)2SiCl3) The organic compound having the anti-sticking property is then baked at 100 c for a certain time to form a dense organic molecular layer as the step buffer layer material 32. Then, any suitable etchant such as an organic solvent may be used to perform wet etching on the step alleviating layer material 32, or suitable process gas may be used to perform dry etching on the step alleviating layer material 32, or a chemical mechanical planarization process may be used to perform top polishing on the step alleviating layer material 32 to remove the step alleviating layer material on the top surface of the first electrode 318, so as to form the step alleviating layer 32a, and the specific process parameters are set as long as the step alleviating layer material on the top surface of the first electrode 318 can be completely removed, and continuously extending step alleviating layer material remains on the sidewall of the first electrode 318 and on the surface of the interlayer dielectric layer 316 outside the sidewall thereof, as shown in fig. 3C and 3D, step alleviating layer material remains on the sidewall and the bottom of the trench between two adjacent first electrodes 318, and to the left of the left first electrode 318There is also a step-mitigating layer material remaining on the sidewalls. At this time, the relative step height between the top of the first electrode 318 and the step alleviation layer 32a is smaller than the relative step height between the top of the first electrode 318 and the upper surface of the interlayer dielectric layer 316, i.e., the height difference between the top surface of the first electrode 318 and the top surface of the horizontal portion of the step alleviation layer 32a laid flat on the interlayer dielectric layer 316 is smaller than the height difference between the top surface of the first electrode 318 and the top surface of the interlayer dielectric layer 316, thereby providing a relatively flat process surface for the subsequent inter-electrode dielectric layer coverage. In addition, since the deposited step buffer layer material 32 is easy to be stripped with respect to metal and not easy to be removed with respect to the interlayer dielectric layer, the step buffer layer material on the bottom of the pad opening 319 can be removed simultaneously in the step buffer layer material removal process on the top of the first electrode 318, and a certain amount of step buffer layer material remains on the surface of the interlayer dielectric layer 316 between the first electrode 318 and the pad opening 319, on the sidewall of the pad opening 319, and in the trench between two adjacent first electrodes. Specifically, as shown in fig. 3C, in an embodiment in which the step alleviating layer material 32 is etched to a relatively small extent, a step alleviating layer 32a remains between adjacent first electrodes 318, and a continuously extending step alleviating layer 32b remains on the sidewalls of the pad openings 319 and the surface of the interlayer dielectric layer 316 between the first electrodes 318 and the pad openings 319, wherein the step alleviating layer 32b may be removed together when the inter-electrode dielectric layer in the pad openings 319 is subsequently removed, or may be further removed by etching before the inter-electrode dielectric layer is deposited, or may be removed during the formation of the aluminum pad in the pad openings 319, as shown in fig. 3F, and the portion of the step alleviating layer 32a tiled on the surface of the interlayer dielectric layer 316 may complement the over-etched height of the interlayer dielectric layer 316 during the formation of the first electrodes 318, so as to reduce the relative step height of the first electrodes 318, meanwhile, the aspect ratio of the trench between adjacent first electrodes 318 can be reduced, which is beneficial to providing a relatively flat process surface for the subsequent formation of the inter-electrode dielectric layer and the second electrode, and no adverse effect is brought. In an embodiment where the step-mitigating layer is etched to a relatively strong degree, as shown in FIG. 3D, the top of the first electrode 318 and the pad are opened The step alleviating layer on the sidewall and bottom surface of the opening 319 are completely removed, and a step alleviating layer 32a remains between the adjacent first electrodes 318, and a step alleviating layer 32c remains on the portion of the surface of the interlayer dielectric layer 316 between the first electrodes 318 and the pad opening 319, which is next to the sidewall of the first electrode 318, and the step alleviating layer 32c may only cover the sidewall of the first electrode 318, or may extend along the top of the sidewall of the first electrode 318 to the surface of the interlayer dielectric layer 316, and is laid out at the interlayer dielectric layer 316 for a certain length.
Referring to fig. 3E, in step S23, the inter-electrode dielectric layer may be directly covered on the entire device surface including the remaining step mitigation layer 32a, and then patterned by photolithography and etching processes to form a patterned inter-electrode dielectric layer 33 between the subsequent second electrode and the first electrode 318, where the patterned inter-electrode dielectric layer 33 exposes the pad opening 319 and covers all the first electrodes 318 and the surface of the step mitigation layer 32a between two adjacent first electrodes 318; then, cleaning the surface of the device to remove the remaining step-relaxing layer in the pad opening 319 and the remaining step-relaxing layer at the boundary between the first electrode 318 and the pad opening 319, which is not covered by the patterned inter-electrode dielectric layer 33, so as to expose the top surface of the inter-layer dielectric layer 316 at the boundary between the first electrode 318 and the pad opening 319; then, covering a second electrode layer on the surfaces of the patterned inter-electrode dielectric layer, the exposed inter-layer dielectric layer 316 and the pad opening; thereafter, the second electrode layer is patterned to form the second electrode 34 completely covering the patterned inter-electrode dielectric layer 33 and completely exposing the pad opening 319. In other embodiments of the present invention, the inter-electrode dielectric layer and the second electrode layer may be directly and sequentially covered on the entire device surface including the remaining step alleviating layer, and then the second electrode layer and the inter-electrode dielectric layer are sequentially patterned through photolithography and etching, so as to form the second electrode 34 and the patterned inter-electrode dielectric layer 33 located between the second electrode 34 and the first electrode 318, at this time, the pad opening 319 has no inter-electrode dielectric layer and second electrode layer in the region, the patterned inter-electrode dielectric layer 33 covers the tops of all the first electrodes 318, the surfaces of the remaining step alleviating layers between two adjacent first electrodes 318, and the surfaces of the remaining step alleviating layers in the boundary region between the first electrode 318 and the pad opening 319, and then surface cleaning is performed to remove the exposed pad opening 319 and the remaining step alleviating layer on the surface of the inter-layer dielectric layer 316, for use in lead and/or aluminum pad 35 fabrication. In other embodiments of the present invention, a mask layer may be formed on a surface of a device including a remaining step alleviating layer, where the mask layer covers the pad opening (i.e., a region where the pad opening is located) and has an opening that exposes the first electrode 318, the remaining step alleviating layer between two adjacent first electrodes 318, and a surface of the remaining step alleviating layer at a boundary region between the first electrode 318 and the pad opening 319 (i.e., a region where the first electrode 318 is located), then the inter-electrode dielectric layer 33 and the second electrode layer are sequentially formed on the mask layer and the surface of the opening through a vapor deposition process or an inkjet process, then the excess inter-electrode dielectric layer 33 and the second electrode layer are removed through a chemical mechanical polishing process, the second electrode 34 and the patterned inter-electrode dielectric layer 33 located between the second electrode 34 and the first electrode 318 are formed, the patterned inter-electrode dielectric layer 33 covers the tops of all the first electrodes 318, the remaining step-relaxing layer between two adjacent first electrodes 318, and the surface of the remaining step-relaxing layer in the boundary area between the first electrode 318 and the pad opening 319, and then the mask layer is removed by wet etching or the like to expose the pad opening 319. Wherein, when the manufactured semiconductor device is an organic light emitting display device, the inter-electrode dielectric layer 33 is an organic light emitting layer, the first electrode is a cathode, the second electrode 34 is an anode, and the material thereof may include a transparent electrode material such as indium tin oxide and/or indium zinc oxide, and the second electrode 34 is formed on an upper layer of the organic light emitting diode, so that light emitted from the organic light emitting layer is emitted upward, and the organic light emitting display device is a top emission type OELD device having an improved aperture ratio.
Wherein the material of the organic light-emitting layer may be formed of a high molecular compound or a low molecular compound,and when formed of a low molecular compound, it may be formed using a vapor deposition process, and when formed of a high molecular compound, it may be formed using an inkjet (inkjet) process. In addition, the organic light emitting layer may have a multi-layered stacked structure, for example, a Hole Injection Layer (HIL), a Hole Transport Layer (HTL), an Emitting Material Layer (EML), an Electron Transport Layer (ETL), an Electron Injection Layer (EIL), and a buffer layer in this order from bottom to top, the Hole Transport Layer (HTL) and the Electron Transport Layer (ETL) for improving light emitting efficiency, the Hole Injection Layer (HIL) and the Electron Injection Layer (EIL) for reducing an energy barrier to inject holes and electrons, the buffer layer for preventing the hole injection layer from being damaged during deposition of the second electrode, and the buffer layer may be formed of copper phthalocyanine (CuPC) and vanadium pentoxide (V)2O5) And one of them is formed. In addition, the Hole Injection Layer (HIL) is composed of CuPC and V2O5In one of the formation, the organic light emitting layer may omit the buffer layer.
In the method for manufacturing a semiconductor device according to the present invention, step S21 may be performed by a foundry for semiconductor device design and manufacturer, and steps S22 to S24 may be performed by the foundry for semiconductor device design and manufacturer, so that social resources are reasonably utilized, the product cycle is shortened, and the efficiency is improved.
In view of the above, the method for manufacturing a semiconductor device according to the present invention includes forming a step alleviation layer exposing the top of the first electrode on the entire device surface after the first electrode is formed, and forming an inter-electrode dielectric layer and a second electrode on the surfaces of the first electrode and the step alleviation layer, where the step alleviation layer can reduce the step height of the top of the first electrode relative to the upper surface of the inter-electrode dielectric layer, and provide a relatively flat process surface for covering the inter-electrode dielectric layer, thereby preventing the formed inter-electrode dielectric layer and the second electrode from cracking, avoiding product defects, and improving product yield. Furthermore, the step relaxation layer is an organic compound, so that the stripping on the top of the first electrode and the bottom of the pad opening can be facilitated, the surfaces of the first electrode and the pad opening cannot be damaged, and the product performance is ensured.
Referring to fig. 3E, the present invention further provides a semiconductor device formed by the above method for manufacturing a semiconductor device, the semiconductor device including:
a substrate having an interlayer dielectric layer 316, a first electrode 318 is formed on a surface of the interlayer dielectric layer 316, a pad opening 319 is formed in the interlayer dielectric layer 316 at one side of the first electrode 318, and an aluminum pad 35 may be formed in the pad opening 319;
A step alleviation layer 32a covering the interlayer dielectric layer 316 and exposing the top of the first electrode 318, for reducing the height of the top of the first electrode 318 relative to the upper surface of the interlayer dielectric layer; the step alleviating layer 32a in this embodiment extends from the top of the sidewall of the first electrode 318 to the surface of the interlayer dielectric layer 316, and is laid on the interlayer dielectric layer 316 for a certain length, the step alleviating layer 32a also exposes a portion of the bottom surface of the pad opening 319, when there are a plurality of first electrodes 318 (for example, a plurality of organic light emitting diodes are manufactured), the step alleviating layer 32a completely covers the surface of the trench between two adjacent first electrodes 318; in addition, the step-relaxing layer 32c may be provided on the other side wall of the first electrode 318, or may not be provided; when there is a step relaxing layer 32c, the step relaxing layer 32c may extend from the top of the sidewall of the first electrode 318 to the surface of the interlayer dielectric layer 316, and may be tiled on the interlayer dielectric layer 316 for a certain length;
an interelectrode dielectric layer 33 covering the surfaces of the first electrode 318 and the step relaxing layer 32 a;
and a second electrode 34 formed on the surface of the inter-electrode dielectric layer 33 and corresponding to the first electrode 318, wherein the meaning of "corresponding" may be completely aligned, or the first electrode 318 may be wrapped inside as shown in fig. 3E.
In this embodiment, at least one transistor (as shown by dotted circles 303a and 303b in fig. 3E) and a multilayer metal interconnection structure 31 located above and electrically connected to the transistor are formed in the substrate; the multilayer metal interconnection structure comprises a topmost interconnection metal layer TM which is used as the first electrode 318 in whole or in part, a next-to-topmost interconnection metal layer M3 which is positioned below the topmost interconnection metal layer TM, the interlayer dielectric layer 316 which is positioned between the topmost interconnection metal layer TM and the next-to-topmost interconnection metal layer M3, and a top conductive plug structure 317 which is positioned on the interlayer dielectric layer 316 and electrically connects the topmost interconnection metal layer TM and the next-to-topmost interconnection metal layer M3; the bottom of the pad opening 319 exposes the top of the next-to-top interconnect metal layer M3.
In this case, the inter-electrode dielectric layer 33 may include an organic light emitting layer, and the material of the step reducing layer 32a may be an organic compound having anti-sticking properties, for example, at least one of polytetrafluoroethylene, parylene, perfluorodecanoic acid, perfluorooctyltrichlorosilane, perfluoroquinoneditrichlorosilane, octadecyltrichlorosilane, dichlorodimethylsilane, chlorosilane, chlorofluorosilane, methoxysilane, trichlorosilane, silicone, polystyrene, polyurethane, and polysilazane. When the semiconductor device is an organic light emitting display device, the material of the second electrode 34 may be a transparent electrode material including indium tin oxide and/or indium zinc oxide.
In this way, the semiconductor device of the present invention is formed by the method of the present invention, the step relaxation layer reduces the relative step height of the first electrode, prevents the inter-electrode dielectric layer and the second electrode on the surface of the first electrode from cracking, and improves the product performance.
It will be apparent to those skilled in the art that various changes and modifications may be made in the invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (12)
1. A method of manufacturing a semiconductor device, comprising the steps of:
providing a substrate with an interlayer dielectric layer, wherein the substrate is provided with a display area and a non-display area positioned at the periphery of the display area, a first electrode is formed on the surface of the interlayer dielectric layer of the display area, a pad opening is formed in the interlayer dielectric layer of the non-display area, and the bottom of the pad opening is exposed out of the top of a corresponding metal layer in the substrate;
covering a step relaxation layer material on the surfaces of the interlayer dielectric layer, the first electrode and the pad opening;
Removing the step relaxing layer material on the top of the first electrode and in the pad opening to form a step relaxing layer exposing the top of the first electrode, wherein the step relaxing layer covers the side wall of the first electrode and the bottom surface of the groove between the adjacent first electrodes, and the height difference between the top surface of the first electrode and the top surface of the horizontal part of the step relaxing layer tiled on the interlayer dielectric layer is smaller than the height difference between the top surface of the first electrode and the top surface of the interlayer dielectric layer;
forming an inter-electrode dielectric layer and a second electrode corresponding to the first electrode in sequence on the top of the first electrode and the surface of the step relaxing layer, wherein the inter-electrode dielectric layer comprises an organic light-emitting layer, the inter-electrode dielectric layer exposes out of the pad opening and covers the first electrode of the display area, the step relaxing layer and the surface of the inter-electrode dielectric layer, and the second electrode is positioned in the display area; the step relaxation layer is an organic compound with anti-sticking performance, has strong adhesion with the interlayer dielectric layer and the inter-electrode dielectric layer, and has relatively weak adhesion with the metal layer exposed at the bottom of the pad opening.
2. The method for manufacturing a semiconductor device according to claim 1, wherein the step of providing the substrate comprises:
providing a substrate, and forming at least one transistor on the substrate by adopting a CMOS (complementary metal oxide semiconductor) process;
forming a multilayer metal interconnection structure electrically connected with the transistor on the surfaces of the substrate and the transistor element by adopting a multilayer metal interconnection process, wherein the multilayer metal interconnection structure comprises a topmost interconnection metal layer, a next topmost interconnection metal layer positioned below the topmost interconnection metal layer, an interlayer dielectric layer positioned between the topmost interconnection metal layer and the next topmost interconnection metal layer, and a top conductive plug structure positioned in the interlayer dielectric layer and electrically connected with the topmost interconnection metal layer and the next topmost interconnection metal layer;
patterning the topmost interconnection metal layer to form the first electrode and expose the surface of the region of the interlayer dielectric layer for forming the pad opening;
and etching the exposed interlayer dielectric layer to form the area surface of the bonding pad opening so as to form the bonding pad opening, wherein the bonding pad opening exposes the top of the secondary top layer interconnection metal layer.
3. The method for manufacturing a semiconductor device according to claim 1, wherein a material of the step relaxing layer includes at least one of polytetrafluoroethylene, parylene, perfluorodecacarboxylic acid, perfluorooctyltrichlorosilane, perfluoroquinoyl trichlorosilane, octadecyltrichlorosilane, dichlorodimethylsilane, chlorosilane, chlorofluorosilane, methoxysilane, trichlorosilane, silicone, polystyrene, polyurethane, and polysilazane.
4. The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein the first electrode is a cathode, the second electrode is an anode, and a material of the second electrode includes one of indium tin oxide and indium zinc oxide.
5. The method for manufacturing a semiconductor device according to claim 1, wherein the step of sequentially forming an interelectrode dielectric layer and a second electrode on the surfaces of the first electrode and the step relaxing layer comprises:
covering an inter-electrode dielectric layer on the surfaces of the first electrode and the step alleviation layer;
patterning the inter-electrode dielectric layer to expose the pad opening;
covering a second electrode layer on the surfaces of the inter-electrode dielectric layer and the pad opening;
And patterning the second electrode layer to form a second electrode exposing the pad opening.
6. The method for manufacturing a semiconductor device according to claim 5, wherein after the inter-electrode dielectric layer is patterned, surface cleaning is performed to remove a step relaxation layer material remaining in the pad opening.
7. The method for manufacturing a semiconductor device according to claim 6, wherein an aluminum pad is formed in the pad opening before the step relaxation layer material is coated on the surfaces of the first electrode, the interlayer dielectric layer, and the pad opening; alternatively, after the second electrode is formed, an aluminum pad is formed in the pad opening.
8. A semiconductor device formed by the method for manufacturing a semiconductor device according to any one of claims 1 to 7, comprising:
the substrate is provided with a display area and a non-display area positioned on the periphery of the display area, a first electrode is formed on the surface of the interlayer dielectric layer in the display area, a bonding pad opening is formed in the interlayer dielectric layer in the non-display area, and the bottom of the bonding pad opening is exposed out of the top of a corresponding metal layer in the substrate;
The step alleviating layer covers the side wall of the first electrode and the interlayer dielectric layer at the bottom of the groove between the adjacent first electrodes, the top of the first electrode is exposed, and the height difference between the top surface of the first electrode and the top surface of the horizontal part of the step alleviating layer paved on the interlayer dielectric layer is smaller than the height difference between the top surface of the first electrode and the top surface of the interlayer dielectric layer;
an inter-electrode dielectric layer covering the first electrode and the step relaxation layer;
the second electrode is formed on the surface of the inter-electrode dielectric layer and corresponds to the first electrode;
the inter-electrode dielectric layer exposes the pad opening and covers the surfaces of the first electrode, the step relaxation layer and the interlayer dielectric layer of the display area, and the second electrode is positioned in the display area; the inter-electrode dielectric layer comprises an organic light emitting layer, the step relaxation layer is an organic compound with anti-sticking performance, and has strong adhesion with the inter-layer dielectric layer and the inter-electrode dielectric layer, and has relatively weak adhesion with the metal layer exposed at the bottom of the pad opening.
9. The semiconductor device according to claim 8, wherein at least one transistor and a multilayer metal interconnect structure which is located over and electrically connected to the transistor are formed in the substrate; the multilayer metal interconnection structure comprises a topmost interconnection metal layer, a next topmost interconnection metal layer, an interlayer dielectric layer and a top conductive plug structure, wherein the topmost interconnection metal layer is used as the first electrode in whole or in part, the next topmost interconnection metal layer is positioned below the topmost interconnection metal layer, the interlayer dielectric layer is positioned between the topmost interconnection metal layer and the next topmost interconnection metal layer, and the top conductive plug structure is positioned on the interlayer dielectric layer and electrically connected with the topmost interconnection metal layer and the next topmost interconnection metal layer; the bottom of the pad opening exposes the top of the next-to-top interconnect metal layer.
10. The semiconductor device according to claim 8, wherein a material of the step-relaxing layer comprises at least one of polytetrafluoroethylene, parylene, perfluorodecacarboxylic acid, perfluorooctyltrichlorosilane, perfluoroquinoneditrichlorosilane, octadecyltrichlorosilane, dichlorodimethylsilane, chlorosilane, chlorofluorosilane, methoxysilane, trichlorosilane, silicone, polystyrene, polyurethane, and polysilazane.
11. The semiconductor device according to any one of claims 8 to 10, wherein the semiconductor device is an organic light-emitting display device, the first electrode is a cathode, the second electrode is an anode, and a material of the second electrode includes one of indium tin oxide and indium zinc oxide.
12. The semiconductor device of claim 8, wherein an aluminum pad is formed in the pad opening.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN86103174A (en) * | 1985-05-07 | 1986-11-19 | 株式会社日立制作所 | Semiconductor device and manufacture method thereof |
| CN101431842A (en) * | 2003-03-27 | 2009-05-13 | 精工爱普生株式会社 | Electro-optical device, and electronic apparatus |
| JP2013254610A (en) * | 2012-06-06 | 2013-12-19 | Rohm Co Ltd | Organic el light emitting device and method for manufacturing the same |
| CN105810719A (en) * | 2016-05-27 | 2016-07-27 | 京东方科技集团股份有限公司 | Pixel unit, production method thereof, array substrate and display device |
| CN107394056A (en) * | 2017-07-25 | 2017-11-24 | 南京迈智芯微光电科技有限公司 | A kind of si-based light-emitting device electrode structure and its preparation technology |
-
2018
- 2018-06-05 CN CN201810578058.2A patent/CN110571358B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN86103174A (en) * | 1985-05-07 | 1986-11-19 | 株式会社日立制作所 | Semiconductor device and manufacture method thereof |
| CN101431842A (en) * | 2003-03-27 | 2009-05-13 | 精工爱普生株式会社 | Electro-optical device, and electronic apparatus |
| JP2013254610A (en) * | 2012-06-06 | 2013-12-19 | Rohm Co Ltd | Organic el light emitting device and method for manufacturing the same |
| CN105810719A (en) * | 2016-05-27 | 2016-07-27 | 京东方科技集团股份有限公司 | Pixel unit, production method thereof, array substrate and display device |
| CN107394056A (en) * | 2017-07-25 | 2017-11-24 | 南京迈智芯微光电科技有限公司 | A kind of si-based light-emitting device electrode structure and its preparation technology |
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