CN110570826A - display panel driving method - Google Patents

Abstract

A display panel driving method comprises an array of element pixels, and further comprises a column driving line, wherein for the nth column driving line from the left, if n is an odd number, the column driving line is used for driving the element pixels of the 2n +1 th column and the 2n-1 th column, if n is an even number, the column driving line is used for driving the element pixels of the 2n-2 nd column and the 2n th column, the grid electrodes of the element pixels are driven by grid driving lines, each column of the element pixels are respectively driven by two grid driving lines, the 4m-3 and 4m-2 pixels of the p-th column are driven by the 2p-1 th grid driving line, and the 4m-1 and 4m-2 m pixels of the p-th column are driven by the 2 p-th grid driving line, wherein in the s half period of single frame loading, the driving sequence of the grid electrodes is 4s-3, the second half period of single frame loading, The 4s-2, the 4s and the 4s-1, the charging frequency of the data line is reduced, the polarity change frequency is low, and the power consumption of the display screen is reduced. In summary, the new driving method of the present invention can better achieve the technical effect of reducing the power consumption of the image.

Description

display panel driving method

Technical Field

The present invention relates to a design of a panel pixel structure, and more particularly, to a driving method capable of eliminating a straight line phenomenon when a viewing angle changes.

Background

With the development of full-screen mobile phones, the lower frame of the display panel is required to be narrowed, and the lower frame of the panel can be reduced by the Dual gate technology. FIG. 1 is a conventional Z-arrangement dual gate panel architecture. The Dual gate technology can reduce the data line by half, so that the fanout area of the panel is smaller; the number of source output channels can be reduced by half, and the Y axis of the IC is further reduced; finally, the effect of reducing the lower frame of the panel is achieved.

fig. 1 shows a pixel arrangement structure of a panel in the prior art, and a panel of a Z-type arrangement dual gate panel is shown as a double row inversion, i.e. the polarities of liquid crystals are two rows positive and two rows negative, the spatial frequency of each frame of dual gate panel is relatively low, human eyes are sensitive to low frequency, and the brightness of the liquid crystal polarities is different between positive and negative. Human eyes watch the picture integratedly, generally integrate the time of two frames (default 60Hz display), when shaking the head to watch the pure color picture of the dual gate panel, only one frame of picture is seen, so the straight line phenomenon can be seen; when the panel is watched without shaking the head, the positive and negative polarities of the liquid crystal are continuously reversed, and the straight stripe phenomenon disappears when the integral of two or more frames with the positive liquid crystal polarity and the negative liquid crystal polarity is observed. This display defect is called a wobbling ruled line. As shown in fig. 2, the conventional Z-shaped arrangement causes a problem of poor display such as straight stripes when the viewing angle is changed. The simultaneous driving results in high power consumption of the associated panel.

Disclosure of Invention

Therefore, it is necessary to provide a new driving scheme for the display panel to achieve the technical effect of reducing the display power consumption of the panel.

To achieve the above object, the inventor provides a display panel driving method, wherein the display panel comprises a plurality of pixels arranged in an array, and further comprises a column driving line, for an nth column driving line from the left, if n is an odd number, the column driving line is used for driving the pixels of a 2n +1 column and a 2n-1 column, if n is an even number, the column driving line is used for driving the pixels of a 2n-2 column and a 2n column, the gates of the pixels are driven by a gate driving line, each column of pixels are respectively driven by two gate driving lines, the 4m-3 and 4m-2 pixels of a p column are driven by the 2p-1 gate driving line, the 4m-1 and 4m pixels of the p column are driven by the 2p gate driving line,

The method comprises the step that in the s-th half period of single frame picture loading, the driving sequence of the grid driving lines is 4s-3, 4s-2, 4s and 4 s-1.

Further, the driving time delay of the 4s-3 th, 4s-2 th, 4s-1 th stripes is one half period of four.

Different from the prior art, the data line has the advantages that the charging frequency is reduced, the polarity change frequency is low, and the power consumption of a display picture is reduced. In summary, the new driving method of the present invention can better achieve the technical effect of reducing the power consumption of the image.

Drawings

FIG. 1 is a schematic diagram of a prior art panel structure;

FIG. 2 is a schematic diagram of the head shaking ruled line phenomenon in the background art;

FIG. 3 is a schematic diagram of a display panel according to an embodiment;

FIG. 4 is a schematic diagram of a novel driving scheme according to an embodiment;

FIG. 5 is a data sequence diagram of dataline transmission according to one embodiment;

Fig. 6 is a diagram illustrating the transmission of dataline according to the present invention.

Detailed Description

To explain technical contents, structural features, and objects and effects of the technical solutions in detail, the following detailed description is given with reference to the accompanying drawings in conjunction with the embodiments.

referring to fig. 3, a display panel structure is included, the panel including an array of unit pixels, i.e., RGB pixel cells. And also includes column driving lines, i.e., source driving lines D1, D2, D3, D4, etc., for the nth column driving line from the left, if n is an odd number, the column driving line is used to drive the 2n +1 th column and the 2n-1 th column of pixels, and if n is an even number, the column driving line is used to drive the 2n-2 nd column and the 2n-2 nd column of pixels. The pixel polarity is column reversed. In the pixel arrangement example shown in fig. 3, the row arrangement sequence of the meta-pixels includes red meta-pixels, green meta-pixels, and blue meta-pixels. In order to eliminate the problems mentioned in the background art, the one column type arrangement proposed herein means that the IC outputs to the data line as column inversion, and the panel display is also column inversion, i.e. the liquid crystal polarity is one column positive and one column negative; taking D1 as an example, the first data line connects the near-end red sub-pixel and the far-end blue sub-pixel, so that the IC outputs to the data line as a single column inversion, and the panel display is also a single column inversion. When the panel is watched by shaking the head, compared with the traditional Z-shaped arranged double-row inversion, the spatial frequency of the picture seen by each frame is higher, so that the display difference caused by positive and negative polarities cannot be distinguished by human eyes, namely, shaking straight lines are eliminated.

In the specific embodiment shown in fig. 3, the gates of the meta-pixels are driven by gate driving lines, each column of pixels is driven by two gate driving lines, the 4m-3 and 4m-2 pixels of the p-th column are driven by the 2p-1 gate driving line, and the 4m-1 and 4m pixels of the p-th column are driven by the 2p gate driving line. As shown in the figure, the pixels of the first column are driven by G1 and G2, with the 1 st, 2 nd, 5 th, 6 th meta-pixel connected to G1 and the 3 rd, 4 th, 7 th, 8 th meta-pixel connected to a G2 drive line. Through the design, the grid electrodes of the two element pixels connected with the source driving line are opened on two different time domains, and the driving requirement of dualgate arrangement can be met.

In some further embodiments, as shown in FIG. 4, a display panel driving method is shown, which is suitable for the new display panel structure shown in the above figure, wherein the driving sequence of the gate driving lines is the 4s-3 th, the 4s-2 th, the 4s-1 th, and the second half period of the single frame loading. As shown in the figure, the clock driving of the GIP is as shown in the figure, CK1 … … CK8 corresponds to the gate driving line G1 … … G8 respectively, the timing of CK3 and CK4 are interchanged, and the timing of CK7 and CK8 are interchanged, namely the opening sequence of the gate line is changed from the original G1, G2, G3 and G4 … to G1, G2, G4 and G3 …, and the following gate is analogized, and the satisfactory gnt-4-Gn +4 is obtained. As can be seen from the figure, the clock driving signal CK is a square wave signal, and the high level occupies the length of one half period. In a further embodiment, we can see that the drive delay of stripes 4s-3, 4s-2, 4s-1 is one half cycle of four. Taking s as an example, in the first half cycle, CK1, CK2, CK4 and CK3 are arranged with a time delay of four and a half cycles. When S takes 2, the rule of CK5, CK6, CK8 and CK7, and then CK9, CK10, CK12 and CK11 continues to be delayed. The principle of specific power saving is discussed below.

In the embodiment shown in fig. 5, the data line transmission data sequence is arranged in a one column format. The principle that one column arrangement cannot reduce the pure color power consumption of the panel is shown, and similar to the conventional Z-type arrangement, taking the case that the panel displays a pure red picture R255 as an example, the changing sequence of D1 lines is as follows: +5V, 0, +5V, data line's frequency of charging is great, and display screen power consumption is great.

In the embodiment controlled by the novel driving method, the new display sequence is as shown in fig. 6, or the panel display is as a pure red image R255, and D1 line display sequence: +5V, 0, +5V, 0, the data line charge frequency is reduced, the polarity change frequency is low and the power consumption of the display screen is reduced. In summary, the new driving method of the present invention can better achieve the technical effect of reducing the power consumption of the image.

It should be noted that, although the above embodiments have been described herein, the invention is not limited thereto. Therefore, based on the innovative concepts of the present invention, the technical solutions of the present invention can be directly or indirectly applied to other related technical fields by making changes and modifications to the embodiments described herein, or by using equivalent structures or equivalent processes performed in the content of the present specification and the attached drawings, which are included in the scope of the present invention.

Claims (2)

1. A display panel driving method is characterized in that the display panel comprises array-arranged element pixels and also comprises column driving lines, wherein for the nth column driving line from the left, if n is an odd number, the column driving line is used for driving the element pixels of the 2n +1 column and the 2n-1 column, if n is an even number, the column driving line is used for driving the element pixels of the 2n-2 column and the 2n column, the grid electrodes of the element pixels are driven by grid driving lines, each column of pixels are respectively driven by two grid driving lines, the 4m-3 and 4m-2 pixels of the p column are driven by the 2p-1 grid driving line, the 4m-1 and 4m pixels of the p column are driven by the 2p grid driving line,

The method comprises the step that in the s-th half period of single frame picture loading, the driving sequence of the grid driving lines is 4s-3, 4s-2, 4s and 4 s-1.

2. The display panel driving method according to claim 1, wherein the driving time delay of the 4s-3 th, 4s-2 th, 4s-1 th stripes is one half cycle of four.