CN110569573A

CN110569573A - Fault confirmation and communication method based on programmable logic device

Info

Publication number: CN110569573A
Application number: CN201910780298.5A
Authority: CN
Inventors: 季冬冬; 薛广营; 张广乐
Original assignee: Suzhou Wave Intelligent Technology Co Ltd
Current assignee: Suzhou Wave Intelligent Technology Co Ltd
Priority date: 2019-08-22
Filing date: 2019-08-22
Publication date: 2019-12-13

Abstract

The invention provides a fault confirmation and communication method based on a programmable logic device, which comprises the following steps: the programmable logic device monitors the board key mark signal in real time; responding to the monitored signal to generate an abnormity, and continuously monitoring the abnormal signal by the programmable logic device within a specified time to confirm the abnormity; and responding to the confirmation of the abnormal occurrence, the programmable logic device executes fault protection measures and informs the fault information to the programmable logic devices of other boards. The invention adds a fault confirmation mechanism and a fault communication mechanism, and has important significance for the stability and the reliability of the whole switch system.

Description

Fault confirmation and communication method based on programmable logic device

Technical Field

The present invention relates to the field of computers, and more particularly, to a method for fault confirmation and communication based on a programmable logic device.

Background

the CPLD/FPGA is a semi-customized special integrated circuit, has the series advantages of flexible programming, quick response, high integration level and the like, and is more and more widely applied to the field of development, verification and control application in the prior period. In the switch system, the CPLD/FPGA chip is used for controlling the power-on and power-off sequence control, communication control, key detection, fan rotating speed control, SFP lighting control, serial port switching, I2C communication switching and the like of the whole switch.

Although the application of CPLDs/FPGAs is becoming more and more common in system design, in current switch system design, the CPLD/FPGA design does not enforce protection, but protects the switch system through the protection mechanism of the power chip itself (i.e., through the voltage regulator) when a fault occurs. But the voltage regulator has slow response speed, which may cause the phenomenon of 'board burning'.

therefore, if the CPLD/FPGA can be used for enforcing forced protection on abnormal faults, the method has important significance on system reliability.

Disclosure of Invention

in view of this, an object of the embodiments of the present invention is to provide a method for fault confirmation and communication based on a programmable logic device, so as to quickly respond to a board fault and prevent a "board burn-in" phenomenon.

In view of the above, an aspect of the embodiments of the present invention provides a method for fault confirmation and communication based on a programmable logic device, including the following steps:

the programmable logic device monitors the board key mark signal in real time;

responding to the monitored signal to generate an abnormity, and continuously monitoring the abnormal signal by the programmable logic device within a specified time to confirm the abnormity;

And responding to the confirmation of the abnormal occurrence, the programmable logic device executes fault protection measures and informs the fault information to the programmable logic devices of other boards.

In some embodiments, the programmable logic device comprises a CPLD, FPGA.

In some embodiments, the method is used in a switch system and/or a server system.

In some embodiments, the real-time monitoring of the board key signature signal by the programmable logic device comprises:

The programmable logic device monitors Power GOOD signals of the voltage regulator, key mark signals sent by the CPU/PCH and other key mark signals needing to be monitored according to project requirements.

in some embodiments, in response to an exception occurring in the monitored signal, the programmable logic device continuously monitoring the exception occurring signal for a prescribed time period to confirm the occurrence of the exception comprises:

And responding to the monitored signal to generate an exception, and the programmable logic device records exception information and uploads the exception information to the BMC to be stored in a log mode.

in some embodiments, in response to confirming that the exception occurs, the programmable logic device performing a fault protection measure and notifying the fault information to the programmable logic devices of the other boards includes:

In response to confirming the occurrence of the anomaly, the programmable logic device outputs a signal to shut down an initial power supply and/or a fault power supply.

in some embodiments, in response to confirming that the exception occurs, the programmable logic device performing a fault protection measure and notifying the fault information to the programmable logic devices of the other boards further comprises:

and after receiving the fault information, the programmable logic devices of the other boards output signals to turn off the initial power supply and/or the fault power supply.

In some embodiments, the clock signal of the programmable logic device is independent of the clock signal of the board.

In some embodiments, the method is based on a modular design.

Another aspect of the embodiments of the present invention provides a switch, which includes a processor and a memory, where the memory stores executable instructions that can be executed on the processor, and the instructions, when executed by the processor, implement the method as described above.

The invention has the following beneficial technical effects: the fault confirmation and communication method based on the programmable logic device provided by the embodiment of the invention adds a fault confirmation mechanism and a fault communication mechanism strategy, can prevent error protection of the CPLD-FPGA caused by misjudgment due to unstable signals, can ensure reliable protection of the CPLD-FPGA on the system when the system really fails, and simultaneously ensures protection of the whole system when the system fails by using a fault communication mechanism between boards, which has important significance on the stability and reliability of the whole system.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other embodiments can be obtained by using the drawings without creative efforts.

FIG. 1 is a flow chart of a method of fault validation and communication based on a programmable logic device according to the present invention;

FIG. 2 is a functional diagram of a fault confirmation mechanism and fault communication modularization based on CPLD-FPGA according to the present invention;

Fig. 3 is a functional diagram of the overall design of a system according to the method of the invention.

Detailed Description

Embodiments of the present invention are described below. However, it is to be understood that the disclosed embodiments are merely examples and that other embodiments may take various and alternative forms. The figures are not necessarily to scale; certain features may be exaggerated or minimized to show details of particular components. Therefore, specific structural and functional details disclosed herein are not to be interpreted as limiting, but merely as a representative basis for teaching one skilled in the art to variously employ the present invention. As one of ordinary skill in the art will appreciate, various features illustrated and described with reference to any one of the figures may be combined with features illustrated in one or more other figures to produce embodiments that are not explicitly illustrated or described. The combination of features shown provides a representative embodiment for a typical application. However, various combinations and modifications of the features consistent with the teachings of the present invention may be desired for certain specific applications or implementations.

In order to make the objects, technical solutions and advantages of the present invention more apparent, the following embodiments of the present invention are described in further detail with reference to the accompanying drawings.

In view of the above object, an aspect of the embodiments of the present invention provides a method for fault confirmation and communication based on a programmable logic device, as shown in fig. 1, including the following steps:

Step S101: the programmable logic device monitors the board key mark signal in real time;

Step S102: responding to the monitored signal to generate an abnormity, and continuously monitoring the abnormal signal by the programmable logic device within a specified time to confirm the abnormity;

step S103: and responding to the confirmation of the abnormal occurrence, the programmable logic device executes fault protection measures and informs the fault information to the programmable logic devices of other boards.

In some embodiments, the programmable logic device comprises a CPLD, FPGA. The CPLD-FPGA is a semi-customized special integrated circuit, has the series advantages of flexible programming, quick response, high integration level and the like, and is more and more widely applied to the field of development, verification and control application in the prior period.

In some embodiments, the method is used in a switch system and/or a server system. In the current switch system design, the CPLD-FPGA design does not enforce protection, but when a fault occurs, the switch system is protected through a power chip self-protection mechanism, and because the power chip has slower response of a fast clock compared with the CPLD-FPGA, abnormal faults can be enforced through the CPLD-FPGA. However, for the switch system, the requirement for stability is very high, so the problem must be confirmed before power-off protection; for the same system, if a plurality of CPLD-FPGA chips are contained, an interactive communication mechanism needs to be added when a fault occurs, so as to ensure the effectiveness of a protection mechanism. It should be understood that the method according to the present invention can be applied not only to the fault detection and protection of the switch system, but also to the fields requiring fault detection, validation, communication and protection, such as servers.

in some embodiments, the real-time monitoring of the board key flag signal by the programmable logic device comprises: the programmable logic device monitors Power GOOD signals of the voltage regulator, key mark signals sent by the CPU/PCH and other key mark signals needing to be monitored according to project requirements. In the switch system, the CPLD-FPGA can monitor the states of all power signals and key signals, and specific detection signals are determined according to project requirements.

In some embodiments, in response to an exception occurring in the monitored signal, the programmable logic device continuously monitoring the exception occurring signal for a prescribed time period to confirm the occurrence of the exception comprises: and responding to the monitored signal to generate an exception, and the programmable logic device records exception information and uploads the exception information to the BMC to be stored in a log mode. In the running process of the switch, the CPLD-FPGA programmable device is used for monitoring effective signals and key signals of a power supply in real time, when the signals are abnormal, error information is firstly recorded and uploaded to an upper management control BMC to be stored in a log mode, and then the CPLD-FPGA programmable device is used for further judging whether the abnormality really occurs.

In some embodiments, the programmable logic device, in response to confirming the occurrence of the exception, performing a fault protection measure and notifying the fault information to other boards, includes: in response to confirming the occurrence of the anomaly, the programmable logic device outputs a signal to shut down an initial power supply and/or a fault power supply. That is, if the abnormality occurs continuously, the CPLD-FPGA programmable device will implement forced protection by turning off the initial controllable power supply and the failure power supply.

In some embodiments, in response to confirming that the exception occurs, the programmable logic device performing a fault protection measure and notifying the fault information to the programmable logic devices of the other boards further comprises: and after receiving the fault information, the programmable logic devices of the other boards output signals to turn off the initial power supply and/or the fault power supply. Namely, the CPLD-FPGA logic chip on the failed board card carries out forced protection by switching off the initial controllable power supply and the failed power supply, and notifies the failure information to other board cards for protection.

In some embodiments, the method is based on a modular design. In order to facilitate application, the whole design adopts a modularization implementation method, a user does not need to care about implementation of bottom codes, more energy can be put on interface connection and other designs, and meanwhile, the modularization implementation method is convenient for transplantation on different projects.

In some embodiments, the modular design is implemented through a hardware description language. The module following the fault judgment and fault communication mechanism can be designed through a hardware description language Verilog, and then a burning file is generated through comprehensive compiling.

A functional diagram of the fault confirmation mechanism and the fault communication mechanism based on the CPLD-FPGA is shown in fig. 2. Wherein, the signals on the left side of fig. 2 are input signals, where "SYS _ CLK" is a module clock Signal, "RST _ N" is a module reset Signal, "Enable" is a module Enable Signal, and "Monitor _ Signal" is an input monitoring Signal, the monitoring signals mainly include VRPwrgd signals and key flag signals sent by CPU/PCH, and the specific detection signals are determined according to project requirements; the signal on the right side of fig. 2 is an output signal, where "Available _ Protect" is a module valid exception protection signal, which is sent when the exception signal is confirmed to be valid, and "Protect _ other" is a signal that the module outputs to notify other CPLD-FPGA of exception, which mainly notifies other boards of exception protection, mainly is an enable signal for turning off the most initial power supply, and ensures the validity of protection; the upper measurement signal "Monitor _ Time" in fig. 2 is a module parameter, which is used to configure the confirmation Time of the fault occurrence, that is, the module further confirms the abnormal signal within the Time specified by the Monitor _ Time parameter; the lower test signal "other _ Protect" in fig. 2 is failure information from other boards, and when the signal is valid, it proves that the other boards are failed, and at this time, the board executes a failure protection mechanism.

the general architecture of the system according to the invention comprises two parts, namely an in-board part and an inter-board part, wherein the in-board flow is as follows: signal monitoring → abnormal recording → fault confirmation → fault protection, the flow between boards is: other board card exception → fault protection, wherein the fault confirmation mechanism is mainly embodied in the board, and the fault communication mechanism is mainly embodied between the boards. As shown in fig. 3, wherein "STBY _ PG", "Main _ Power _ En", "Main _ Power _ PG", and "Key _ Signal" are monitoring signals, and these signals are input to the CPLD-FPGA fault monitoring module; when the abnormality is detected, firstly, the fault information is recorded, then whether the fault continuously occurs within a period of time is detected through a timer in the CPLD-FPGA, and the judgment is mainly carried out through the step because the requirement of the switch system on reliability is high, the false triggering caused by unstable signals is prevented, and meanwhile, the safety protection is carried out when the fault really occurs. When other board cards send fault information, namely fault information of the other board cards after judgment, the board card can immediately respond to the fault, namely the initial power supply and the fault power supply are cut off, and because the fault does not occur in the board card, only the initial power supply is actually cut off.

Where technically feasible, the technical features listed above for the different embodiments may be combined with each other or changed, added, omitted, etc. to form further embodiments within the scope of the invention.

It can be seen from the above embodiments that, the method for fault confirmation and communication based on a programmable logic device provided by the embodiments of the present invention adds a fault confirmation mechanism and a fault communication mechanism strategy, which can prevent error protection of the CPLD-FPGA caused by misjudgment due to unstable signals, and can ensure reliable protection of the CPLD-FPGA on the system when the system actually fails, and meanwhile, the fault communication mechanism between boards ensures protection of the entire system when the system fails, which has important significance on stability and reliability of the entire system; meanwhile, the design based on the CPLD-FPGA is convenient for different project applications and meets different project requirements, a modularization and parameterization realization method is adopted for the whole fault confirmation and fault communication mechanism, and the fault confirmation and fault communication mechanism is designed on the conventional CPLD-FPGA, so that the hardware cost is not increased.

In view of the above objects, in another aspect of the embodiments of the present invention, an embodiment of a switch is provided, where the switch includes a processor and a memory, and the memory stores executable instructions that can be executed on the processor, and when the instructions are executed by the processor, the method as described above is implemented.

Any embodiment of the switch that performs the programmable logic device based fault validation and communication method may achieve the same or similar effects as any of the preceding method embodiments to which it corresponds.

finally, it should be noted that, as will be understood by those skilled in the art, all or part of the processes in the methods of the above embodiments may be implemented by a computer program, which may be stored in a computer-readable storage medium, and when executed, may include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), a Random Access Memory (RAM), or the like.

In addition, the apparatuses, devices and the like disclosed in the embodiments of the present invention may be various electronic terminal devices, such as a mobile phone, a Personal Digital Assistant (PDA), a tablet computer (PAD), a smart television and the like, or may be a large terminal device, such as a server and the like, and therefore the scope of protection disclosed in the embodiments of the present invention should not be limited to a specific type of apparatus, device. The client disclosed in the embodiment of the present invention may be applied to any one of the above electronic terminal devices in the form of electronic hardware, computer software, or a combination of both.

Furthermore, the method disclosed according to an embodiment of the present invention may also be implemented as a computer program executed by a CPU, and the computer program may be stored in a computer-readable storage medium. The computer program, when executed by the CPU, performs the above-described functions defined in the method disclosed in the embodiments of the present invention.

further, the above method steps and system elements may also be implemented using a controller and a computer readable storage medium for storing a computer program for causing the controller to implement the functions of the above steps or elements.

Further, it should be appreciated that the computer-readable storage media (e.g., memory) described herein can be either volatile memory or nonvolatile memory, or can include both volatile and nonvolatile memory. By way of example, and not limitation, nonvolatile memory can include Read Only Memory (ROM), Programmable ROM (PROM), Electrically Programmable ROM (EPROM), Electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM), which can act as external cache memory. By way of example and not limitation, RAM may be available in a variety of forms such as synchronous RAM (DRAM), Dynamic RAM (DRAM), Synchronous DRAM (SDRAM), double data rate SDRAM (DDR SDRAM), Enhanced SDRAM (ESDRAM), Synchlink DRAM (SLDRAM), and Direct Rambus RAM (DRRAM). The storage devices of the disclosed aspects are intended to comprise, without being limited to, these and other suitable types of memory.

Those of skill would further appreciate that the various illustrative logical blocks, modules, circuits, and algorithm steps described in connection with the disclosure herein may be implemented as electronic hardware, computer software, or combinations of both. To clearly illustrate this interchangeability of hardware and software, various illustrative components, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. Whether such functionality is implemented as software or hardware depends upon the particular application and design constraints imposed on the overall system. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the disclosed embodiments of the present invention.

The various illustrative logical blocks, modules, and circuits described in connection with the disclosure herein may be implemented or performed with the following components designed to perform the functions described herein: a general purpose processor, a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. A general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. A processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP, and/or any other such configuration.

The steps of a method or algorithm described in connection with the disclosure herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium. In the alternative, the storage medium may be integral to the processor. The processor and the storage medium may reside in an ASIC. The ASIC may reside in a user terminal. In the alternative, the processor and the storage medium may reside as discrete components in a user terminal.

In one or more exemplary designs, the functions may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functions may be stored on or transmitted over as one or more instructions or code on a computer-readable medium. Computer-readable media includes both computer storage media and communication media including any medium that facilitates transfer of a computer program from one place to another. A storage media may be any available media that can be accessed by a general purpose or special purpose computer. By way of example, and not limitation, such computer-readable media can comprise RAM, ROM, EEPROM, CD-ROM or other optical disk storage, magnetic disk storage or other magnetic storage devices, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and that can be accessed by a general-purpose or special-purpose computer, or a general-purpose or special-purpose processor. Also, any connection is properly termed a computer-readable medium. For example, if the software is transmitted from a website, server, or other remote source using a coaxial cable, fiber optic cable, twisted pair, Digital Subscriber Line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. Disk and disc, as used herein, includes Compact Disc (CD), laser disc, optical disc, Digital Versatile Disc (DVD), floppy disk, blu-ray disc where disks usually reproduce data magnetically, while discs reproduce data optically with lasers. Combinations of the above should also be included within the scope of computer-readable media.

It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly supports the exception. It should also be understood that "and/or" as used herein is meant to include any and all possible combinations of one or more of the associated listed items.

The numbers of the embodiments disclosed in the embodiments of the present invention are merely for description, and do not represent the merits of the embodiments.

It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program instructing relevant hardware, where the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a magnetic disk, an optical disk, or the like.

The above-described embodiments are possible examples of implementations and are presented merely for a clear understanding of the principles of the invention. Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, of embodiments of the invention is limited to these examples; within the idea of an embodiment of the invention, also technical features in the above embodiment or in different embodiments may be combined and there are many other variations of the different aspects of an embodiment of the invention as described above, which are not provided in detail for the sake of brevity. Therefore, any omissions, modifications, substitutions, improvements, and the like that may be made without departing from the spirit and principles of the embodiments of the present invention are intended to be included within the scope of the embodiments of the present invention.

Claims

1. a method for fault confirmation and communication based on a programmable logic device, comprising the steps of:

The programmable logic device monitors the board key mark signal in real time;

2. The method of claim 1, wherein the programmable logic device comprises a CPLD, an FPGA.

3. The method according to claim 1, wherein the method is used in a switch system and/or a server system.

4. the method of claim 1, wherein the programmable logic device monitoring board key flag signals in real time comprises:

5. The method of claim 1, wherein in response to an exception occurring in the monitored signal, the programmable logic device continuously monitoring the exception occurring signal for a prescribed time to confirm the occurrence of the exception comprises:

6. The method of claim 1, wherein in response to confirming the exception occurred, the programmable logic device performing fault protection measures and notifying programmable logic devices of other boards of the fault information comprises:

7. The method of claim 6, wherein in response to confirming the exception occurred, the programmable logic device performing fault protection measures and notifying programmable logic devices of other boards of the fault information further comprises:

8. the method of claim 1, wherein the clock signal of the programmable logic device is independent of the clock signal of the board.

9. The method of claim 1, wherein the method is based on a modular design.

10. A switch, characterized in that the switch comprises a processor and a memory storing executable instructions executable on the processor, which instructions, when executed by the processor, implement the method according to any of claims 1-9.