CN110568749A - time-to-digital converter circuit, time-to-digital converter device, time-to-digital converter apparatus, and method of controlling time-to-digital converter device - Google Patents
time-to-digital converter circuit, time-to-digital converter device, time-to-digital converter apparatus, and method of controlling time-to-digital converter device Download PDFInfo
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- G04—HOROLOGY
- G04F—TIME-INTERVAL MEASURING
- G04F10/00—Apparatus for measuring unknown time intervals by electric means
- G04F10/005—Time-to-digital converters [TDC]
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Abstract
the invention discloses a time-to-digital converter circuit, a device, equipment and a control method of the device, wherein the time-to-digital converter circuit comprises a logic synchronization circuit, a time-to-digital converter and a time amplitude converter module; the logic synchronization circuit separates the start signal and the stop signal and outputs a counting clock signal, a time amplitude conversion start signal and a time amplitude conversion stop signal; the time-to-digital converter counts according to the counting clock signal; and the time amplitude converter module is used for receiving the reference current, the time amplitude conversion starting signal and the time amplitude conversion stopping signal and timing according to the reference current, the time amplitude conversion starting signal and the time amplitude conversion stopping signal. The time amplitude converter module and the logic synchronous circuit are adopted to improve the time resolution of the time digital converter, the number of digital circuits is small, the area is saved, and the time resolution of the time digital converter is improved.
Description
Technical Field
the present invention relates to the field of time-to-digital converter technologies, and in particular, to a time-to-digital converter circuit, a time-to-digital converter apparatus, a device, and a method for controlling the time-to-digital converter apparatus.
Background
with respect To Time of flight (TOF) Time measurement, a Time To Digital Converter (TDC) plays a major role, and its main function is To convert a Time interval To be measured into a Digital signal and obtain the Time interval by calculation, which is essentially a multi-bit counter, but its Time resolution is at least one clock cycle of an external clock clk, so that the requirement of measuring a Time interval shorter than one clock cycle of clk cannot be met. Applications are wide, such as TOF _3D imaging in combination with camera principles, measurement of fluorescence time of fluorescent materials in material physics, etc.
However, the methods currently employed with respect to time-of-flight measurements are: the coarse counting is realized by a counter, the fine counting is realized by a vernier method TDC and the like, the essence of the method is a multi-stage delay chain, the time resolution of the TDC can be improved, but the layout area is too large, large array integration cannot be realized, and the method is extremely unfavorable for finishing an array TOF chip.
Disclosure of Invention
The invention mainly aims to provide a time-to-digital converter circuit, a time-to-digital converter device, a time-to-digital converter equipment and a control method of the time-to-digital converter device, and aims to solve the technical problem of how to improve the time resolution of a TDC and avoid too large layout area in the prior art.
in order to achieve the above object, the time-to-digital converter circuit provided by the present invention includes a logic synchronization circuit, a time-to-digital converter, and a time-to-amplitude converter module, wherein a first output terminal of the logic synchronization circuit is connected to the time-to-digital converter, and a second output terminal of the logic synchronization circuit is connected to an input terminal of the time-to-amplitude converter module;
the logic synchronization circuit is used for receiving a clock signal, a starting signal and a stopping signal, separating the starting signal and the stopping signal and outputting a counting clock signal, a time amplitude conversion starting signal and a time amplitude conversion stopping signal;
The time-to-digital converter is used for receiving the counting clock signal and counting according to the counting clock signal;
The time-amplitude converter module is configured to receive a reference current, the time-amplitude conversion start signal, and the time-amplitude conversion end signal, and perform timing according to the reference current, the time-amplitude conversion start signal, and the time-amplitude conversion end signal.
Preferably, the time-amplitude converter module comprises a signal generating circuit and a time-amplitude converter;
the second output end of the logic synchronization circuit is connected with the input end of the signal generation circuit, and the output end of the signal generation circuit is connected with the input end of the time-amplitude converter;
The signal generating circuit is used for receiving the time-amplitude conversion starting signal and the time-amplitude conversion stopping signal and outputting a fine counting enable signal and a reset signal;
The time-amplitude converter is configured to receive a reference current, the fine count enable signal, and the reset signal, and perform timing according to the reference current and reset according to the reset signal when the fine count enable signal is low.
preferably, the time-amplitude converter includes: a MOS transistor circuit module and a capacitor;
the output end of the signal generating circuit is connected with the first end of the MOS tube circuit module, and the second end of the MOS tube circuit module is connected with the capacitor;
the MOS tube circuit module is used for receiving a reference current and the fine counting enable signal, controlling whether to charge the capacitor or not through the fine counting enable signal and controlling whether to reset the capacitor or not according to the reset signal;
And the capacitor is used for timing according to the reference current and resetting according to the reset signal.
preferably, the time-to-digital converter comprises a counter.
Preferably, the logic synchronization circuit comprises a flip-flop module, an or gate and an and gate module;
The first end of the trigger module is used for receiving a clock signal, a start signal and a termination signal;
The second end of the trigger module is connected with the first end of the AND gate module, and the second end of the trigger module is also connected with the OR gate;
And the second end of the AND gate module is connected with the first end of the counter, and the second end of the counter is connected with the time-amplitude converter module.
preferably, the trigger module comprises a first trigger, a second trigger and a third trigger; the AND gate module comprises a first AND gate and a second AND gate;
The input end of the first trigger receives a start signal, the first output end of the first trigger is connected with the input end of the second trigger, the output end of the second trigger is connected with the first input end of the first AND gate, the output end of the first AND gate is connected with the input end of the second AND gate, the output end of the second AND gate is connected with the first end of the counter, the input end of the third trigger receives a termination signal, the output end of the third trigger is connected with the second input end of the first AND gate, the second output end of the first trigger is connected with the first input end of the OR gate, and the output end of the second trigger is further connected with the second input end of the OR gate.
The present invention provides a method for controlling a time-to-digital converter device, which is applied to the time-to-digital converter device as described above and is based on a time-to-digital converter circuit, wherein the time-to-digital converter circuit comprises a logic synchronization circuit, a time-to-digital converter and a time amplitude converter module, and the method for controlling the time-to-digital converter device comprises the following steps:
the logic synchronization circuit receives a clock signal, a start signal and a stop signal, separates the start signal from the stop signal and outputs a counting clock signal, a time amplitude conversion start signal and a time amplitude conversion stop signal;
the time-to-digital converter receives the counting clock signal and counts according to the counting clock signal;
The time-amplitude converter module receives a reference current, the time-amplitude conversion starting signal and the time-amplitude conversion ending signal, and performs timing according to the reference current, the time-amplitude conversion starting signal and the time-amplitude conversion ending signal.
Preferably, the time-amplitude converter module comprises a signal generating circuit and a time-amplitude converter; the time-amplitude converter module receives a reference current, the time-amplitude conversion start signal and the time-amplitude conversion end signal, and performs timing according to the reference current, the time-amplitude conversion start signal and the time-amplitude conversion end signal, and specifically includes:
the signal generating circuit receives the time-amplitude conversion starting signal and the time-amplitude conversion stopping signal and outputs a fine count enabling signal and a reset signal;
The time-amplitude converter receives a reference current, the fine count enable signal, and the reset signal, performs timing based on the reference current when the fine count enable signal is low, and performs reset based on the reset signal.
The invention also proposes a time-to-digital converter device comprising a time-to-digital converter circuit as described above.
The invention also proposes a time-to-digital converter device comprising a time-to-digital converter apparatus as described above, or applying a control method of a time-to-digital converter apparatus as described above.
the invention discloses a time-to-digital converter circuit, which comprises a logic synchronization circuit, a time-to-digital converter and a time amplitude converter module, wherein a first output end of the logic synchronization circuit is connected with the time-to-digital converter, a second output end of the logic synchronization circuit is connected with an input end of the time amplitude converter module, and the logic synchronization circuit is used for receiving a clock signal, a start signal and an end signal, separating the start signal and the end signal and outputting a counting clock signal, a time amplitude conversion start signal and a time amplitude conversion end signal, so that the problem of a metastable state is solved; the time-to-digital converter is used for receiving the counting clock signal and counting according to the counting clock signal, the time-to-amplitude converter module is used for receiving a reference current, the time-to-amplitude conversion starting signal and the time-to-amplitude conversion ending signal, timing is carried out according to the reference current, the time-to-amplitude conversion starting signal and the time-to-amplitude conversion ending signal, the time-to-amplitude converter module and the logic synchronization circuit are adopted to jointly improve the time resolution of the time-to-digital converter, the number of digital circuits is small, the area is saved, and meanwhile the time resolution of the time-to-digital converter is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
FIG. 1 is a functional block diagram of a time-to-digital converter circuit according to a first embodiment of the present invention;
FIG. 2 is a timing diagram of a time-to-digital converter circuit according to a first embodiment of the present invention;
FIG. 3 is a functional block diagram of a time-to-digital converter circuit according to a second embodiment of the present invention;
FIG. 4 is a circuit schematic of a third embodiment of a time-to-digital converter circuit of the present invention;
FIG. 5 is a timing diagram illustrating a time-to-digital converter circuit according to a third embodiment of the present invention;
FIG. 6 is a schematic circuit diagram of a logic synchronization circuit in a fourth embodiment of a time-to-digital converter circuit according to the present invention;
FIG. 7 is an ideal timing diagram of a time-to-digital converter circuit according to a fourth embodiment of the present invention;
FIG. 8 is an error timing diagram of a time-to-digital converter circuit according to a fourth embodiment of the present invention;
FIG. 9 is a timing diagram of the operation of the synchronization signals of the time-to-digital converter circuit according to the fourth embodiment of the present invention;
FIG. 10 is a flowchart illustrating a control method of a time-to-digital converter apparatus according to a first embodiment of the present invention.
the reference numbers illustrate:
| Reference numerals | Name (R) | reference numerals | Name (R) |
| 100 | Logic synchronous circuit | 201 | counter with a memory |
| 200 | time-to-digital converter | M1 | First MOS transistor |
| 300 | Time-amplitude converter module | M2 | second MOS transistor |
| 301 | Signal generating circuit | M3 | third MOS transistor |
| 302 | Time-amplitude converter | M4 | Fourth MOS transistor |
| C | Capacitor with a capacitor element | M5 | Fifth MOS transistor |
| H | OR gate | M6 | sixth MOS transistor |
| D1 | First trigger | D3 | Third trigger |
| D2 | Second trigger | Y1 | first AND gate |
| Y2 | second AND gate |
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that all the directional indicators (such as up, down, left, right, front, and rear … …) in the embodiment of the present invention are only used to explain the relative position relationship between the components, the movement situation, etc. in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indicator is changed accordingly.
in addition, the descriptions related to "first", "second", etc. in the present invention are for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, the technical solutions in the embodiments may be combined with each other, but it must be based on the realization of those skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination should be considered to be absent and not within the protection scope of the present invention.
The invention provides a time-to-digital converter circuit.
Referring to fig. 1, fig. 1 is a functional block diagram of a time-to-digital converter circuit according to a first embodiment of the present invention.
As shown in fig. 1, in the embodiment of the present invention, the time-to-digital converter circuit includes a logic synchronization circuit 100, a time-to-digital converter 200, and a time-to-amplitude converter module 300, wherein a first output terminal of the logic synchronization circuit 100 is connected to the time-to-digital converter 200, and a second output terminal of the logic synchronization circuit 100 is connected to an input terminal of the time-to-amplitude converter module 300;
the logic synchronization circuit 100 is configured to receive a clock signal, a start signal, and a stop signal, separate the start signal and the stop signal, and output a count clock signal, a time-amplitude conversion start signal, and a time-amplitude conversion stop signal;
The time-to-digital converter 200 is configured to receive the counting clock signal and count according to the counting clock signal;
The time-amplitude converter module 300 is configured to receive a reference current, the time-amplitude conversion start signal, and the time-amplitude conversion end signal, and perform timing according to the reference current, the time-amplitude conversion start signal, and the time-amplitude conversion end signal.
It should be understood that, in order to improve the Time resolution of the TDC, the most basic Time-to-Amplitude Converter (TAC) structure and logic synchronization circuit 100 is added, and the number of digital circuits is small, thereby greatly saving the area and improving the Time resolution of the TDC. The principle is as follows:
As shown in fig. 1, the logic synchronization circuit 100 mainly implements strict separation of the START signal of the coarse-and-fine count, as shown in fig. 2, fig. 2 is a timing diagram of a first embodiment of the time-to-digital converter circuit of the present invention, and after the START (START) signal of a certain event comes, there is a certain time difference between the START (START) signal and the STOP (STOP) signal given from the outside, the time difference is divided into two parts, i.e., the coarse count and the fine count, and the STOP signal is a signal completely synchronized with the reference clock, so as to generate only one fine count for the purpose of experiment.
The logic synchronization circuit 100 receives the clock signal, the start signal, and the stop signal, separates the start signal and the stop signal, that is, strictly separates the start signal of the coarse-fine count, and outputs the count clock signal, the time-amplitude-conversion start signal, and the time-amplitude-conversion stop signal. The counting clock signal COUNTER _ CLK is used as an input of the time-to-digital converter, the time-to-digital converter receives the counting clock signal, counts according to the counting clock signal, COUNTER _ CLK is a starting signal of rough counting and is synchronous with the clock signal CLK in a rough counting time period, a rising edge is effective, the time-to-digital converter comprises a COUNTER, the COUNTER counts once every rising edge, and finally, the rough counting time Td is the counting times T, wherein T is the period of the CLK clock.
the time-amplitude converter module 300 receives a reference current, the time-amplitude conversion start signal and the time-amplitude conversion end signal, the time-amplitude converter module 300 includes a signal generating circuit and a time-amplitude converter, the signal generating circuit receives the time-amplitude conversion start signal and the time-amplitude conversion end signal and outputs a CUR _ CON signal, the CUR _ CON is a fine count enable signal, and when the CUR _ CON is active low, the time-amplitude converter in the time-amplitude converter module 300 is charged and timed in the period of time.
in the embodiment, the TAC and the logic synchronization circuit are adopted to improve the time resolution of the TDC together, so that the number of digital circuits is small, the area is greatly saved, and the time resolution of the TDC is improved.
Referring to fig. 3, fig. 3 is a functional block diagram of a time-to-digital converter circuit according to a second embodiment of the present invention.
As shown in fig. 3, in the embodiment of the present invention, the time-amplitude converter module 300 includes a signal generating circuit 301 and a time-amplitude converter 302;
a second output terminal of the logic synchronization circuit 100 is connected to an input terminal of the signal generation circuit 301, and an output terminal of the signal generation circuit 301 is connected to an input terminal of the time-amplitude converter 302;
The signal generating circuit 301 is configured to receive the time-amplitude conversion start signal and the time-amplitude conversion end signal, and output a fine count enable signal and a reset signal;
The time-amplitude converter 302 is configured to receive a reference current, the fine count enable signal, and the reset signal, count time according to the reference current when the fine count enable signal is low, and reset according to the reset signal.
it should be noted that the second output terminal of the logic synchronization circuit 100 outputs the time-amplitude conversion start signal and the time-amplitude conversion stop signal, the second output terminal of the logic synchronization circuit 100 is connected to the input terminal of the signal generation circuit 301, the signal generation circuit 301 receives the time-amplitude conversion start signal and the time-amplitude conversion stop signal as input, and the signal generation circuit 301 outputs the fine count enable signal CUR _ CON and the RESET signal RESET, where the RESET signal is the RESET signal of the TAC.
it is understood that the time-amplitude converter 302 is configured to receive the reference current, the fine count enable signal CUR _ CON and the RESET signal RESET, when the rising edge of the START signal comes together with the rising edge of CLK, as shown in fig. 4, fig. 4 is a second timing diagram of the first embodiment of the time-to-digital converter circuit of the present invention, and the time of the fine count is longest, i.e. one entire clock cycle. The time-to-amplitude converter 302 includes a capacitor, and the time difference between TART and STOP is the coarse count + the fine count. IREF is a reference current, and the capacitor is charged by the power supply within a fixed time period by giving a fixed current from the outside; when CUR _ CON is low, the power supply starts to charge the capacitor, and when the signal is high, the external circuit starts to read out the voltage at the two ends of the capacitor; the RESET signal is a RESET signal, and when an external circuit reads out the voltage of the capacitor, the RESET signal is high, and the capacitor is RESET to wait for the next charging timing.
In the embodiment, the time amplitude converter and the logic synchronous circuit are adopted to improve the time resolution of the TDC, so that the digital circuits are few, and the area is greatly saved.
Referring to fig. 4, fig. 4 is a schematic circuit diagram of a time-to-digital converter circuit according to a third embodiment of the present invention.
As shown in fig. 4, in the present embodiment, the time-amplitude converter 302 includes: a MOS transistor circuit module and a capacitor C;
the output end of the signal generating circuit 301 is connected to the first end of the MOS transistor circuit module, and the second end of the MOS transistor circuit module is connected to the capacitor C;
The MOS tube circuit module is used for receiving a reference current and the fine counting enable signal, controlling whether to charge the capacitor C or not through the fine counting enable signal and controlling whether to reset the capacitor C or not according to the reset signal;
and the capacitor C is used for timing according to the reference current and resetting according to the reset signal.
In a specific implementation, IREF is a reference current, and a fixed current is given from the outside to charge the capacitor C in a fixed time period by a power supply; the MOS tube circuit module is equivalent to a switch circuit, when the count enable signal CUR _ CON is low, the MOS tube circuit module is conducted, a power supply starts to charge the capacitor C, when the count enable signal CUR _ CON is high, the MOS tube circuit module is switched off, and an external circuit starts to read out the voltage at two ends of the capacitor C; the RESET is a RESET signal, and when an external circuit reads out a voltage of the capacitor C, the RESET signal is high, and RESETs the capacitor C to wait for the next charging timing.
in this embodiment, the MOS transistor circuit module includes a first MOS transistor M1, a second MOS transistor M2, a third MOS transistor M3, a fourth MOS transistor M4, a fifth MOS transistor M5, and a sixth MOS transistor M6;
the first output end of the signal generating circuit is connected to the gate of the fifth MOS transistor M5, the source of the fifth MOS transistor M5 is connected to the drain of the fourth MOS transistor M4, the gate of the fourth MOS transistor M4 is connected to the gate of the third MOS transistor M3, the source of the fourth MOS transistor M4 is connected to the drain of the second MOS transistor M2, the source of the second MOS transistor M2 is connected to the source of the first MOS transistor M1, the gate of the first MOS transistor M1 is connected to the gate of the second MOS transistor M2, the drain of the first MOS transistor M1 is connected to the source of the third MOS transistor M3, the drain of the sixth MOS transistor M6 is connected to the drain of the fifth MOS transistor M5, the drain of the sixth transistor M6 is further connected to the first end of the capacitor, the source of the sixth MOS transistor M6 is connected to the second end of the capacitor, and the drain of the third MOS transistor M3 receives the reference current, the gate of the fifth MOS transistor M5 receives the fine count enable signal, and the gate of the sixth MOS transistor M6 receives the reset signal.
It should be understood that the fifth MOS transistor M5 in the MOS transistor circuit block corresponds to a switch circuit, when the fine count enable signal CUR _ CON is low, the fifth MOS transistor M5 is turned on, the power supply starts to charge the capacitor C, when the fine count enable signal CUR _ CON is high, the fifth MOS transistor M5 is turned off, and the external circuit starts to read out the voltage across the capacitor C; the RESET is a RESET signal, and when an external circuit reads out the voltage of the capacitor C, the RESET signal is high, the sixth MOS transistor M6 is turned on, and RESETs the capacitor C to wait for the next charging timing. The source of the second MOS transistor M2 is connected to the source of the first MOS transistor M1, and an AVDD, which is an analog voltage or an analog positive power supply, is provided from the chip.
in this embodiment, the time-to-digital converter 200 includes a counter 201.
It is understood that COUNTER _ CLK is a start signal of the rough count, and is synchronized with CLK during the rough count period, the rising edge is active, for the COUNTER 201, the COUNTER 201 counts once every rising edge, and the final rough count time Td is the number of counts T, where T is the period of the CLK clock; calculation of the fine count: when the rising edge of the START signal comes together with the rising edge of CLK, as shown in fig. 5, fig. 5 is a timing diagram of a third embodiment of the time-to-digital converter circuit of the present invention, the time of the fine count is longest, i.e. one entire clock cycle, the voltage on the capacitor C also reaches the maximum value Vmax, and then the time of the fine count is (V/Vmax) × T, where T is the period of CLK. The time difference between START and STOP is the coarse count + the fine count.
in this embodiment, the counter 201 in the time-to-digital converter 200 counts, the logic synchronization circuit 100 strictly separates the start signals of the coarse and fine counts, so as to improve the counting accuracy, and the time-to-amplitude converter 302 composed of the MOS transistor circuit module and the capacitor C improves the time resolution of the TDC.
Referring to fig. 6, fig. 6 is a schematic circuit diagram of a logic synchronization circuit in a fourth embodiment of the time-to-digital converter circuit according to the present invention.
As shown in fig. 6, in the present embodiment, the logic synchronization circuit 100 includes a flip-flop module, an or gate H, and an and gate module;
The first end of the trigger module is used for receiving a clock signal, a start signal and a termination signal;
the second end of the trigger module is connected with the first end of the AND gate module, and the second end of the trigger module is also connected with the OR gate H;
And the second end of the AND gate module is connected with the first end of the counter, and the second end of the counter is connected with the time-amplitude converter module.
It should be understood that, referring to fig. 7, fig. 7 is an ideal timing chart of the time-to-digital converter circuit according to the fourth embodiment of the present invention, and as shown in fig. 7, it is an ideal timing case, and the coarse 9321 count is performed after the fine count is finished. However, there is also a case where we have no way to predict, referring to fig. 8, fig. 8 is an error timing diagram of a fourth embodiment of the time-to-digital converter circuit of the present invention, as shown in fig. 8: when the start signal of an event comes along with the rising edge of the external reference clock, if not controlled by the strict synchronization circuit, the coarse count enable signal will have a wrong timing, which results in the TDC calculating one more clock cycle, and thus, the time accuracy of the TDC is seriously affected.
it should be noted that, in order to solve the problem of the TDC metastable state, the logic synchronization circuit 100 for improving the time resolution includes a flip-flop module, an or gate H, and an and gate module, and compared with a common method for improving the TDC precision by using a multi-stage delay chain, the logic synchronization circuit 100 plus TAC can save a lot of layout area.
As shown in fig. 6, in the present embodiment, the flip-flop module includes a first flip-flop D1, a second flip-flop D2, and a third flip-flop D3; the AND gate module comprises a first AND gate Y1 and a second AND gate Y2;
An input end of the first flip-flop D1 receives a start signal, a first output end of the first flip-flop D1 is connected to an input end of the second flip-flop D2, an output end of the second flip-flop D2 is connected to a first input end a1 of the first and gate Y1, an output end Z1 of the first and gate Y1 is connected to an input end of the second and gate Y2, an output end of the second and gate Y2 is connected to a first end of the counter 201, an input end of the third flip-flop D3 receives a termination signal, an output end of the third flip-flop D3 is connected to a second input end of the first and gate Y1, a second output end of the first flip-flop D1 is connected to a first input end of the or gate H, and an output end of the second flip-flop D2 is further connected to a second input end of the or gate H.
It can be appreciated that, as shown in fig. 6, the logic synchronization circuit 100 is implemented with only three D flip-flops, two and gates, and one or gate, a first input terminal of the first flip-flop D1 and a first input terminal of the third flip-flop receive an external voltage VDD, a second input of the first flip-flop D1 receives a START signal START, a second input of the third flip-flop D3 receives a STOP signal STOP, the output terminal of the second and gate Y2 outputs a count clock signal COUNTER _ CLK, which is a start signal of rough counting, and a rising edge is active in synchronization with the clock signal CLK for a coarse count period, the time-to-digital converter comprising a counter, for the counter, the counter counts once every rising edge, and the final coarse count time Td is the count times T, where T is the period of the CLK clock. A second output terminal of the first flip-flop D1 is connected to a first input terminal of the or gate H, a second output terminal of the first flip-flop D1 outputs the time-amplitude conversion START signal START _ TAC, an output terminal of the second flip-flop D2 is further connected to a second input terminal of the or gate H, and an output terminal of the second flip-flop D2 outputs the time-amplitude conversion STOP _ TAC, so that the output terminal of the or gate H outputs the fine count enable signal CUR _ CON. A first output terminal of the first flip-flop D1 is connected to a first input terminal of the second flip-flop D2, a second input terminal of the second flip-flop is inputted with the clock signal CLK, an output terminal Z1 of the first and gate Y1 is connected to a first input terminal of the second and gate Y2, and a second input terminal of the second and gate Y2 is inputted with the clock signal CLK. Referring to fig. 9, fig. 9 is a timing diagram of a synchronization signal operation in a fourth embodiment of the time-to-digital converter circuit of the present invention, and a specific timing sequence of the synchronization signal operation is shown in fig. 9, which can be obtained by combining the schematic circuit diagram of fig. 6.
The logic synchronization circuit adopted by the embodiment has a compact structure and strict time sequence control, and can well improve the time resolution of the TDC.
the present invention further provides a time-to-digital converter apparatus, which includes the time-to-digital converter circuit as described above, and the specific structure of the time-to-digital converter circuit refers to the above embodiments. The time-to-digital converter device may be a time-to-digital converter hand washer or the like.
Based on the time-to-digital converter apparatus, referring to fig. 10, the present invention further provides a first embodiment of a method for controlling the time-to-digital converter apparatus.
The control method is based on a time-to-digital converter circuit, the time-to-digital converter circuit comprises a logic synchronization circuit, a time-to-digital converter and a time-to-amplitude converter module, and the control method of the time-to-digital converter device comprises the following steps:
step S10: the logic synchronization circuit receives a clock signal, a start signal and a stop signal, separates the start signal from the stop signal and outputs a counting clock signal, a time amplitude conversion start signal and a time amplitude conversion stop signal;
step S20: the time-to-digital converter receives the counting clock signal and counts according to the counting clock signal;
Step S30: the time-amplitude converter module receives a reference current, the time-amplitude conversion starting signal and the time-amplitude conversion ending signal, and performs timing according to the reference current, the time-amplitude conversion starting signal and the time-amplitude conversion ending signal.
In this embodiment, the time-to-digital converter circuit includes a logic synchronization circuit, a time-to-digital converter, and a time-to-amplitude converter module, wherein a first output terminal of the logic synchronization circuit is connected to the time-to-digital converter, and a second output terminal of the logic synchronization circuit is connected to an input terminal of the time-to-amplitude converter module.
It should be understood that, in order to improve the Time resolution of the TDC, a most basic Time-to-Amplitude Converter (TAC) structure and a logic synchronization circuit are added, and the number of digital circuits is small, thereby greatly saving the area and improving the Time resolution of the TDC. The principle is as follows:
as shown in fig. 1, the logic synchronization circuit mainly implements strict separation of the START signal of the coarse count, as shown in fig. 2, fig. 2 is a timing diagram of a first embodiment of the time-to-digital converter circuit of the present invention, and after the START (START) signal of a certain event comes, there is a certain time difference between the START (START) signal and the STOP (STOP) signal given from the outside, the time difference is divided into two parts, namely, the coarse count and the fine count, and the STOP signal is a signal completely synchronized with the reference clock, so as to generate only a fine count for the purpose of experiment.
The logic synchronization circuit receives the clock signal, the start signal and the stop signal, separates the start signal and the stop signal, namely, realizes strict separation of the start signal of thickness counting, and outputs the counting clock signal, the time-amplitude conversion start signal and the time-amplitude conversion stop signal. The counting clock signal COUNTER _ CLK is used as an input of the time-to-digital converter, the time-to-digital converter receives the counting clock signal, counts according to the counting clock signal, COUNTER _ CLK is a starting signal of rough counting and is synchronous with the clock signal CLK in a rough counting time period, a rising edge is effective, the time-to-digital converter comprises a COUNTER, the COUNTER counts once every rising edge, and finally, the rough counting time Td is the counting times T, wherein T is the period of the CLK clock.
The time-amplitude converter module receives a reference current, the time-amplitude conversion start signal and the time-amplitude conversion end signal, and comprises a signal generation circuit and a time-amplitude converter, wherein the signal generation circuit receives the time-amplitude conversion start signal and the time-amplitude conversion end signal and outputs a CUR _ CON signal, the CUR _ CON signal is a fine count enable signal, and when the CUR _ CON is low and effective, the time-amplitude converter in the time-amplitude converter module is charged and timed in the period of time.
In this embodiment, the time-amplitude converter module includes a signal generating circuit and a time-amplitude converter; the step S30 includes:
the signal generating circuit receives the time-amplitude conversion starting signal and the time-amplitude conversion stopping signal and outputs a fine count enabling signal and a reset signal;
the time-amplitude converter receives a reference current, the fine count enable signal, and the reset signal, performs timing based on the reference current when the fine count enable signal is low, and performs reset based on the reset signal.
it should be noted that the second output terminal of the logic synchronization circuit outputs the time-amplitude conversion start signal and the time-amplitude conversion stop signal, the second output terminal of the logic synchronization circuit is connected to the input terminal of the signal generation circuit, the signal generation circuit receives the time-amplitude conversion start signal and the time-amplitude conversion stop signal as input, the signal generation circuit outputs the fine count enable signal CUR _ CON and the RESET signal RESET, and the RESET signal is the RESET signal of the TAC.
It can be understood that, the time-amplitude converter is configured to receive the reference current, the fine count enable signal CUR _ CON and the RESET signal RESET, when the rising edge of the START signal comes together with the rising edge of CLK, as shown in fig. 4, fig. 4 is a second timing diagram of the first embodiment of the time-to-digital converter circuit of the present invention, and the time of the fine count is longest, i.e. one entire clock cycle. The time-amplitude converter comprises a capacitor, and the time difference between the TART and STOP is the coarse count + the fine count. IREF is a reference current, and the capacitor is charged by the power supply within a fixed time period by giving a fixed current from the outside; when CUR _ CON is low, the power supply starts to charge the capacitor, and when the signal is high, the external circuit starts to read out the voltage at the two ends of the capacitor; the RESET signal is a RESET signal, and when an external circuit reads out the voltage of the capacitor, the RESET signal is high, and the capacitor is RESET to wait for the next charging timing.
In the embodiment, the TAC and the logic synchronization circuit are adopted to improve the time resolution of the TDC together, so that the number of digital circuits is small, the area is greatly saved, and the time resolution of the TDC is improved.
Furthermore, the present invention also proposes a time-to-digital converter apparatus comprising a time-to-digital converter device as described above, or a control method applying the time-to-digital converter device as described above. It will be readily appreciated that the time-to-digital converter apparatus has at least the benefits associated with the above-described embodiments.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and all modifications and equivalents of the present invention, which are made by the contents of the present specification and the accompanying drawings, or directly/indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (10)
1. a time-to-digital converter circuit is characterized in that the time-to-digital converter circuit comprises a logic synchronization circuit, a time-to-digital converter and a time amplitude converter module, wherein a first output end of the logic synchronization circuit is connected with the time-to-digital converter, and a second output end of the logic synchronization circuit is connected with an input end of the time amplitude converter module;
The logic synchronization circuit is used for receiving a clock signal, a starting signal and a stopping signal, separating the starting signal and the stopping signal and outputting a counting clock signal, a time amplitude conversion starting signal and a time amplitude conversion stopping signal;
the time-to-digital converter is used for receiving the counting clock signal and counting according to the counting clock signal;
The time-amplitude converter module is configured to receive a reference current, the time-amplitude conversion start signal, and the time-amplitude conversion end signal, and perform timing according to the reference current, the time-amplitude conversion start signal, and the time-amplitude conversion end signal.
2. The time-to-digital converter circuit of claim 1, wherein the time-to-amplitude converter module comprises a signal generation circuit and a time-to-amplitude converter;
The second output end of the logic synchronization circuit is connected with the input end of the signal generation circuit, and the output end of the signal generation circuit is connected with the input end of the time-amplitude converter;
The signal generating circuit is used for receiving the time-amplitude conversion starting signal and the time-amplitude conversion stopping signal and outputting a fine counting enable signal and a reset signal;
The time-amplitude converter is configured to receive a reference current, the fine count enable signal, and the reset signal, and perform timing according to the reference current and reset according to the reset signal when the fine count enable signal is low.
3. the time-to-digital converter circuit of claim 2, wherein the time-to-amplitude converter comprises: a MOS transistor circuit module and a capacitor;
The output end of the signal generating circuit is connected with the first end of the MOS tube circuit module, and the second end of the MOS tube circuit module is connected with the capacitor;
The MOS tube circuit module is used for receiving a reference current and the fine counting enable signal, controlling whether to charge the capacitor or not through the fine counting enable signal and controlling whether to reset the capacitor or not according to the reset signal;
and the capacitor is used for timing according to the reference current and resetting according to the reset signal.
4. The time-to-digital converter circuit of any of claims 1-3, wherein the time-to-digital converter comprises a counter.
5. the time-to-digital converter circuit of claim 4, wherein the logic synchronization circuit comprises a flip-flop module, an OR gate, and an AND gate module;
The first end of the trigger module is used for receiving a clock signal, a start signal and a termination signal;
the second end of the trigger module is connected with the first end of the AND gate module, and the second end of the trigger module is also connected with the OR gate;
And the second end of the AND gate module is connected with the first end of the counter, and the second end of the counter is connected with the time-amplitude converter module.
6. the time-to-digital converter circuit of claim 5, wherein the flip-flop module comprises a first flip-flop, a second flip-flop, and a third flip-flop; the AND gate module comprises a first AND gate and a second AND gate;
the input end of the first trigger receives a start signal, the first output end of the first trigger is connected with the input end of the second trigger, the output end of the second trigger is connected with the first input end of the first AND gate, the output end of the first AND gate is connected with the input end of the second AND gate, the output end of the second AND gate is connected with the first end of the counter, the input end of the third trigger receives a termination signal, the output end of the third trigger is connected with the second input end of the first AND gate, the second output end of the first trigger is connected with the first input end of the OR gate, and the output end of the second trigger is further connected with the second input end of the OR gate.
7. A time-to-digital converter arrangement, characterized in that the time-to-digital converter arrangement comprises a time-to-digital converter circuit according to any of claims 1-6.
8. A method for controlling a time-to-digital converter apparatus, applied to the time-to-digital converter apparatus as claimed in claim 7, wherein the method is based on a time-to-digital converter circuit, the time-to-digital converter circuit comprising a logic synchronization circuit, a time-to-digital converter and a time-to-amplitude converter module, the method for controlling the time-to-digital converter apparatus comprising the steps of:
The logic synchronization circuit receives a clock signal, a start signal and a stop signal, separates the start signal from the stop signal and outputs a counting clock signal, a time amplitude conversion start signal and a time amplitude conversion stop signal;
The time-to-digital converter receives the counting clock signal and counts according to the counting clock signal;
the time-amplitude converter module receives a reference current, the time-amplitude conversion starting signal and the time-amplitude conversion ending signal, and performs timing according to the reference current, the time-amplitude conversion starting signal and the time-amplitude conversion ending signal.
9. the method of controlling a time-to-digital converter apparatus of claim 8, wherein the time-to-amplitude converter module comprises a signal generating circuit and a time-to-amplitude converter; the time-amplitude converter module receives a reference current, the time-amplitude conversion start signal and the time-amplitude conversion end signal, and performs timing according to the reference current, the time-amplitude conversion start signal and the time-amplitude conversion end signal, and specifically includes:
the signal generating circuit receives the time-amplitude conversion starting signal and the time-amplitude conversion stopping signal and outputs a fine count enabling signal and a reset signal;
The time-amplitude converter receives a reference current, the fine count enable signal, and the reset signal, performs timing based on the reference current when the fine count enable signal is low, and performs reset based on the reset signal.
10. a time-to-digital converter apparatus, characterized in that it comprises a time-to-digital converter device according to claim 7, or in that it applies a control method of a time-to-digital converter device according to any one of claims 8 to 9.
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