CN110556335A - 采用选择性金属沉积的完全对准的通孔 - Google Patents
采用选择性金属沉积的完全对准的通孔 Download PDFInfo
- Publication number
- CN110556335A CN110556335A CN201910439085.6A CN201910439085A CN110556335A CN 110556335 A CN110556335 A CN 110556335A CN 201910439085 A CN201910439085 A CN 201910439085A CN 110556335 A CN110556335 A CN 110556335A
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- Prior art keywords
- metal
- layer
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- dielectric layer
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- 238000001465 metallisation Methods 0.000 title claims abstract description 22
- 229910052751 metal Inorganic materials 0.000 claims abstract description 152
- 239000002184 metal Substances 0.000 claims abstract description 152
- 238000000034 method Methods 0.000 claims abstract description 59
- 238000000206 photolithography Methods 0.000 claims abstract description 16
- 239000010410 layer Substances 0.000 claims description 168
- 239000004065 semiconductor Substances 0.000 claims description 58
- 239000006117 anti-reflective coating Substances 0.000 claims description 34
- 239000000463 material Substances 0.000 claims description 34
- 150000004767 nitrides Chemical class 0.000 claims description 28
- 229920002120 photoresistant polymer Polymers 0.000 claims description 22
- 239000004020 conductor Substances 0.000 claims description 15
- 239000011229 interlayer Substances 0.000 claims description 14
- 238000000151 deposition Methods 0.000 claims description 10
- 238000001459 lithography Methods 0.000 claims 1
- 230000008569 process Effects 0.000 description 18
- 239000010949 copper Substances 0.000 description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 12
- 230000004888 barrier function Effects 0.000 description 11
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 10
- 238000005229 chemical vapour deposition Methods 0.000 description 10
- 229910052802 copper Inorganic materials 0.000 description 10
- 238000005530 etching Methods 0.000 description 9
- 229910052581 Si3N4 Inorganic materials 0.000 description 8
- 150000001875 compounds Chemical class 0.000 description 8
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 8
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 8
- 239000003989 dielectric material Substances 0.000 description 7
- 238000005240 physical vapour deposition Methods 0.000 description 7
- 229910052710 silicon Inorganic materials 0.000 description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 6
- 229910052799 carbon Inorganic materials 0.000 description 6
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 6
- 239000000047 product Substances 0.000 description 6
- 239000010703 silicon Substances 0.000 description 6
- 235000012239 silicon dioxide Nutrition 0.000 description 6
- 239000000377 silicon dioxide Substances 0.000 description 6
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 6
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 5
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 5
- 230000003667 anti-reflective effect Effects 0.000 description 5
- 230000000903 blocking effect Effects 0.000 description 5
- 238000013461 design Methods 0.000 description 5
- 239000010936 titanium Substances 0.000 description 5
- 229910052782 aluminium Inorganic materials 0.000 description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 4
- 239000007795 chemical reaction product Substances 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 230000000737 periodic effect Effects 0.000 description 4
- 238000005498 polishing Methods 0.000 description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 4
- 239000000126 substance Substances 0.000 description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 229910017052 cobalt Inorganic materials 0.000 description 3
- 239000010941 cobalt Substances 0.000 description 3
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 230000009977 dual effect Effects 0.000 description 3
- 229910052697 platinum Inorganic materials 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 229910052715 tantalum Inorganic materials 0.000 description 3
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 3
- 229910052721 tungsten Inorganic materials 0.000 description 3
- 239000010937 tungsten Substances 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 238000005137 deposition process Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000005566 electron beam evaporation Methods 0.000 description 2
- 238000009713 electroplating Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000000227 grinding Methods 0.000 description 2
- 239000013067 intermediate product Substances 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 239000011295 pitch Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 238000002207 thermal evaporation Methods 0.000 description 2
- 235000001674 Agaricus brunnescens Nutrition 0.000 description 1
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- FYYHWMGAXLPEAU-UHFFFAOYSA-N Magnesium Chemical compound [Mg] FYYHWMGAXLPEAU-UHFFFAOYSA-N 0.000 description 1
- PWHULOQIROXLJO-UHFFFAOYSA-N Manganese Chemical compound [Mn] PWHULOQIROXLJO-UHFFFAOYSA-N 0.000 description 1
- BPQQTUXANYXVAA-UHFFFAOYSA-N Orthosilicate Chemical compound [O-][Si]([O-])([O-])[O-] BPQQTUXANYXVAA-UHFFFAOYSA-N 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 description 1
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 1
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 description 1
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 1
- HMDDXIMCDZRSNE-UHFFFAOYSA-N [C].[Si] Chemical compound [C].[Si] HMDDXIMCDZRSNE-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 239000011651 chromium Substances 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(iv) oxide Chemical compound O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 1
- 230000005865 ionizing radiation Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 239000011777 magnesium Substances 0.000 description 1
- 229910052748 manganese Inorganic materials 0.000 description 1
- 239000011572 manganese Substances 0.000 description 1
- WPBNNNQJVZRUHP-UHFFFAOYSA-L manganese(2+);methyl n-[[2-(methoxycarbonylcarbamothioylamino)phenyl]carbamothioyl]carbamate;n-[2-(sulfidocarbothioylamino)ethyl]carbamodithioate Chemical compound [Mn+2].[S-]C(=S)NCCNC([S-])=S.COC(=O)NC(=S)NC1=CC=CC=C1NC(=S)NC(=O)OC WPBNNNQJVZRUHP-UHFFFAOYSA-L 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 230000005012 migration Effects 0.000 description 1
- 238000013508 migration Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 1
- BPUBBGLMJRNUCC-UHFFFAOYSA-N oxygen(2-);tantalum(5+) Chemical compound [O-2].[O-2].[O-2].[O-2].[O-2].[Ta+5].[Ta+5] BPUBBGLMJRNUCC-UHFFFAOYSA-N 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 229920006254 polymer film Polymers 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 238000005389 semiconductor device fabrication Methods 0.000 description 1
- 150000004760 silicates Chemical class 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical class [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- -1 siloxanes Chemical class 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000003860 storage Methods 0.000 description 1
- 229910052712 strontium Inorganic materials 0.000 description 1
- CIOAGBVUUVVLOB-UHFFFAOYSA-N strontium atom Chemical compound [Sr] CIOAGBVUUVVLOB-UHFFFAOYSA-N 0.000 description 1
- 229910001936 tantalum oxide Inorganic materials 0.000 description 1
- 230000036962 time dependent Effects 0.000 description 1
- 229910052718 tin Inorganic materials 0.000 description 1
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 description 1
- 238000012876 topography Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- 229910052720 vanadium Inorganic materials 0.000 description 1
- GPPXJZIENCGNKB-UHFFFAOYSA-N vanadium Chemical compound [V]#[V] GPPXJZIENCGNKB-UHFFFAOYSA-N 0.000 description 1
- 229910052725 zinc Inorganic materials 0.000 description 1
- 239000011701 zinc Substances 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76808—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving intermediate temporary filling with material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
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- H01L21/76844—Bottomless liners
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
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- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
- H01L21/0274—Photolithographic processes
- H01L21/0276—Photolithographic processes using an anti-reflective coating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31144—Etching the insulating layers by chemical or physical means using masks
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Abstract
本发明提出了通过采用选择性金属沉积来创建完全对准的通孔(FAV)。所述方法包含在第一层间电介质(ILD)层内形成金属线,在第一ILD层之上形成第二ILD层,在第二ILD层之上形成光刻堆叠体以限定防止通孔生长的区域,使光刻堆叠体凹陷以暴露金属线的由光刻堆叠体允许通孔生长的顶表面,以及在金属线的允许通孔生长的暴露的顶表面之上进行金属生长。
Description
技术领域
本发明总体上涉及半导体装置,并且更具体而言,涉及通过采用选择性金属沉积来形成完全对准的通孔。
背景技术
相关技术的描述
随着工艺尺寸持续缩小,半导体装置的光刻蚀刻图案化通常需要印刷64纳米(nm)或者更小节距的金属层(Mx级别)。然而,不良的覆盖可是成功的图案化应用中考虑的重要因素。例如,在没有自对准的通孔(SAV)工艺的情况下,铜线和通孔之间的介电空间可能变小,这可能引起可靠性问题。此外,当前的SAV工艺通常仅在一个方向上自对准。由于通孔底部与其下方的不相关的金属接近,可形成时间依赖的介电击穿的可靠性失效机制的弱点。沿着其界面可能发生击穿以导致泄漏增加或完全短路,因此影响产品的功能性。
发明内容
根据实施例,提供一种通过采用选择性金属沉积来创建完全对准的通孔(FAV)的方法。该方法包含:在第一层间电介质(ILD)层内形成金属线,在第一ILD层之上形成第二ILD层,在第二ILD层之上形成光刻堆叠体以限定防止通孔生长的区域,使光刻堆叠体凹陷以暴露金属线的由光刻堆叠体允许通孔生长的顶表面,以及在金属线的允许通孔生长的暴露的顶表面之上进行金属生长。
根据实施例,提供一种通过采用选择性金属沉积来创建完全对准的通孔(FAV)的方法。该方法包含:在第一层间电介质(ILD)层内形成金属线,在金属线上形成绝缘蚀刻停止层,在绝缘蚀刻停止层之上形成第二ILD层,在第二ILD层之上形成光刻堆叠体以限定防止通孔生长的区域,使光刻堆叠体凹陷以暴露金属线的由光刻堆叠体允许通孔生长的顶表面,在金属线的允许通孔生长的暴露的顶表面之上进行金属生长,以及在金属生长之上沉积共形金属氮化物盖,使得在金属生长和第二ILD层之间形成气隙。
根据另一个实施例,提供一种通过采用选择性金属沉积来创建完全对准的通孔(FAV)的半导体装置。半导体装置包含金属线、第二ILD层、金属生长和共形金属氮化物盖,该金属线设置在第一层间电介质(ILD)层内;该第二ILD层设置在第一ILD层之上;该金属生长设置在允许通孔生长的暴露的金属线之上;并且该共形金属氮化物盖设置在金属生长之上,使得在金属生长和第二ILD层之间形成气隙。
应该注意的是,参考不同主题来描述示例性实施例。特别地,一些实施例参考方法类型的权利要求来描述,而其他实施例参考设备类型的权利要求来描述。然而,本领域技术人员将从上述或以下的描述中获悉的是,除非另外指出,除了属于主题的一个类型的特征的任何组合以外,在与不同主题相关的特征之间(特别是在方法类型的权利要求的特征和设备类型的权利要求的特征之间)的任何组合被认为在该文档内描述。
从以下对其说明性实施例的详细描述中,这些和其他特征和优点将变得显而易见,这将结合附图来理解。
附图说明
本发明将参考如下附图在以下的优选的实施例的描述中提供细节,其中:
图1是根据本发明的实施例的包含至少多个金属线的半导体结构的横截面图;
图2是根据本发明的实施例的、图1中发生凹陷以暴露绝缘蚀刻停止层的顶表面的半导体结构的横截面图;
图3是根据本发明的实施例的、图2中沉积有机平坦化层(OPL)、抗反射涂层(ARC)层和光刻胶的半导体结构的横截面图;
图4是根据本发明的实施例的、图3中移除光刻胶、蚀刻OPL和ARC层以暴露多个金属线中的一个或多个的顶表面的半导体结构的横截面图;
图5是根据本发明的实施例的、图4中在暴露的金属线之上形成自对准的通孔互连结构的半导体结构的横截面图;
图6是根据本发明的实施例的、图5中移除剩余的OPL和ARC层以暴露绝缘蚀刻停止层的顶表面的半导体结构的横截面图;
图7是根据本发明的实施例的、图6中沉积共形金属氮化物层的半导体结构的横截面图;
图8是根据本发明的实施例的、图7中沉积低k材料的半导体结构的横截面图;
图9是根据本发明的实施例的、图8中低k材料被凹陷以在自对准的通孔互连结构之上暴露共形金属氮化物层的半导体结构的横截面图;
图10是根据本发明的实施例的、图9中暴露的共形金属氮化物层被移除以暴露自对准的通孔互连结构的顶表面的半导体结构的横截面图;
图11是根据本发明的实施例的、图10中发生金属填充的半导体结构的横截面图;
图12是根据本发明的实施例的、图11中平坦化金属填充的半导体结构的横截面图;
图13是根据本发明的另一个实施例的、包含至少多个金属线的半导体结构的横截面图;
图14是根据本发明的实施例的、图13中发生凹陷以暴露第二层间电介质(ILD)的顶表面的半导体结构的横截面图;
图15是根据本发明的实施例的、图14中沉积有机平坦化层(OPL)、抗反射涂层(ARC)层和光刻胶的半导体结构的横截面图;
图16根据本发明的另一个实施例的、图15中移除光刻胶、蚀刻OPL和ARC层以暴露金属线的顶表面的半导体结构的横截面图;
图17是根据本发明的实施例的、图16中在暴露的金属线之上形成自对准的通孔互连结构的半导体结构的横截面图;
图18是根据本发明的实施例的、图17中沉积共形金属氮化物层的半导体结构的横截面图;
图19是根据本发明的实施例的、图18中暴露的共形金属氮化物层被移除以暴露自对准的通孔互连结构的顶表面的半导体结构的横截面图;
图20是根据本发明的实施例的、图19中发生金属填充而金属填充被平坦化的半导体结构的横截面图。
在所有附图中,相同或相似的附图标记表示相同或相似的元件。
具体实施方式
根据本发明的实施例提供了在半导体装置中为低电容布线构造完全对准的通孔(FAV)的方法和装置。由选择性金属沉积技术来形成FAV。在研发阶段中的7nm技术节点和进入研发的5nm节点的情况下,晶体管的缩放比例正变得愈加复杂。重要的是,如果没有在后端制程(BEOL)中做出相似的改进,则前段制程(例如晶体管)增加的性能效益可能很容易地被撤销。BEOL工艺涉及创建与芯片中的晶体管电互连的金属线的堆叠层。在每个技术节点的情况下,该金属布线方案变得越来越复杂,主要因为存在更多晶体管以与愈加紧凑的节距连接。缩小的尺寸还意味着布线具有减小的横截面面积,这提高了互连系统的电阻-电容乘积(RC)。
基于金属的双镶嵌已经是互连的主要工艺流程。金属可以是例如铜(Cu)。简单的双镶嵌流程起始于在结构上沉积低k介电材料。这些低k的薄膜设计为在集成电路(IC)中降低电容和延迟。下一步骤中,该介电层覆盖有氧化物和抗蚀剂,并且使用光刻和蚀刻步骤来形成通孔和沟槽。这些通孔将一个金属层与上方的或下方的层连接。然后,金属阻挡层被加入以防止金属原子迁移到低k材料中。使用诸如钽和钽氮化物,以例如物理气相沉积(PVD)来沉积阻挡层。在最终步骤中,将该结构接种、用金属(通常铜)电镀,随后进行化学机械平坦化(CMP)步骤。
本发明总体上涉及半导体装置制造,更特别地涉及制造金属线互连(通孔),其与Mx层级和Mx+1层级二者完全对准。根据本发明的实施例提供采用选择性金属沉积以构建与Mx和Mx+1沟槽图案的交叉处自对准的通孔的方法和装置。在一个实施例中,方法需要进行Mx+1沟槽的第一电介质蚀刻以揭露下面的Mx结构,然后在阻挡没有形成通孔的交叉处之后,进行金属通孔的选择性沉积以构建金属突起物、沉积间隙填充介电材料并且使其凹陷以围绕并包封生长的通孔“柱状物”、打开或移除任何剩余的硬掩模或覆盖材料、以及进行单镶嵌金属化以在Mx+1沟槽的剩余的部分中形成Mx+1线。
在形成这样的结构中可以采用的半导体材料的示例包含硅(Si)、锗(Ge)、硅锗合金(SiGe)、碳化硅(SiC)、碳化硅锗(SiGeC)、III-V族化合物半导体和/或II-VI族化合物半导体。III-V族化合物半导体是包含来自元素周期表III族的至少一个元素和来自元素周期表V族的至少一个元素的材料。II-VI族化合物半导体是包含来自元素周期表II族的至少一个元素和来自元素周期表VI族的至少一个元素的材料。
理解的是,将在给定的说明性架构方面描述本发明,然而其他架构、结构、基板材料和工艺特征以及步骤/块可以在本发明的范围内变化。需要注意的是,为了简洁起见,不能在所有附图中示出某些特征。这不旨在于解释为对任何特定的实施例、或图示、或者权利要求的范围进行限制。
图1是根据本发明的实施例的、包含至少多个金属线的半导体结构的横截面图。
半导体结构5包含第一层间电介质(ILD)10内形成的多个金属线12。绝缘蚀刻停止层14可以形成在金属线12之上。阻挡层16可以形成在绝缘蚀刻停止层14之上。第二ILD18可以形成在阻挡层16之上。然后,第一牺牲层20和第二牺牲层22可以形成在第二ILD 18之上。有机平坦化层(OPL)24然后可以形成在第一和第二牺牲层20、22之上。附加地,抗反射涂层(ARC)层26和光刻胶层28可以形成在OPL 24的部分之上。
第一ILD 10可以包含本领域已知的任何材料,诸如多孔硅酸盐、碳掺杂氧化物、二氧化硅、硅氮化物、硅氮氧化物或其他介电材料。可以使用本领域已知的任何方法(诸如化学气相沉积、等离子体增强化学气相沉积、原子层沉积或物理气相沉积)来形成第一ILD10。第一ILD 10的厚度的范围可以为从约25nm至约200nm。
介电层10可以包含但不限于超低k(ULK)材料,诸如多孔硅酸盐、碳掺杂氧化物、二氧化硅、硅氮化物、硅氮氧化物、碳掺杂的硅氧化物(SiCOH)及其多孔变体、倍半硅氧烷、硅氧烷、或者具有例如在约2至约4的范围中的介电常数的其它介电材料。
金属线12(与Mx层相关联)可以形成在第一ILD 10中所形成的金属开口或沟槽中。金属线12可以是本领域已知的任何导电材料,诸如铜(Cu)、铝(A1)或钨(W)。金属线12可以使用本领域已知的任何技术(诸如单镶嵌或双镶嵌技术)来制造。在未示出的实施例中,金属线12可以是铜(Cu)并且可以包含金属衬垫,其中该金属衬垫可以是诸如钽氮化物和钽(TaN/Ta)、钛、钛氮化物、钴、钌和锰的金属。
阻挡层16可以是电介质盖。电介质盖的介电材料可以是氮化硅(SiN)、二氧化硅(SiO2)、二氧化铪(HfO2)等。在另一个示例实施例中,电介质盖16可以包含诸如氮化硅(Si3N4)、碳化硅(SiC)或硅碳(Si、C)的材料。
绝缘蚀刻停止层14可以例如是氮化铝(AlN)层。绝缘蚀刻停止层14的其他材料可以包含,但不必限于,氮化钛(TiN)、氮化钽(TaN)、铝氧化物、钛氧化物、钽氧化物和TaN/Ta的双层,其(像是TaN)根据本文所描述的实施例可以被选择性或非选择性地移除。
第一牺牲层20可以是氮化钛(TiN)层,并且第二牺牲层22可以是例如氮化硅(SiN)层的氮化物层。
OPL层24和ARC层26可以用作光刻堆叠体以图案化下面的层。OPL层24以预定的厚度来形成,以在下方的硬掩膜层的蚀刻期间提供反射和形貌控制。OPL层24可以包含诸如聚合物的有机材料。OPL 24的厚度可以在从约50nm到约300nm的范围中。
层26是三层光刻堆叠体的光刻期间使光反射最小化的ARC层。ARC层26可以包含硅,例如硅抗反射层(SiARC)。ARC层26的厚度可以在从约10nm到约100nm的范围中。抗反射薄膜层20可以是在光刻期间抑制非期望的光反射的抗反射层。抗反射层的示例材料包含但不限于金属硅氮化物或聚合物薄膜。根据材料,例如使用溅射沉积、化学气相沉积或旋涂,可以形成抗反射层。
光刻工艺通常包含施加光刻胶材料28(例如在暴露于光时将会反应的材料)的层,并且然后将光刻胶28的部分选择性地暴露于光或其他离子化辐射(例如紫外、电子束、X射线等),由此改变部分材料的溶解度。然后通过用诸如四甲基氢氧化铵(TMAH)的显影剂溶液清洗抗蚀剂来显影抗蚀剂28,由此移除抗蚀剂层中的未被辐射的部分(负性抗蚀剂中)或辐射的部分(正性抗蚀剂中)。
图2是根据本发明的实施例的、图1中发生凹陷以暴露绝缘蚀刻停止层的顶表面的半导体结构的横截面图.
在各种示例实施例中,OPL 24、第二牺牲层22、第一牺牲层20和第二ILD 18被蚀刻为形成开口或沟槽30,以暴露阻挡层16的顶表面17。还暴露了第二ILD 18的侧壁19。
图3是根据本发明的实施例的、图2中沉积有机平坦化层(OPL)、抗反射涂层(ARC)层和光刻胶的半导体结构的横截面图。
在各种示例实施例中,第二OPL 32沉积在开口或沟槽30内,并且与阻挡层16的顶表面17直接接触。第二ARC层34沉积在第二OPL 32之上。附加地,第二光刻胶36沉积在第二ARC 34之上。第二抗蚀剂36限定了通孔生长被阻挡或阻止的区域。换言之,第二光刻胶36限定了防止自对准的通孔互连结构形成的区域。
图4是根据本发明的实施例的、图3中移除光刻胶、蚀刻OPL和ARC层以暴露多个金属线中的一个或多个的顶表面的半导体结构的横截面图。
在各种示例实施例中,第二光刻胶36被移除,并且发生蚀刻以暴露一个或多个金属线12的顶表面13(在该处要形成通孔)。蚀刻导致在暴露的金属线12之上形成的开口或沟槽38。附加地,第二牺牲层22的顶表面23被暴露。剩余的第二OPL 32’和剩余的第二ARC层34’形成在一个或多个未暴露的金属线12之上。剩余的第二OPL 32’和剩余的第二ARC层34’可以被称为阻挡岛(或Vx图案)。阻挡岛防止通孔形成。然而,将未被Vx图案或阻挡岛阻挡的某些金属线(Mx)打开。打开的金属线将容纳要形成的通孔。
移除是将材料从晶片移除的任何工艺:例如包含蚀刻工艺(湿式或干式)、和化学机械平坦化(CMP)等。
图5是根据本发明的实施例的、图4中在暴露的金属线之上形成自对准的通孔互连结构的半导体结构的横截面图.
在各种示例实施例中,自对准的通孔互连结构40形成在暴露的金属线12之上。这可以被称为至期望的通孔高度的选择性金属生长,其中蘑菇状或横向生长发生并且可以用块CD来控制。
自对准的通孔互连结构40可以用于防止电迁移,例如由于导电电子和扩散的金属原子之间的动量转移而使导体中的离子的逐渐移动所引起的材料的传输。事实上,自对准的通孔互连结构40可以防止通孔互连结构和布线结构的两种类型的失效模式:(i)通孔损耗和(ii)线路损耗。通孔损耗发生在电子从下方的布线线路流动到上方的通孔互连结构中时。另一方面,线路损耗发生在电子从通孔互连结构向下流动到下方的布线线路时。
图6是根据本发明的实施例的、图5中移除剩余的OPL和ARC层以阻挡层的顶表面的半导体结构的横截面图。
在各种示例实施例中,剩余的OPL 32’和剩余的ARC层34’被移除,以暴露阻挡层16的顶表面17。剩余的OPL 32’和剩余的ARC层34’可以由例如湿法蚀刻技术来移除。
图7是根据本发明的实施例的、图6中沉积共形金属氮化物层的半导体结构的横截面图。
在各种示例实施例中,沉积共形金属氮化物层42,使得在第二ILD 18和自对准的通孔互连结构或金属生长40之间形成沟槽49。共形金属氮化物层42保护通孔金属。
图8是根据本发明的实施例的、图7中沉积低k材料的半导体结构的横截面图。
在各种示例实施例中,低k材料层44沉积在共形金属氮化物层42之上。
作为在低k介电层44中所使用的低k介电材料可以具有小于4.0(例如3.9)的介电常数。在一个实施例中,低k材料层44具有的介电常数的范围可以为从约1.0到约3.5。在另一个实施例中,低k材料层44具有的介电常数的范围可以为从约1.75到约3.2。
适合于低k介电层44的低k材料的材料的一个示例可以包含硅氮碳氧化物(SiOCN)。还可以用于低k介电层44的其他低k材料可以包含氟掺杂的二氧化硅、碳掺杂的二氧化硅、多孔二氧化硅、多孔碳掺杂的二氧化硅、有机硅酸盐玻璃(OSG)、类金刚石碳(DLC)及其组合。
在一些实施例中,可以使用化学气相沉积(CVD)共形地沉积低k介电层44。还可以采用适合于形成第一介电层的CVD工艺的变型,其包含但不限于,大气压强CVD(APCVD)、低压CVD(LPCVD)和等离子体增强的CVD(PECVD)、金属有机物CVD(MOCVD)及其组合。在一些实施例中,低k介电层44具有的厚度的范围可以为从约5nm到约30nm。在另一个实施例中,低k介电层44具有的厚度的范围可以为从约7nm到约15nm。
图9是根据本发明的实施例的、图8中低k介电层被凹陷以在自对准的通孔互连结构之上暴露共形金属氮化物层的半导体结构的横截面图。
在各种示例实施例中,低k介电层44被凹陷以创建开口45,使得低k介电部分44’保留在第二ILD 18和自对准的通孔互连结构40之间形成的沟槽49中。附加地,低k介电部分44’保留在阻挡层16和自对准的通孔互连结构40之间。凹陷可以在共形金属氮化物层42的顶表面42下方延伸“X1”的距离。
图10是根据本发明的实施例的、图9中暴露的共形金属氮化物层被移除以暴露自对准的通孔互连结构的顶表面的半导体结构的横截面图。
在各种示例实施例中,将共形金属氮化物层42从第二ILD 18的侧壁19移除,并且还从自对准的通孔互连结构40的顶表面移除。因此,现在暴露了自对准的通孔互连结构40的顶表面41。另外,暴露了第二ILD 18的顶表面47,因为第一和第二牺牲层20、22的剩余部分或区段被移除。共形金属氮化物层42可以例如由反应离子蚀刻(RIE)技术来移除。
图11是根据本发明的实施例的、图10中发生金属填充的半导体结构的横截面图。
在各种示例实施例中,可以沉积导电材料46。金属化可以是单镶嵌金属化。因此,对于沟槽,只需要单镶嵌金属化,这样使对图案或轮廓需求敏感的动态回流或其他填充技术成为可能。导电材料46例如可以是金属或掺杂的多晶硅(poly-Si)。金属的非限制性示例包含铜(Cu)、钴(Co)、铝(Al)、铂(Pt)、金(Au)、钨(W)、钛(Ti)或其任意组合。金属可以由如下适当的沉积工艺来沉积:例如化学气相沉积(CVD)、等离子体增强的化学气相沉积(PECVD)、物理气相沉积(PVD)、电镀、热或电子束蒸发、或者溅射。
如贯穿本申请所使用的,术语“铜”旨在于包含实质上纯元素的铜、含有不可避免的掺杂物(包括原生氧化物)的铜和含有一个或多个附加的元素(诸如碳、氮、镁、铝、钛、钒、铬、锰、镍、锌、锗、锶、锆、银、铟、锡、钽和铂)的铜合金。在实施例中,铜合金是铜锰合金。在其它实施例中,可以采用钴金属(Co)或钴金属合金来替代铜。含有铜的结构是导电的。本公开全文中所使用的“导电”是指具有至少为10-8(Ω-m)-1的室温电导率的材料。
图12是根据本发明的实施例的、图11中金属填充被平坦化的半导体结构的横截面图。
在各种示例实施例中,可以平坦化导电材料46,使得导电材料46’保留。剩余的导电材料46’可以与第二ILD 18的顶表面47齐平。在各种示例性实施例中,可以由化学机械抛光(CMP)和/或蚀刻来降低导电材料46的高度。因此,可以由CMP来提供平坦化工艺。其他平坦化工艺可以包含磨削和抛光。
图13是根据本发明的另一个实施例的、包括至少多个金属线的半导体结构的横截面图。
半导体结构5包含第一层间电介质(ILD)10内形成的多个金属线12。绝缘蚀刻停止层14可以形成在金属线12之上。阻挡层16可以形成在绝缘蚀刻停止层14之上。第二ILD 18可以形成在阻挡层16之上。然后,第一牺牲层20和第二牺牲层22可以形成在第二ILD 18之上。有机平坦化层(OPL)24然后可以形成在第一和第二牺牲层20、22之上。附加地,抗反射涂层(ARC)层26和光刻胶层28可以形成在OPL 24的部分之上。
图14是根据本发明的实施例的、图13中发生凹陷以暴露第二层间电介质(ILD)的顶表面的半导体结构的横截面图。
在各种示例实施例中,OPL 24、第二牺牲层22、第一牺牲层20和第二ILD 18被蚀刻为形成开口或沟槽50,以暴露剩余的第二ILD 18’的顶表面51。因此,第二ILD 18’保留为与阻挡层16直接接触。
图15是根据本发明的实施例的、图14中沉积有机平坦化层(OPL)、抗反射涂层(ARC)层和光刻胶的半导体结构的横截面图。
在各种示例实施例中,第二OPL 52沉积在开口或沟槽50内,并且与剩余的第二ILD18’的顶表面直接接触。第二ARC层54沉积在第二OPL 52之上。附加地,第二光刻胶56沉积在第二ARC 54之上。光刻胶56设计为使得将用其他工艺暴露仅一个金属线12。
图16是根据本发明的另一个实施例的、图15中移除光刻胶、蚀刻OPL和ARC层以暴露金属线的顶表面的半导体结构的横截面图。
在各种示例实施例中,发生蚀刻以暴露一个金属线12的顶表面13。蚀刻导致在暴露的金属线12之上形成开口或沟槽58。剩余的第二OPL 52’、剩余的第二ARC层54’和剩余的光刻胶56’形成在一个或多个未暴露的金属线12之上。
图17是根据本发明的实施例的、图16中在暴露的金属线之上形成自对准的通孔互连结构的半导体结构的横截面图。
在各种示例实施例中,剩余的OPL 52’、剩余的ARC层54’和剩余的光刻胶56’被移除,以创建间隙62并且暴露剩余的第二ILD 18’的顶表面51。剩余的OPL 52’和剩余的ARC层54’和剩余的光刻胶56’可以由例如湿法蚀刻技术来移除。此外,在各种示例实施例中,自对准的通孔互连结构或金属生长60形成在暴露的金属线12之上。
图18是根据本发明的实施例的、图17中沉积共形金属氮化物层的半导体结构的横截面图。
在各种示例实施例中,沉积共形金属氮化物层64,使得在剩余的第二ILD18’和自对准的通孔互连结构60之间形成气隙66。
图19是根据本发明的实施例的、图18中暴露的共形金属氮化物被移除以暴露自对准的通孔互连结构的顶表面的半导体结构的横截面图。
在各种示例实施例中,共形金属氮化物层64的部分被移除,以暴露剩余的第二ILD18’的顶表面51并且暴露自对准的通孔互连结构60的顶表面41。气隙66在剩余的第二ILD18’和自对准的通孔互连结构60之间保持完整。
图20是根据本发明的实施例的、图19中发生金属填充而金属填充被平坦化的半导体结构的横截面图。
在各种示例实施例中,可以沉积导电材料68。导电材料68例如可以是金属或掺杂的多晶硅(poly-Si)。金属的非限制性示例包含铜(Cu)、钴(Co)、铝(A1)、铂(Pt)、金(Au)、钨(W)、钛(Ti)或其任意组合。金属可以由如下适当的沉积工艺来沉积:例如化学气相沉积(CVD)、等离子体增强的化学气相沉积(PECVD)、物理气相沉积(PVD)、电镀、热或电子束蒸发、或者溅射。
在各种示例实施例中,可以平坦化导电材料68。剩余的导电材料68可以与剩余的第二ILD18’的顶表面67齐平。在各种示例性实施例中,可以由化学机械抛光(CMP)和/或蚀刻来降低导电材料68的高度。因此,可以由CMP来提供平坦化工艺。其他平坦化工艺可以包含磨削和抛光。
总之,本发明的示例性实施例采用选择性金属沉积以“构建”与Mx和Mx+1沟槽图案的交叉处自对准的通孔,以缓和沟槽和通孔光刻变化或者覆盖的任何影响。在一个实施例中,进行Mx+1沟槽第一电介质蚀刻以揭露下面的Mx结构,然后在阻挡其中没有形成通孔的交叉处之后,进行金属通孔的选择性沉积以构建金属突起物。然后该方法沉积间隙填充介电材料并且使其凹陷,以围绕并且包封生长的通孔“柱状物”。在打开或移除任何剩余的硬掩膜或覆盖材料之后,可以进行单镶嵌金属化和CMP。
可以将本文中所公开的互连结构并入到任何电气装置中。例如,互连结构可以存在于电气装置内,其使用在集成电路芯片内存在的半导体。包含所公开的互连件的集成电路芯片可以与其他芯片、离散电路元件和/或其他信号处理装置集成,以作为(a)诸如母板的中间产品或是(b)终端产品的部件。终端产品可以是包含集成电路芯片的任何产品,包含了具有显示器、键盘或其他输入装置以及中央处理单元的计算机产品或装置。
将理解的是,还将在给定说明性架构的方面描述本发明,然而其他架构、结构、基板材料和工艺特征以及步骤/块可以在本发明的范围内变化。
还将理解的是,当诸如层、区域或基板的元件被称为在另一个元件“上”或“之上”时,它可以直接在其他元件上或者还可以存在中间元件。相比之下,当元件被称为“直接在”另一个元件“上”或“之上”时,没有中间元件存在。还将理解的是,当元件被称为“连接”或“耦接”至另一个元件时,它可以直接地连接或耦接至其他元件或者可以存在中间元件。相比之下,当元件被称为“直接连接”或“直接耦接”至另一个元件时,没有中间元件存在。
出现的实施例可以包含集成电路芯片的设计,其可以在图形计算机编程语言中创建,并且在计算机储存介质(诸如磁盘、磁带、物理硬盘驱动器或诸如存储器访问网络中的虚拟硬盘驱动器)中储存。如果设计者不制造芯片或者用于制造芯片的光刻掩模,则设计者可以由物理机制(例如通过提供储存设计的存储器介质的拷贝件)或电子地(例如通过因特网)将得到的设计直接地或间接地传输到这样的实体。然后将储存的设计转换为光刻掩模的制造的适当的格式(例如GDSII),这包含晶片上要形成的考虑中的芯片设计的多个拷贝件。光刻掩模用于限定晶片的要蚀刻或者要处理的区域。
如本文所描述的方法可以用于集成电路芯片的制造中。得到的集成电路芯片可以由制造者以原始的晶片形式(换言之,具有多个未封装的芯片的单个晶片)来分布,如裸芯,或者以封装的形式来分布。在后述的情况下,将芯片安装在单个芯片封装体(诸如塑料载体,带有粘附到母板或其他较高级别载体的引线)中,或者在多芯片封装体(诸如具有表面互连件和埋置的互连件之一或二者的陶瓷载体)中。在任何情况下,然后将该芯片与其他芯片、离散电路元件和/或其他信号处理装置集成,以作为(a)诸如母板的中间产品或是(b)终端产品的部件。终端产品可以是包含集成电路芯片的任何产品,范围从玩具和其他低端应用到具有显示器、键盘或其他输入装置以及中央处理器的先进计算机产品。
还应该理解的是,在列出的元素(例如SiGe)方面将描述材料化合物。这些化合物包含化合物内不同比例的元素,例如SiGe包含SixGe1-x,其中x小于或等于1,等等。附加地,根据本实施例,其他元素可以包含在化合物中并且仍然起作用。具有附加的元素的化合物将在本文被称为合金。说明书中参考本发明的“一个实施例”或“实施例”及其其他变型,意味着与实施例有关的所描述的特定特征、结构或特性等等包含在本发明的至少一个实施例中。因此,在说明书各种地方出现的短语“一个实施例中”或“实施例中”以及任何其他变型不必都指代相同的实施例。
应当理解的是,使用以下中的任一个旨在于涵盖仅选择列出的第一可选项(A)、或仅选择列出的第二可选项(B)、或者选择两个可选项(A和B):“/”、“和/或”和“中的至少一个”,例如在“A/B”、“A和/或B”和“A和B中的至少一个”的情况下。作为另一个示例,在“A、B和/或C”和“A、B和C中的至少一个”的情况下,这样的短语旨在于涵盖仅选择列出的第一可选项(A)、或仅选择列出的第二可选项(B)、或仅选择列出的第三可选项(C)、或仅选择列出的第一和第二可选项(A和B)、或仅选择列出的第一和第三可选项(A和C)、或仅选择列出的第二和第三可选项(B和C)、或选择全部三个可选项(A和B和C)。如本领域或相关领域的普通技术人员显而易见,这可以扩展到所列出的许多项目。
本文中所使用的术语仅为了描述特定实施例,而不旨在于对示例实施例进行限制。如本文所使用的,单数形式“一”、“一个”和“该”也旨在于包括复数形式,除非上下文另外明确指示。还将理解的是,术语“包括”、“包含”和/或“含有”,在用于本文中的时候,指定存在所述的特征、整数、步骤、操作、元件和/或组件,但是不排除存在或添加一个或多个其他特征、整数、步骤、操作、元件、组件和/或其组合。
空间相关术语(诸如“之下”、“下方”、“下部”、“上方”、“上部”等)可以在本文中用于简单描述,以如附图所示描述一个元件或特征与其他元件或特征的关系。将理解的是,空间相关术语旨在于涵盖使用或操作中装置的除了附图中所描绘的取向以外的不同取向。例如,如果翻转附图中的装置,则描述为在其他元件或特征“下方”或“之下”的元件取向为在其他元件或特征“上方”。因此,术语“下方”可以涵盖上方和下方二者的取向。装置可以用其他方式取向(旋转90度或在其他取向处),并且可以因此解释本文所使用的空间相关描述。附加地,将还理解的是,当层被称为“在”两层“之间”时,可以在两层之间只有该层,或者还可以存在一个或多个中间层。
将理解的是,尽管术语第一、第二等可以在本文用于描述各种元件,这些元件应该不限于这些术语。这些术语仅用于将一个元件与另一个元件区分开。因此,在不脱离本构思的范围的情况下,下面讨论的第一元件可以被称为第二元件。
已经描述了采用选择性金属沉积以构建与Mx和Mx+1沟槽图案的交叉处自对准的通孔的方法的优选实施例(其旨在于说明性而非限制性),值得注意的是,本领域技术人员可以根据上述教导做出修改和改变。因此理解的是,如由所附的权利要求概括的本发明的范围内所描述的特定实施例可以在做出改变。因此已经用专利法所要求的细节和特殊性描述本发明的各方面,在所附权利要求中提出了由专利证书所主张并且期望保护的内容。
Claims (20)
1.一种通过采用选择性金属沉积来创建完全对准的通孔(FAV)的方法,所述方法包括:
在第一层间电介质(ILD)层内形成金属线;
在所述第一层间电介质层之上形成第二层间电介质层;
在所述第二层间电介质层之上形成光刻堆叠体,以限定防止通孔生长的区域;
使所述光刻堆叠体凹陷,以暴露所述金属线的由所述光刻堆叠体允许通孔生长的顶表面;以及
在所述金属线的允许通孔生长的暴露的顶表面之上进行金属生长。
2.根据权利要求1所述的方法,还包括移除所述光刻堆叠体,并且在所述金属生长之上沉积共形金属氮化物盖。
3.根据权利要求2所述的方法,还包括在所述共形金属氮化物盖之上沉积低k材料层。
4.根据权利要求3所述的方法,还包括使所述低k材料层凹陷,以暴露在所述金属生长之上的所述共形金属氮化物盖的顶表面。
5.根据权利要求4所述的方法,还包括移除在所述金属生长之上的所述共形金属氮化物盖的暴露的顶表面,以暴露所述金属生长的顶表面。
6.根据权利要求5所述的方法,还包括在所述金属生长的暴露的顶表面之上进行单镶嵌金属化。
7.根据权利要求6所述的方法,其中所述金属生长是一个或多个自对准的通孔互连结构。
8.根据权利要求7所述的方法,其中,在使所述低k材料层凹陷之后,所述低k材料层的部分保留在所述金属生长和所述第二层间电介质层之间。
9.根据权利要求1所述的方法,还包括在形成所述第二层间电介质层之前,在所述金属线之上形成绝缘蚀刻停止层。
10.一种通过采用选择性金属沉积来创建完全对准的通孔(FAV)的方法,所述方法包括:
在第一层间电介质层内形成金属线;
在所述金属线之上形成绝缘蚀刻停止层;
在所述绝缘蚀刻停止层之上形成第二层间电介质层;
在所述第二层间电介质层之上形成光刻堆叠体,以限定防止通孔生长的区域;
使所述光刻堆叠体凹陷,以暴露所述金属线的由所述光刻堆叠体允许通孔生长的顶表面;
在所述金属线的允许通孔生长的暴露的顶表面之上进行金属生长;以及
在所述金属生长之上沉积共形金属氮化物盖,使得在所述金属生长和所述第二层间电介质层之间形成气隙。
11.根据权利要求10所述的方法,还包括在沉积所述金属生长之前,移除所述光刻堆叠体。
12.根据权利要求11所述的方法,还包括移除在所述金属生长之上的所述共形金属氮化物盖的暴露的顶表面,以暴露所述金属生长的顶表面。
13.根据权利要求12所述的方法,还包括在所述金属生长的暴露的顶表面之上进行单镶嵌金属化。
14.根据权利要求13所述的方法,其中所述金属生长是一个或多个自对准的通孔互连结构。
15.根据权利要求10所述的方法,其中所述光刻堆叠体包含至少两个牺牲层和有机平坦化层。
16.根据权利要求15所述的方法,其中所述光刻堆叠体还包含抗反射涂层层和光刻胶层。
17.一种通过采用选择性金属沉积来创建完全对准的通孔(FAV)的半导体结构,所述半导体结构包括:
金属线,其设置在第一层间电介质层内;
第二层间电介质层,其设置在所述第一层间电介质层之上;
金属生长,其设置在允许通孔生长的暴露的金属线之上;以及
共形金属氮化物盖,其设置在所述金属生长之上,使得在所述金属生长和所述第二层间电介质层之间形成气隙。
18.根据权利要求17所述的半导体结构,其中在沉积所述第二层间电介质层之前,在所述金属线之上设置绝缘蚀刻停止层。
19.根据权利要求18所述的半导体结构,其中通过采用单镶嵌金属化在所述金属生长之上设置导电材料。
20.根据权利要求19所述的半导体结构,其中所述导电材料、所述金属生长和所述暴露的金属线是对准的。
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