CN115602628A - 半导体结构 - Google Patents
半导体结构 Download PDFInfo
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- CN115602628A CN115602628A CN202210009184.2A CN202210009184A CN115602628A CN 115602628 A CN115602628 A CN 115602628A CN 202210009184 A CN202210009184 A CN 202210009184A CN 115602628 A CN115602628 A CN 115602628A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 74
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 239000010410 layer Substances 0.000 description 191
- 238000000034 method Methods 0.000 description 60
- 230000008569 process Effects 0.000 description 39
- 239000000463 material Substances 0.000 description 30
- 230000004888 barrier function Effects 0.000 description 25
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 21
- 229920002120 photoresistant polymer Polymers 0.000 description 21
- 229910052710 silicon Inorganic materials 0.000 description 21
- 239000010703 silicon Substances 0.000 description 21
- 238000002955 isolation Methods 0.000 description 14
- 238000005229 chemical vapour deposition Methods 0.000 description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 11
- 229910052782 aluminium Inorganic materials 0.000 description 11
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 11
- 238000000231 atomic layer deposition Methods 0.000 description 11
- 229910017052 cobalt Inorganic materials 0.000 description 10
- 239000010941 cobalt Substances 0.000 description 10
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 10
- 229910010271 silicon carbide Inorganic materials 0.000 description 10
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 9
- 229910052581 Si3N4 Inorganic materials 0.000 description 9
- 238000005530 etching Methods 0.000 description 9
- 229910052707 ruthenium Inorganic materials 0.000 description 9
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 9
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 9
- 150000001875 compounds Chemical class 0.000 description 8
- 229910052814 silicon oxide Inorganic materials 0.000 description 8
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 7
- 229910052741 iridium Inorganic materials 0.000 description 7
- GKOZUEZYRPOHIO-UHFFFAOYSA-N iridium atom Chemical compound [Ir] GKOZUEZYRPOHIO-UHFFFAOYSA-N 0.000 description 7
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 7
- 229910052750 molybdenum Inorganic materials 0.000 description 7
- 239000011733 molybdenum Substances 0.000 description 7
- 238000005240 physical vapour deposition Methods 0.000 description 7
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 7
- 229910052703 rhodium Inorganic materials 0.000 description 7
- 239000010948 rhodium Substances 0.000 description 7
- MHOVAHRLVXNVSD-UHFFFAOYSA-N rhodium atom Chemical compound [Rh] MHOVAHRLVXNVSD-UHFFFAOYSA-N 0.000 description 7
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 7
- 229910052721 tungsten Inorganic materials 0.000 description 7
- 239000010937 tungsten Substances 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 6
- 239000004020 conductor Substances 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000010949 copper Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- 238000000059 patterning Methods 0.000 description 6
- 230000005855 radiation Effects 0.000 description 6
- -1 silicon carbide nitride Chemical class 0.000 description 6
- 229910052719 titanium Inorganic materials 0.000 description 6
- 239000010936 titanium Substances 0.000 description 6
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 5
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 description 5
- FEBFYWHXKVOHDI-UHFFFAOYSA-N [Co].[P][W] Chemical compound [Co].[P][W] FEBFYWHXKVOHDI-UHFFFAOYSA-N 0.000 description 5
- 229910021332 silicide Inorganic materials 0.000 description 5
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 239000011248 coating agent Substances 0.000 description 4
- 238000000576 coating method Methods 0.000 description 4
- PMHQVHHXPFUNSP-UHFFFAOYSA-M copper(1+);methylsulfanylmethane;bromide Chemical compound Br[Cu].CSC PMHQVHHXPFUNSP-UHFFFAOYSA-M 0.000 description 4
- 238000000151 deposition Methods 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 230000000873 masking effect Effects 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- TWNQGVIAIRXVLR-UHFFFAOYSA-N oxo(oxoalumanyloxy)alumane Chemical compound O=[Al]O[Al]=O TWNQGVIAIRXVLR-UHFFFAOYSA-N 0.000 description 4
- 229910052715 tantalum Inorganic materials 0.000 description 4
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 4
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 description 4
- 229910000530 Gallium indium arsenide Inorganic materials 0.000 description 3
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 3
- ZGUQGPFMMTZGBQ-UHFFFAOYSA-N [Al].[Al].[Zr] Chemical compound [Al].[Al].[Zr] ZGUQGPFMMTZGBQ-UHFFFAOYSA-N 0.000 description 3
- 239000012790 adhesive layer Substances 0.000 description 3
- RRZKHZBOZDIQJG-UHFFFAOYSA-N azane;manganese Chemical compound N.[Mn] RRZKHZBOZDIQJG-UHFFFAOYSA-N 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000011049 filling Methods 0.000 description 3
- 239000011796 hollow space material Substances 0.000 description 3
- 238000001459 lithography Methods 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 3
- 229910001928 zirconium oxide Inorganic materials 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 2
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 description 2
- GPXJNWSHGFTCBW-UHFFFAOYSA-N Indium phosphide Chemical compound [In]#P GPXJNWSHGFTCBW-UHFFFAOYSA-N 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 2
- LEVVHYCKPQWKOP-UHFFFAOYSA-N [Si].[Ge] Chemical compound [Si].[Ge] LEVVHYCKPQWKOP-UHFFFAOYSA-N 0.000 description 2
- FTWRSWRBSVXQPI-UHFFFAOYSA-N alumanylidynearsane;gallanylidynearsane Chemical compound [As]#[Al].[As]#[Ga] FTWRSWRBSVXQPI-UHFFFAOYSA-N 0.000 description 2
- 230000008859 change Effects 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 230000008021 deposition Effects 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 229910052733 gallium Inorganic materials 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 229910021389 graphene Inorganic materials 0.000 description 2
- 238000009616 inductively coupled plasma Methods 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 238000007669 thermal treatment Methods 0.000 description 2
- 229910052726 zirconium Inorganic materials 0.000 description 2
- ZXEYZECDXFPJRJ-UHFFFAOYSA-N $l^{3}-silane;platinum Chemical compound [SiH3].[Pt] ZXEYZECDXFPJRJ-UHFFFAOYSA-N 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-M Acrylate Chemical compound [O-]C(=O)C=C NIXOWILDQLNWCW-UHFFFAOYSA-M 0.000 description 1
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 101000869523 Homo sapiens Phosphatidylinositide phosphatase SAC2 Proteins 0.000 description 1
- 101000869517 Homo sapiens Phosphatidylinositol-3-phosphatase SAC1 Proteins 0.000 description 1
- 229910000673 Indium arsenide Inorganic materials 0.000 description 1
- 102100032287 Phosphatidylinositide phosphatase SAC2 Human genes 0.000 description 1
- 102100032286 Phosphatidylinositol-3-phosphatase SAC1 Human genes 0.000 description 1
- 229920002396 Polyurea Polymers 0.000 description 1
- 230000004075 alteration Effects 0.000 description 1
- AJGDITRVXRPLBY-UHFFFAOYSA-N aluminum indium Chemical compound [Al].[In] AJGDITRVXRPLBY-UHFFFAOYSA-N 0.000 description 1
- 239000006117 anti-reflective coating Substances 0.000 description 1
- 238000004380 ashing Methods 0.000 description 1
- YXTPWUNVHCYOSP-UHFFFAOYSA-N bis($l^{2}-silanylidene)molybdenum Chemical compound [Si]=[Mo]=[Si] YXTPWUNVHCYOSP-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- WUKWITHWXAAZEY-UHFFFAOYSA-L calcium difluoride Chemical compound [F-].[F-].[Ca+2] WUKWITHWXAAZEY-UHFFFAOYSA-L 0.000 description 1
- 229910001634 calcium fluoride Inorganic materials 0.000 description 1
- 150000007942 carboxylates Chemical class 0.000 description 1
- 239000000460 chlorine Substances 0.000 description 1
- 229910052801 chlorine Inorganic materials 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000000609 electron-beam lithography Methods 0.000 description 1
- 239000002360 explosive Substances 0.000 description 1
- 230000009969 flowable effect Effects 0.000 description 1
- 239000005350 fused silica glass Substances 0.000 description 1
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- WPYVAWXEWQSOGY-UHFFFAOYSA-N indium antimonide Chemical compound [Sb]#[In] WPYVAWXEWQSOGY-UHFFFAOYSA-N 0.000 description 1
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000002527 ion beam patterning Methods 0.000 description 1
- 239000002052 molecular layer Substances 0.000 description 1
- 229910021344 molybdenum silicide Inorganic materials 0.000 description 1
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 1
- 229910021334 nickel silicide Inorganic materials 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 230000001590 oxidative effect Effects 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 230000000737 periodic effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229910021339 platinum silicide Inorganic materials 0.000 description 1
- 238000005498 polishing Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 239000002094 self assembled monolayer Substances 0.000 description 1
- 239000013545 self-assembled monolayer Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 229910021341 titanium silicide Inorganic materials 0.000 description 1
- UONOETXJSWQNOL-UHFFFAOYSA-N tungsten carbide Chemical compound [W+]#[C-] UONOETXJSWQNOL-UHFFFAOYSA-N 0.000 description 1
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
- 229910021342 tungsten silicide Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823475—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type interconnection or wiring or contact manufacturing related aspects
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/5226—Via connections in a multilevel interconnection structure
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
-
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76805—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics the opening being a via or contact hole penetrating the underlying conductor
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- H—ELECTRICITY
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
-
- H—ELECTRICITY
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
- H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53257—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a refractory metal
- H01L23/53266—Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
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Abstract
一种半导体结构,包括基板、介电层、第一导电特征件和第二导电特征件。该基板包括半导体器件。该介电层设置于该基板上。该第一导电特征件形成于该介电层中。该第二导电特征件穿透该第一导电特征件与该介电层,且电连接至该第一导电特征件与该半导体器件。
Description
技术领域
本发明实施例涉及一种半导体结构及其形成方法,特别是有关于具有深金属线的半导体结构及用于形成该半导体结构的方法。
背景技术
半导体集成电路(IC)产业在过去几十年中经历了巨大的进步,且仍在经历着蓬勃的发展。随着IC设计的显著进步,新一代的集成电路具有更小且更复杂的电路。镶嵌制程,例如单镶嵌或双镶嵌,是用于形成BEOL(back-end-of-line,后段制程)互连结构(interconnect structure)的技术中的一种。互连结构对于新一代IC的小型化及电气性能方面扮演重要角色。因此,业界非常重视互连结构的发展。
发明内容
本发明的一态样是提出一种半导体结构,包括基板、介电层、第一导电特征件与第二导电特征件。该基板包括半导体器件。所述介电层设置于所述基板上。所述第一导电特征件形成于所述介电层中。所述第二导电特征件穿透所述第一导电特征件与所述介电层,且电连接至所述第一导电特征件与所述半导体器件。
本发明的另一态样是提出一种半导体结构,包括基板、第一介电层、互连结构与第二导电特征件。基板包含晶体管。所述第一介电层设置于所述基板上。所述互连结构包括:第一导电特征件,其设置于所述第一介电层上并相反于所述基板;以及第二介电层,其围绕所述第一导电特征件。所述第二导电特征件穿透所述互连结构,且电连接至所述第一导电特征件与所述晶体管。
本发明的又一态样是提出一种半导体结构的制造方法,包含:提供基板,其包含半导体器件;在所述基板上形成介电层;在所述介电层中形成第一导电特征件,所述第一导体特征件与所述基板分开;形成通孔,其穿透所述第一导电特征件及所述介电层以暴露出所述半导体器件的接触件;以及在所述通孔中形成第二导电特征件,使所述第二导电特征件电连接至所述半导体器件的所述第一导电特征件及所述接触件。
附图说明
当结合附图阅读时,自以下详细描述可最佳理解本揭露的态样。请注意为遵循业界标准作法,各种特征没有按比例绘制。事实上,为使讨论内容清楚,各种特征的尺寸可任意地放大或缩小。
图1至图4示出了根据一些实施例的半导体结构的形成中各个阶段的示意图。
图5示出了根据一些实施例的用于制造半导体结构的制程流程。
图6示出了根据一些实施例的半导体结构的布局。
图7A至图16B示出了根据一些实施例的半导体结构的形成的各阶段的示意图。
图17为根据一些实施例的半导体结构的放大剖面示意图。
图18示出了图16A中描述的结构的替代例。
图19至图21示出了根据一些实施例的隔离特征件的各种范例。
图22及图23示出了根据一些实施例的隔离特征件的其他范例。
具体实施方式
较佳实施例的详细说明
以下揭露内容提供许多不同实施例或范例,用于实现本揭露的不同特征。为简化本揭露,以下描述组件及配置(arrangements)的具体范例。当然,这些仅为范例且非意欲作为限制。举例来说,在以下叙述中,一第一特征件形成于一第二特征件之上或上方,可能包含形成直接接触的第一特征件与第二特征件的实施例,也可能包含有形成于第一特征件与第二特征件之间的附加特征件的实施例,而使第一特征件与第二特征件可能未直接接触。此外,本揭露可能会在不同范例中重复参考符号和/或字母。前述作法本身并不表示所讨论的各种实施例及/或配置之间的关系。
此外,为便于描述,可在本文中使用诸如「在...下面」、「在...下方」、「下」、「在...上方」、「上」及类似者的空间相对术语来描述如图所说明的一个组件或特征件与另一(些)组件或特征件的关系。除图中描绘的方向外,空间相对术语意图是涵盖器件在使用或操作中的不同的方向。设备可被以其他方式定向(旋转90度或其他方位),且文中所使用的空间相对描述词也将据此来解释。
图1至图4是说明形成半导体结构的步骤的示意图。
参考图1,提供基板10,其形成有多个晶体管101,每一个晶体管包括源极102、漏极103、连接在源极102与漏极103之间的通道104与栅极105。晶体管101可通过隔离特征件106分离,如浅沟槽隔离(STI)或类似者。然后在基板10上形成第一介电层11,接着将第一介电层11图案化以形成通孔111,以暴露出晶体管101中的至少一者的源极102、漏极103和栅极105的至少一者。参考图2,在形成及图案化第一介电层11之后,通过合适的沉积技术,例如化学气相沉积(CVD)或类似者,在第一介电层11与通孔111(见图1)中沉积导电材料,以填充通孔111,而后进行合适的平坦化技术,例如化学机械抛光(CMP)或类似者,以将沉积的导电材料薄化,以在通孔111(见图1)中形成接触插塞12。参考图3,在形成接触插塞12之后,在第一介电层11上形成第二介电层13,接着将第二介电层13图案化,以形成通孔131,以暴露出接触插塞12。在第一介电层11中形成多个通孔111且随后在此等通孔111中形成多个接触插塞12的情况下,通过图案化第二介电层13形成的通孔131可暴露接触插塞12的一或多者。参考图4,在形成及图案化第二介电层13之后,通过诸如物理气相沉积或类似者的合适沉积技术在第二介电层13上沉积导电材料以填充通孔131(见图3),继之以执行诸如CMP或类似者的合适平坦化技术以薄化经沉积的导电材料以形成导线14。
图6示意性地示出半导体结构300的布局,其包括多个半导体器件(例如晶体管301)。每一个半导体器件包括至少两个MD结构302和一MG结构303。在一些实施例中,MD指的是OD(oxide-defining region,氧化物定义区域)上金属,其可连接至一个晶体管301的源极或漏极区(未绘示)。在一些实施例中,MG是指金属栅极,其可由金属或多晶硅制成,且是一个晶体管301的栅极结构的一部分。图7A至图16B示出根据一些实施例的形成半导体结构300的中间步骤的示意图。图7A至图16A中的各者显示在制造半导体结构300期间从图6的线A-A截取的示意性剖视图,图7B-图16B中各者显示在制造半导体结构300期间从图6的线B-B截取的示意性剖视图。对应的制程也反映在图5所示的流程图200中。
参考图6、图7A与图7B,依据某些实施例,提供一基板30。此制程被说明于图5所示流程图200中的制程202。在一些实施例中,晶体管301部分形成于基板30中。在一些实施例中,基于实际应用,晶体管301的各者可为互补式金属氧化物半导体(complementarymetal-oxide semiconductor;CMOS)晶体管、平面或垂直多栅极晶体管(例如,FinFET器件)、环绕式栅极(gate-all-around;GAA)器件、存储器件(例如,NAND闪存、NOR闪存,或类似者)或类似者。于一些实施例中,基板30可为半导体基板,例如元素半导体(elementalsemiconductor)或化合物半导体(compound semiconductor)。元素半导体由单一种类的原子组成,例如在周期表IV族中的硅(Si)与锗(Ge)。化合物半导体由二或更多个元素组成,诸如碳化硅(SiC)、砷化镓(GaAs)、磷化镓(GaP)、磷化铟(InP)、砷化铟(InAs)、锑化铟(InSb)、硅锗(SiGe)、磷砷化镓(GaAsP)、砷化铝铟(AlInAs)、砷化铝镓(AlGaAs)、砷化镓铟(GaInAs)、磷化镓铟(GaInP)、磷砷化镓铟(GaInAsP)或类似物。化合物半导体可具有梯度特征,其中组成由一位置的一比例改变为在化合物半导体中的另一位置的另一比例。化合物半导体可形成于硅基板上。化合物半导体可为应变的。在一些实施例中,基板30可包括多层的化合物半导体结构。或者,基板30可包含非半导体材料,例如玻璃、熔融石英或氟化钙。再者,在某些实施例中,基板30可为绝缘层上半导体(SOI)(例如绝缘层上硅锗(SGOI))。一般而言,SOI基板包括一层半导体材料如磊晶硅(Si)、锗(Ge),硅锗(SiGe),或其等的组合。如本领域中已知的,基板30可掺杂p型掺质如硼(B)、铝(Al)、镓(Ga)、或类似者,或也可掺杂n型掺质。在一些实施例中,基板30可包括掺杂磊晶层。浅沟槽隔离(shallow trenchisolation,STI)区域(未绘示)可形成于基板30内,以隔离基板30内的有源区(activeregion)。此外,可形成延伸进入基板30的穿孔(through-vias)(未绘示),以电连接基板30的相对侧上的特征件。
根据一些实施例,每一晶体管301的源极区和漏极区和MG结构303的顶部可形成有硅化物特征件(未绘示),以改善与后续形成的电连接特征件的电连接。在一些实施例中,硅化物特征件可以包括钴硅化物、钛硅化物、钨硅化物、镍硅化物、钼硅化物、钽硅化物、铂硅化物、钯硅化物,或类似者。在一些实施例中,MD结构302与MG结构303可被多个间隔物304、305隔开,其可由合适的材料制成,例如氮化硅、氧化硅或类似者。在一些实施方式中,间隔物304及305可由不同材料制备。
依据一些实施例,晶体管301中每一者的MG结构303可被第一介电层331(可被称为第一自对准接触(SAC)介电体或SAC1层)覆盖,且晶体管301中每一者的MD结构302可被第二介电层332(可被称为第二自对准接触(SAC)介电体或SAC2层)覆盖。在一些实施例中,第一介电层331和第二介电层332可被第三介电层333(可以被称为层间介电(ILD2)层)覆盖。第一、第二和第三介电层331、332、333中的每一者可包括多个子层(未绘示),且可由适当的电介质材料制成,例如氧化硅、氮化硅、碳化硅(包括未掺杂碳化硅(UDC)、掺杂氧的碳化硅(ODC)、掺杂氮的碳化硅(NDC)或类似者)、氮氧化硅、碳氧化硅(包括SiOCH)、碳氮化硅(silicon carbonitride)、碳氧化硅的氮化物(silicon oxycarbide nitride)、氧化铝、氮氧化铝、氮化铝、氧化锆、氮氧化铝锆(zirconium aluminum oxynitride)、非晶硅或其等的组合。在一些实施例中,氧化硅可由正硅酸乙酯(TEOS)所制成。在一些实施例中,第一介电层331、第二介电层332以及第三介电层333可由不同材料制成。第一介电层331、第二介电层332、与第三介电层333各自的形成方法可为任何合适制程如CVD(例如可流动CVD(FCVD)、低压CVD(LPCVD)、等离子体增强CVD(PECVD)、或类似者)、PVD、ALD、旋转涂布、及/或其他合适技术,且可具有任何合适厚度。
参考图6、图8A与图8B,根据一些实施例,形成第一导电特征件341于第三介电层333上。此制程说明于图5所示流程图200中的制程204。在一些实施例中,在形成第一导电特征件341之前,黏着层342可形成于第三介电层333上,且可包含钽、氮化钽、钴、钌、钛、氮化钛、氮化锰、钨、铝、钼、铱、铑、石墨烯、导电自组装单层体或类似者。可使用合适的技术沉积黏着层342,像是PVD、CVD、原子层沉积(ALD)等。在一些实施例中,第一导电特征件341为金属层,且可由铜、钌、钨、钛、铝、钴、钼、铱、铑、钴-钨-磷(cobalt-tungsten-phosphorus)、其等的组合、或类似物制成。在一些实施例中,第一导电特征件341可由合适技术所形成,比如PVD、CVD、ALD、无电沉积(ELD)、PVD及电化学电镀(ECP)的组合、或类似者。
参考图9A与图9B,在形成黏着层342与第一导电特征件341之后,于第一导电特征件341上形成掩模层35。之后,将掩模层35图案化为所期望的形状。此制程说明于图5所示的流程图200中的制程206。在一些实施例中,掩模层35可具有范围自约至约的厚度。根据一些实施例,掩模层35可包括多个子层(如第一子层352与第二子层353),其各自由合适的材料组成,比如氮化钛、氧化硅、氮化硅、氮氧化硅、碳化钨、氮化钽、硅(如非晶硅)、碳氧化硅(silicon oxycarbide)(包括SiOCH)、碳化硅(包括UDC、ODC、NDC或类似者)、或其等的组合。在一些实施例中,第一子层352可由氮化硅制成,并且第二子层353可以由氮化钛制成。掩模层35的可由合适的技术形成,比如旋转涂布、CVD(如FCVD、LPCVD、PECVD、或类似者)、ALD、或类似者。
根据一些实施例,光阻(未绘示)可用于图案化的掩模层35。先于掩模层35上形成光阻,接着采用图案化的掩模图案化光阻。光阻可包括光敏材料,当曝露于光时其经历性质改变。性质改变可在微影图案化制程中选择性地移除光阻曝光部分或未曝光部分。在一些实施例中,微影系统将光阻暴露至辐射。通过图案化掩模的辐射光照射光阻,以借此将图案化掩模的布局转移至光阻。在一些实施例中,使用直接写入或无掩模微影技术,例如激光图案化、电子束图案化、离子束图案化或类似者,将光阻图案化。在曝光步骤后,接着使光阻显影,保留光阻的曝光部分,或在其他范例中,保留光阻的未曝光部分。在一些实施例中,图案化制程可包括多个步骤,比如光阻的软烘烤、掩模对准、曝光、曝光后烘烤、光阻显影、冲洗、与干燥(如硬烘烤)。所述步骤的每一者可根据实际需求重复或省略。图案化的光阻暴露出掩模层35将被蚀刻的部分。在一些实施例中,蚀刻制程可包含非等向(如方向性)蚀刻,其被配置以垂直蚀刻穿过掩模层35而实质上不水平蚀刻。因此,蚀刻制程可包括任何适合的蚀刻技术,例如干蚀刻、湿蚀刻、反应离子蚀刻(RIE)、灰化或类似者。蚀刻制程可使用任何合适的蚀刻剂,且特定的蚀刻剂或多个蚀刻剂可取决于所使用的掩模层35的材料。
参考图10A与图10B,在形成并图案化的掩模层35之后,采用图案化的掩模层35作为掩模,图案化第一导电特征件341以形成通孔结构343。根据一些实施例,在此步骤中也图案化黏着层342。此制程说明于第5图所示的流程图200中的制程208。第一导电特征件341由合适的技术如含氯的氧化等离子体或类似者进行图案化。在一些实施例中,黏着层342或第三介电层333可作为蚀刻第一导电特征件341的蚀刻停止层。
参考图11A与图11B,在图案化第一导电特征件341之后,于掩模层35上形成第四介电层36并填入通孔结构343(见图10A)。此制程说明于图5所示流程图200中的制程212。在一些实施例中,气隙361可被形成,且可邻近或邻接于第一导电特征件341。在某些实施例中,气隙361可由第四介电层36、第一导电特征件341及第三介电层333所定义。第四介电层36是由合适的电介质材料形成,例如氧化硅、氮化硅、碳化硅(包括UDC、ODC、NDC或类似者)、氮氧化硅、碳氧化硅(silicon carbide nitride,包括SiOCH)、碳氧化硅的氮化物(siliconoxycarbide nitride)、氧化铝、氮氧化铝、氮化铝、氧化锆、氮氧化铝锆(zirconiumaluminum oxynitride)、非晶硅或其等的组合。在一些实施例中,二氧化硅可由TEOS制成。介电层36可使用合适的技术形成,像是旋转涂布、CVD(例如FCVD、LPCVD、PECVD、或类似者)、ALD、或类似者。
根据一些实施例,在形成第四介电层36之前,可保形地(conformally)形成阻障/衬垫层37,以覆盖图案化的掩模层35并且环绕通孔结构343(见图10A)。此制程说明于图5所示的流程图200中的制程210。在一些实施例中,阻障/衬垫层37由合适的氧化物材料、ODC、氮化硅(例如碳氮化硅)、氧化铝、氮化铝或类似者制成,且可通过合适的技术形成,例如CVD(例如FCVD、LPCVD、PECVD或类似者)、ALD(包含等离子体增强ALD(PEALD))或类似者。
参考图12A与图12B,在形成第四介电层36之后,对第四介电层36和阻障/衬垫层37进行合适的平坦化制程,例如等离子体干蚀刻、CMP或类似者。此制程说明于图5所示的流程图200中的制程214。在一些实施例中,移除形成于图案化的掩模层35的上表面351上的第四介电层36的一部分与阻障/衬垫层37的一部分。在某些实施例中,图案化的掩模层35的第一子层352的一部分也被移除。在一些实施例中,可完全移除第一子层352,并且可移除第二子层353的一部分。
参考图13A与图13B,在平坦化制程之后,光阻52形成于图案化的掩模层35上方。在某些实施例中,在形成光阻52之前,可在图案化的掩模层35上方形成中间层(ML)与底层(BL),其为图13A与图13B中的标号51所标示。在一些实施例中,中间层可以是含硅抗反射涂层(SiARC),例如SiCxHyOz或类似者,并且底层可以是光学平坦化层,例如CxHyOz或类似者。在形成光阻52与中间层与底层51之后,可图案化光阻52以形成开口53。
参考图14A与图14B,在图13A与图13B所说明的制程之后,形成穿透图案化的掩模层35、第一导电特征件341、黏着层342、第三介电层333和第二介电层332的通孔38,以露出对应的晶体管301(请见图6)的MD结构302。图13A至图14B所说明的制程,被一起说明于图5所示的流程图200中的制程216。通孔38的形成可通过任何适合蚀刻技术进行,诸如电容耦合等离子体(CCP)、感应耦合等离子体(ICP)、变压器耦合等离子体(TCP)或类似者。在一些实施例中,第一介电层331和第二介电层332可由不同材料组成以具有不同的蚀刻选择性,如此一来,在蚀刻制程中,第一介电层331被蚀刻穿透,而第二介电层332实质上保持未蚀刻或仅被轻微蚀刻。在一些实施例中,第一介电层331由氧化硅组成,第二介电层332由氮化硅组成,且氧化硅相对氮化硅的蚀刻速率可大于10。在一些实施例中,在形成通孔38期间MD结构302可被稍微蚀刻。
参考图15A与图15B,在形成通孔38之后,形成一阻障层391,其后在阻障层391上形成一衬垫层392。此制程说明于图5所示的流程图200中的制程218。在某些实施例中,阻障层391是形成于图案化的掩模层35的上表面351(见图12A与图12B)及图案化的第四介电层36的上表面362(见图12A)上,并围绕通孔38(见图14A)。在一些实施例中,阻障层391及衬垫层392的各者是由一导电材料制成,包含钽、氮化钽、钴、钌、钛、氮化钛、氮化锰或其等的组合。阻障层391及衬垫层392的各者可通过合适的技术形成,诸如CVD(例如,FCVD、LPCVD、PECVD或类似者)、ALD(包括PEALD)或类似者。
在形成阻障层391及衬垫层392之后,在衬垫层392上方形成第二导电特征件393。此制程说明于图5所示流程图200的制程220中。在一些实施例中,第二导电特征件393是一金属层,且可由包含铜、钌、钨、钛、铝、钴、钼、铱、铑、钴-钨-磷(cobalt-tungsten-phosphorus)或其等的组合的一材料制成。在一些实施例中,可通过合适的技术形成第二导电特征件393,例如PVD、CVD、ALD、ELD、PVD和ECP的组合或类似者。在一些实施例中,第二导电特征件393电连接至对应的晶体管301(参见图6)的MD结构302。
参考图16A与图16B,在形成第二导电特征件393之后,通过适合技术,诸如等离子体干蚀刻、CMP或类似者,对第二导电特征件393进行平坦化。此制程说明于图5所示的流程图200中的制程222。在一些实施例中,第二导电特征件393的一部分、阻障层391和衬垫层392的一部分、第四介电层36的一部分、阻障/衬垫层37的一部分和图案化的掩模层35被移除,以得到半导体结构300。在一些实施例中,衬垫层392围绕且连接至第二导电特征件393,阻障层391围绕且连接至衬垫层392,且第二导电特征件393经由衬垫层392及阻障层391而连接至第一导电特征件341。在一些实施例中,依据实际应用,第一导电特征件341与第二导电特征件393可由相同或不同的材料所组成。如图16A与图16B中所示,在一些实施例中,第二导电特征件393可部分地落在对应的晶体管301(见图6)的MD结构302上。在其他实施例中,第二导电特征件393可完全落在对应晶体管301的MD结构302上。在某些实施例中,形成于通孔38(见图14A)中的第二导电结构393,可对应至形成于光阻52中的开口53(见图13A)。在一些实施例中,第二导电特征件393的俯视图如图6中所展示。
在一些实施例中,可对半导体结构300进行后续的互连(interconnect)形成制程,例如单一或双镶嵌制程,以于半导体结构300上形成多个互连层,以实现半导体结构300所需的电连接。参考图6,根据一些实施例,相应晶体管301的MG结构303可经由电连接结构,例如贯孔70,电连接至第一导电特征件341。
参考图6、图16A、图16B及图17,在一些实施例中,通孔结构343包括多个通孔343'(见图10A),其将第一导电特征件341分成多个导电组件341'。第二导电特征件393穿透导电组件341'中的对应一者。在一些实施例中,在得到半导体结构300之后,图案化的第四介电层36、阻障/衬垫层37与气隙361共同地定义一隔离特征件41。在一些实施例中,在邻近的两个隔离特征件41之间的最小间距(P)在约12nm至约42nm的范围内,但也可以在此范围外。在一些实施例中,隔离特征件41的深宽比,其定义为隔离特征件41的高度(H2)除以隔离特征件41的直径(D2),可以在约1至约4的范围内,但也可以在此范围外。在一些实施例中,隔离特征件41的高度(H2)在约10nm至约35nm的范围内,但也可以在此范围外。在一些实施例中,隔离特征件41的直径(D2)在约5nm至约20nm的范围内,但也可以在此范围外。在一些实施例中,导电特征件42被定义以包括阻障层391、衬垫层392和第二导电特征件393。在一些实施例中,导电特征件42的直径(D1)可在约10nm至约100nm的范围,但也可以在此范围外。在其他实施例中,导电特征件42的直径(D1)可在约3nm至约20nm的范围,但也可以在此范围外。在一些实施例中,导电特征件42的高度(H1)可在约20nm至约100nm的范围,但也可以在此范围外。在一些实施例中,导电特征件42的深宽比,其由导电特征件42的高度(H1)除以导电特征件42的直径(D1)所定义,可以在约0.5至约5的范围内,但也可以在此范围外。在其他实施例中,导电特征件42的深宽比可以在约1至约10的范围,但也可以在此范围外。在一些实施例中,第二导电特征件393具有外壁394,其与相应晶体管301(见图6)的MD结构302形成夹角(A),且夹角(A)的范围可为约72度至约90度。在一些实施例中,通孔38(见图14A)由孔洞定义壁50来界定,其由第一导电特征件341、黏着层342、第二介电层332、第三介电层333及对应晶体管301的MD结构302共同界定。阻障层391是保形地形成在孔洞定义壁50上。在一些实施例中,孔洞定义壁50与对应晶体管301的MD结构302形成夹角(B),且夹角(B)的范围从约72度至约90度,使得形成于由孔洞定义壁50所界定的通孔38中的第二导电特征件393具有与对应晶体管301的MD结构302形成72度至90度夹角(A)的外壁394。
参考图18,在一些实施例中,导电特征件42具有连接至晶体管301的MD结构302的底表面422,以及与底表面422相对的顶表面421,并且与第一导电特征件341的相应的导电组件341'的顶表面实质上齐平,导电特征件42穿透此顶表面。在一些实施例中,导电特征件42的顶表面421具有占第一导电特征件341的导电组件341'的对应一者的顶表面面积约20%至约100%的面积。图18显示在一些实施例中,导电特征件42的顶表面421的面积占第一导电特征件341的导电组件341'的对应一者的顶表面的面积100%。换句话说,导电特征件42的最大直径(D1)等于与导电特征件42相邻的两个隔离特征件41之间的最小距离(S)。在一些实施例中,对于导电特征件42,顶表面421的面积可以等于或大于底表面422的面积。
图19至图21示意性地显示气隙361的不同范例。在一些实施例中,在一个通孔343'中(见图10A),气隙361的体积为通孔343'的体积的约20%至约90%,且第四介电层36的体积为通孔343'的体积的约10%至约80%。参考图19,在一些实施例中,在第四介电层36的形成期间,第四介电层36的顶部部分363可以在通孔343'被第四介电层36完全填充之前密封通孔343',借此在通孔343'内留下气隙361。
参考图20,在一些实施例中,合适的蚀刻停止层60是形成在通孔343'(见图10A)的底部。在此等实施例中,在形成第四介电层36之前,在通孔343'的底部上形成蚀刻停止层60,接着通过热可降解的或UV可降解的材料(未绘示)填充通孔343'以形成可降解的元件。热或UV可降解的材料可由含聚脲材料、含丙烯酸酯材料、含羧酸盐材料或类似者制成。可以合适的技术形成热或紫外光可降解的材料,例如ALD(包含PEALD)、CVD(例如FCVD、LPCVD、PECVD或类似者)、分子层沉积(MLD)、旋转涂布或类似者。接着,蚀刻可降解的元件(例如,使用非等向性干式蚀刻)直到蚀刻停止层60,以在可降解的元件中形成一中空空间(未绘示),接着用第四介电层36填充该中空空间。最后,通过热处理或UV辐射移除热可降解的或UV可降解的材料的剩余部分以形成气隙361。在一些实施例中,可在约200℃至约400℃范围内的温度下进行热处理约10秒至约10分钟。在一些实施例中,可在自约10mJ/cm2至约100J/cm2的范围内的辐射能下进行UV辐射约10秒至约10分钟。
参考图21,在一些实施例中,热可降解的或UV可降解的材料形成于通孔343'(见图10A)的底部部分处,接着用第四介电层36完全填充通孔343'。随后,通过合适的热处理或UV辐射移除热可降解的或UV可降解的材料以形成气隙361。
在一些实施例中,隔离特征件41可能不包含气隙361。请参考图22,在一些实施例中,第四介电层36可包含第一子层364和第二子层365。在一些实施例中,首先在通孔343'(见图10A)中形成第一子层364,之后形成第二子层365以完全填充通孔343'。
参考图23,在一些实施例中,蚀刻停止层60形成于通孔343'(见图10A)的底部处。之后,形成第一子层364以填充通孔343',之后蚀刻(例如,使用非等向性干式蚀刻)第一子层364直至蚀刻停止层60而于第一子层364内形成中空空间(未绘示)。接着,中空空间被第二子层365填充。
依据实际需求,第一子层364和第二子层365可由不同的电介质材料构成。在一些实施例中,第一子层364的材料可更佳地黏着至阻障/衬垫层37或第一导电特征件341。在一些实施例中,第二子层365可由低介电常数电介质材料制成。在一些实施例中,第一子层364的组成可为掺杂氮化物的碳化硅,而第二子层365的组成可为氧化硅、氮化硅、碳化硅(包含UDC、ODC、NDC、或类似者)、氮氧化硅、碳氧化硅(包括silicon carbide nitride,SiOCH)、碳氧化硅的氮化物、氧化铝、氮氧化铝、氮化铝、氧化锆、氮氧化铝锆(zirconium aluminumoxynitride)、非晶硅、或其等的组合。
本揭露的实施例具有一些有利特征。通过形成穿透第一导电特征件并电连接至第一导电特征件和下方半导体器件的第二导电特征件,第二导电特征件可以取代第一导电特征件和半导体器件之间的接触插塞,借此消除接触插塞和第一导电特征件之间的界面,以降低第一导电特征件和半导体器件之间的电阻。第二导电特征件可形成为长形轨道结构,其可取代多个接触插塞且简化整体制造制程。第二导电特征件可形成为用于第一导电特征件与半导体器件之间的电连接的接触件;另一方面,第二导电特征件可为深电源轨,其提供足够的电力至半导体器件,可改善因为导电线路尺寸缩减而供电不足所造成的电压降低问题。第二导电特征件可由基于第一导电特征件材料所选择的材料制成,并且根据实际需求,例如超低电阻、低电容、可靠度或其他变化,其允许半导体结构依据实际需求而灵活地设计。半导体结构可与介电层的气隙或多个填入第一导电特征件通孔结构的子层整合,以降低半导体结构整体的介电常数。
根据一些实施例,一半导体结构包括一基板、一介电层、一第一导电特征件与一第二导电特征件。该基板包括一半导体器件。该介电层设置于该基板上。该第一导电特征件形成于该介电层中。该第二导电特征件穿透该第一导电特征件与该介电层,且电连接至该第一导电特征件与该半导体器件。
根据一些实施例,该第一导电特征件与该第二导电特征件由不同材料组成。
根据一些实施例,该第一导电特征件的组成材料包括铜、钌、钨、钛、铝、钴、钼、铱、铑、石墨烯、或其等的组合。该第二导电特征件由包括铜、钌、钨、钛、铝、钴、钼、铱、铑、钴-钨-磷(cobalt-tungsten-phosphorus)或其等的组合的材料制成。
根据一些实施例,该半导体结构更包括一衬垫层,其围绕并连接至该第二导电特征件;以及一阻障层,其围绕并连接至该衬垫层。该第二导电特征件通过该衬垫层和该阻障层连接至该第一导电特征件。
根据一些实施例,该阻障层及该衬垫层的各者是由导电材料所制成,包括钽、氮化钽、钴、钌、钛、氮化钛、氮化锰或其等的组合。
根据一些实施例,该第二导电特征件具有与该半导体器件形成夹角的一外壁。该夹角的范围从约72度到约90度。
根据一些实施例,该介电层具有邻近该第一导电特征件的一气隙。
根据一些实施例,一半导体结构包括一基板、一第一介电层、一互连结构与一第二导电特征件。基板包含一晶体管。该第一介电层设置于该基板上。该互连结构包括:一第一导电特征件,其设置于该第一介电层上并相反于该基板;以及一第二介电层,其围绕该第一导电特征件。该第二导电特征件穿透该互连结构,且电连接至该第一导电特征件与该晶体管。
根据一些实施例,该半导体结构更包括一黏着层与一衬垫层/阻障层。该黏着层设置于该第一介电层与该第一导电特征件之间,且延伸于大致平行该基板的方向。衬垫层/阻障层为连接并围绕第二导电特征件。
根据一些实施例,该第一导电特征件包括多个导电组件,其通过该第二介电层彼此隔开。
根据一些实施例,该第一导电特征件的一底表面连接至该第一介电层。该第二导电特征件的一底表面连接至该晶体管的一接触件,并且低于该第一导电特征件的底表面。
根据一些实施例,该第二导电特征件的底表面低于该晶体管的一顶表面。
根据一些实施例,该第二导电特征件电连接至该晶体管的多个接触件。
根据一些实施例,一种半导体结构的制造方法包含:提供一基板,其包含一半导体器件;在该基板上形成一介电层;在该介电层中形成一第一导电特征件,该第一导体特征件与该基板分开;形成一通孔,其穿透该第一导电特征件及该介电层以暴露出该半导体器件的一接触件;以及在该通孔中形成一第二导电特征件,使该第二导电特征件电连接至该半导体器件的该第一导电特征件及该接触件。
根据一些实施例,该第一导电特征件与该第二导电特征件由不同材料组成。
根据一些实施例,该第一导电特征件的组成材料包括铜、钌、钨、钛、铝、钴、钼、铱、铑、钴-钨-磷或其等的组合。该第二导电特征件由包括铜、钌、钨、钛、铝、钴、钼、铱、铑、钴-镍-磷(cobalt-tungsten-phosphorus)或其等的组合的材料制成。
根据一些实施例,该通孔由一孔洞定义壁界定。该方法更包括:在形成该通孔之后且在形成该第二导电特征件之前,在该孔洞定义壁上保形地形成一导电阻障层,并且在该阻障层上保形地形成一导电衬垫层;以及在形成该第二导电特征件之后,该第二导电特征件被衬垫层围绕且连接该衬垫层。
根据一些实施例,形成该通孔的步骤是通过使用一光阻作为一掩模以蚀刻穿过该第一导电特征件及该介电层而进行。
根据一些实施例,在形成该通孔的步骤中,该通孔是由与该半导体器件形成一夹角的一孔洞定义壁所界定。该夹角是在从约72度至约90度的范围内,以使填充该通孔的该第二导电特征件具有与该半导体器件形成另一夹角的一外壁。该外壁与该半导体器件之间的另一夹角的范围是自约72度至约90度。
根据一些实施例,在形成通孔的步骤中,部分地移除半导体器件的接触件。
上文概述若干实施例的特征,使得本领域技术人员可更好地理解本揭露的态样。本领域技术人员应当理解,他们可轻易地以本揭露内容为基础设计或修改以用于执行与本文介绍的实施例具有相同目的及/或实现相同优点的其它制程及结构。本领域技术人员也应理解到,此类等效的制程和结构并无悖离本发明的精神与范围,且他们能在不违背本发明的精神和范围之下,做各式各样的改变、取代和替换。
Claims (1)
1.一种半导体结构,其特征在于,所述半导体结构包含:
基板,其包括半导体器件;
介电层,其被设置在所述基板上;
第一导电特征件,形成于所述介电层中;以及
第二导电特征件,穿过所述第一导电特征件及所述介电层,且电连接至所述第一导电特征件及所述半导体器件。
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