CN110545158B - Virtualization and self-adaptive communication system and communication method for multiple interfaces of optical digital tester - Google Patents
Virtualization and self-adaptive communication system and communication method for multiple interfaces of optical digital tester Download PDFInfo
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- CN110545158B CN110545158B CN201910663596.6A CN201910663596A CN110545158B CN 110545158 B CN110545158 B CN 110545158B CN 201910663596 A CN201910663596 A CN 201910663596A CN 110545158 B CN110545158 B CN 110545158B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
- H04L1/0015—Systems modifying transmission characteristics according to link quality, e.g. power backoff characterised by the adaptation strategy
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
- H04L1/0033—Systems modifying transmission characteristics according to link quality, e.g. power backoff arrangements specific to the transmitter
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
- H04L1/0001—Systems modifying transmission characteristics according to link quality, e.g. power backoff
- H04L1/0036—Systems modifying transmission characteristics according to link quality, e.g. power backoff arrangements specific to the receiver
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L67/00—Network arrangements or protocols for supporting network services or applications
- H04L67/50—Network services
- H04L67/56—Provisioning of proxy services
- H04L67/568—Storing data temporarily at an intermediate stage, e.g. caching
Abstract
The invention relates to a virtualization and self-adaptive communication system of multiple interfaces of an optical digital tester and a communication method thereof, wherein a communication data packet is established according to a communication model; sending the communication data packet to a receiving module; converting the communication data packet into bus time sequence sending data; the frame judging module judges the consistency of the target port number of the received bus time sequence sending data and the receiving port of the corresponding communication main body, if the consistency is consistent, the target port number is cached in the sending caching module, the sending source selecting module traverses each sending caching module, and the bus time sequence receiving data is sent to the de-framing module; and the sending module transmits the communication data packet converted by the de-framing module to a receiving port of the corresponding communication main body. The invention can complete reliable and high-bandwidth transmission of data by only filling simple target port number, source port number, data packet length, communication data segment and check field without deeply knowing channel establishment, maintenance and release.
Description
Technical Field
The invention relates to the field of digital overhaul and test of secondary equipment of an intelligent substation, in particular to a virtualization and self-adaptive communication method for multiple interfaces of an optical digital tester.
Background
With the rapid development of intelligent power grids in China, more and more digital transformer substations are provided, and a large number of test instruments are needed for detection and testing of secondary equipment in the transformer substations. These test and measurement instruments have evolved from single optical ethernet ports to numerous physical interfaces, such as SGMII (Serial Media-Independent Interface) Gigabit ethernet ports, MII (Medium-Independent Interface) Gigabit ethernet, FT3 interfaces, Analog to digital converter (dac) interfaces, and the like; not only the physical form is different, but also the number is expanded from 4, 8 to 16. In addition, other interfaces or buses are involved in communication inside the system, such as a upp (universal Parallel port) interface, PCIE, SRIO (Serial RapidIO), and the like.
Currently, address addressing-based single-master multi-slave buses, such as axi (advanced Extensible interface) bus of ARM company, Avalon bus of Intel company, etc., are applied to systems, and such buses have the advantages of convenient design, uniform addressing, convenient management, etc. But the disadvantages are more prominent, for example, the interfaces connected to the bus must transmit data under the unified scheduling control of the central processing unit or the controller, which results in more time consumption of the processor; in the unified addressing mode, under the condition of more external devices or interfaces, the bit width of an address bus is large, and the combination logic chain for realizing addressing is too large to cause the system clock to be incapable of being promoted, thereby further causing the bandwidth to be reduced; in addition, the physical form, bandwidth, delay and other differences of the interfaces are large, so that the complexity of the system is increased.
Disclosure of Invention
In view of the above, an object of the present invention is to provide a virtualization and adaptive communication method for multiple interfaces of an optical digital tester, which can complete reliable and high-bandwidth data transmission by filling simple destination port number, source port number, packet length, communication data segment and check field without deep knowledge of channel establishment, maintenance and release.
The invention is realized by adopting the following scheme: a virtualization and self-adaptive communication system of multiple interfaces of an optical digital tester comprises an interface adaptation module, a sending bus, a receiving bus, a frame discrimination module and a sending cache module;
the interface adaptation module comprises a receiving module, a framing module, a deframing module and a sending module; the input end of the receiving module is connected with the corresponding sending port of the communication main body, the output end of the receiving module is connected with the input end of the framing module, and the output end of the framing module is connected with each frame judgment module through the corresponding sending bus; the input end of the deframing module is connected with the corresponding receiving bus, the output end of the deframing module is connected with the input end of the sending module, and the output end of the sending module is connected with the receiving port of the corresponding communication main body;
the output end of the frame distinguishing module is connected with the input end of the corresponding sending buffering module, the output end of the sending buffering module is connected with the input end corresponding to the sending source selecting module, and the input end of the de-framing module of each interface adapting module is respectively connected with the output end of the corresponding sending source selecting module;
the transmission source selection module, each frame discrimination module and each transmission cache module form a virtual and self-adaptive communication interconnection module, and the virtual and self-adaptive communication interconnection module and the interface adaptation module can be realized through an FPGA.
The invention also provides a communication method of the virtualization and self-adaptive communication system of the multiple interfaces of the optical digital tester, which specifically comprises the following steps:
step S1: each communication main body establishes a communication model, the communication model comprises a head field, a communication data section and a check field, and the head field comprises a target port number, a source port number and a data packet length;
step S2: establishing a communication data packet by any communication main body according to a communication model;
step S3: the communication main body sends the communication data packet to a receiving module of an interface adaptation module corresponding to the communication main body through a sending port, and the receiving module caches the received communication data packet;
step S4: the framing module converts the communication data packet stored in the receiving module into bus time sequence sending data;
step S5: the bus time sequence sending data is transmitted to each frame judging module through the corresponding sending bus, the frame judging module judges whether the target port number of the received bus time sequence sending data is consistent with the receiving port of the communication main body corresponding to the frame judging module, if so, the bus time sequence sending data is converted into sending cache data to be cached in the sending cache module, and the step S6 is carried out; if the bus time sequence is inconsistent with the current bus time sequence, discarding the current bus time sequence sending data;
step S6: the transmission source selection module sequentially traverses each transmission buffer module, judges whether transmission buffer data are buffered in the transmission buffer module, converts the transmission buffer data into bus time sequence receiving data if the transmission buffer data are buffered, transmits the bus time sequence receiving data to a frame decoding module of a corresponding interface adaptation module through a corresponding receiving bus, and goes to step S7;
step S7: the frame decoding module converts bus time sequence receiving data into a communication data packet;
step S8: and the sending module transmits the communication data packet converted by the de-framing module to a receiving port of the corresponding communication main body.
Further, step S4 is specifically: the framing module checks the communication data packet in the receiving module in real time, initiates reading of a frame of communication data packet when a frame of complete communication data packet is found to be stored in the receiving module, and converts the communication data packet into bus time sequence sending data.
Further, the bus timing transmission data in step S4 and the bus timing reception data in step S6 each include, transmitted in parallel: a communication bus clock, a receive end ready signal, a frame data start signal, a frame data end signal, a frame data valid signal, a data bit signal, a destination port signal, a source port signal, and a frame length signal.
Further, in each transmission cycle:
for the receive-end ready signal: the first clock and the second clock of the communication bus clock are both high level; the third clock of the self-communication bus clock is always at a low level;
for the frame data start signal: a first clock of the communication bus clock is at a low level; the second clock of the communication bus clock is high level; continuing to be at a low level from a third clock of the communication bus clock;
for the frame end signal: the first clock to the second last clock of the communication bus clock are always in low level; the last clock of the communication bus clock is high level;
for a frame data valid signal: a first clock of the communication bus clock is at a low level; from the second clock of the communication bus clock, the effective signal of the frame data is always high level;
for the data bit signal: at the second clock of the communication bus clock, a header field in the communication data packet is provided, wherein the header field comprises a target port number, a source port number and a data packet length; the data bit signals are communication data segments of communication data packets from the third clock to the last clock of the communication bus clock; at the last clock of the communication bus clock, the data bit signal is the check field of the communication data packet;
for the destination port signal: continuously setting the target port number in the communication data packet from the second clock to the last clock of the communication bus clock;
for source port signals: continuing to be the source port number in the communication data packet from the second clock to the last clock of the communication bus clock;
for the frame length signal, the second clock to the last clock of the communication bus clock lasts the length of the data bit signal.
Further, in step S5, the sending cache module includes a content cache module and a frame header cache module, the sending cache data includes valid cache data and a valid cache data length, the valid cache data includes a header field, a communication data segment, and a check field, and the valid cache data length is a length of valid cache data in the corresponding sending cache data; the effective cache data is stored in the content cache module, and the effective cache data length and the first address of the effective cache data in the content cache module are stored in the frame header cache module as frame header information.
Further, in step S6, traversing a transmission buffer module includes the following steps: the sending source selection module firstly checks whether the frame header information in the frame header caching module is empty, reads out a piece of frame header information from the frame header caching module firstly under the non-empty condition, determines the first address and the effective caching data length of effective caching data stored in the content caching module according to the frame header information, reads corresponding effective caching data in the content caching module according to the first address and the effective caching data length of the effective caching data stored in the content caching module, converts the effective caching data into bus time sequence receiving data, sends the bus time sequence receiving data to a corresponding frame decoding module of the interface adaptation module through a corresponding receiving bus, and deletes the frame header information.
Compared with the prior art, the invention has the following beneficial effects:
1. the invention adopts virtualization and self-adaptive communication method, so that programmers in application layers of the digital signal processor and the general processor can complete reliable and high-bandwidth transmission of data by filling simple target port number, source port number, data packet length, communication data segment and check field without deeply knowing channel establishment, maintenance and release.
2. The invention establishes, maintains and releases communication channels automatically and adaptively through the virtual and adaptive communication interconnection module and the interface adaptation module, and has the characteristics of simple design, easy configuration, easy expansion and the like.
3. The invention achieves higher system bandwidth capability (8000 Mbps theoretically) by receiving data in the bus time sequence and sending the time sequence of the data in the bus time sequence without longer address decoding logic.
Drawings
FIG. 1 is a schematic diagram of a communication structure according to the present invention;
FIG. 2 is a block diagram of a system of the present invention;
FIG. 3 is a parameter diagram of a communication model according to the present invention;
FIG. 4 is a schematic diagram of an interface adapter module according to the present invention;
FIG. 5 is a timing diagram of bus timing receive data and bus timing transmit data in accordance with the present invention;
FIG. 6 is a signal definition diagram of bus timing receive data and bus timing transmit data according to the present invention;
fig. 7 is a schematic connection diagram of the interface adaptation module and the virtual and adaptive communication interconnection module according to the present invention.
The numbers and n in fig. 4 and 7 are serial numbers, and do not represent numerical signs of the components.
Detailed Description
The invention is further explained below with reference to the drawings and the embodiments.
It should be noted that the following detailed description is exemplary and is intended to provide further explanation of the disclosure. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs.
It is noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of example embodiments according to the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, and it should be understood that when the terms "comprises" and/or "comprising" are used in this specification, they specify the presence of stated features, steps, operations, devices, components, and/or combinations thereof, unless the context clearly indicates otherwise.
As shown in fig. 1 to 7, the present embodiment provides a virtualization and adaptive communication system for multiple interfaces of an optical digital tester, which includes an interface adaptation module, a transmission bus, a reception bus, a frame determination module, and a transmission buffer module;
the interface adaptation module comprises a receiving module, a framing module, a deframing module and a sending module; the input end of the receiving module is connected with the corresponding sending port of the communication main body 1, the output end of the receiving module is connected with the input end of the framing module, and the output end of the framing module is connected with each frame judgment module through the corresponding sending bus; the input end of the deframing module is connected with the corresponding receiving bus, the output end of the deframing module is connected with the input end of the sending module, and the output end of the sending module is connected with the corresponding receiving port of the communication main body 1;
the output end of the frame distinguishing module is connected with the input end of the corresponding sending buffering module, the output end of the sending buffering module is connected with the input end corresponding to the sending source selecting module, and the input end of the de-framing module of each interface adapting module is respectively connected with the output end of the corresponding sending source selecting module;
the transmission source selection module, each frame discrimination module and each transmission cache module form a virtual and self-adaptive communication interconnection module, and the virtual and self-adaptive communication interconnection module and the interface adaptation module can be realized through an FPGA.
The embodiment further provides a communication method of the virtualization of the multiple interfaces of the optical digital tester and the adaptive communication system, which specifically includes the following steps:
step S1: each communication main body establishes a communication model, the communication model comprises a head field, a communication data section and a check field, and the head field comprises a target port number, a source port number and a data packet length; the check field is a CRC check code with the length of 4 bytes;
as shown in fig. 3, the purpose of establishing a communication model is to virtualize a communication subject with different physical forms (such as a signal, a bandwidth, and a delay difference) according to the communication model to obtain characteristic parameters that facilitate channel establishment.
Step S2: establishing a communication data packet by any communication main body according to a communication model; the first byte of the communication data packet is a target port number, the second byte is a source port number, the third byte and the fourth byte are communication data packet lengths, and the fourth byte is followed by a communication data segment and a check field in sequence.
Step S3: the communication main body sends the communication data packet to a receiving module of an interface adaptation module corresponding to the communication main body through a sending port according to a protocol or logic or time sequence corresponding to the sending port of the communication main body, and the receiving module caches the received communication data packet;
preferably, the receiving module comprises two RAMs with a bit width of 32 bits and a depth of 512 bits, respectively labeled as RAM-0 and RAM-1, for ping-pong storage of incoming communication data packets. The last communication data packet is stored in the RAM-0, and the next communication data packet is stored in the RAM-1, and the operation is carried out alternately in sequence.
The data format stored by the communication data packet is as follows: the first 32 bits are the header field of the communication model, where [7:0] stores the destination port, [15:8] stores the source port, and [31:16] stores the packet length, followed by the communication data segment and the check field in sequence.
Step S4: the framing module converts the communication data packet stored in the receiving module into bus time sequence sending data;
step S5: the bus time sequence sending data is transmitted to each frame judging module through the corresponding sending bus, the frame judging module judges whether the target port number of the received bus time sequence sending data is consistent with the receiving port of the communication main body corresponding to the frame judging module, if so, the bus time sequence sending data is converted into sending cache data to be cached in the sending cache module, and the step S6 is carried out; if the bus time sequence is inconsistent with the current bus time sequence, discarding the current bus time sequence sending data;
step S6: the transmission source selection module sequentially traverses each transmission buffer module, judges whether transmission buffer data are cached in the transmission buffer module, converts the transmission buffer data into bus time sequence receiving data if the transmission buffer data are cached, transmits the bus time sequence receiving data to a frame decoding module of a corresponding interface adaptation module through a corresponding receiving bus, and goes to step S7;
step S7: the frame decoding module converts bus time sequence receiving data into a communication data packet; the de-framing module stores the communication data packet in two RAM memories in a ping-pong storage mode.
Step S8: and the sending module transmits the communication data packet converted by the deframing module to the receiving port of the corresponding communication main body according to the protocol or logic or time sequence corresponding to the receiving port of the corresponding communication main body.
The sending module sends the communication data packets stored in the two RAM memories in the ping-pong storage form to the corresponding receiving port of the communication body according to the protocol or logic or time sequence corresponding to the receiving port of the communication body.
The sending port and the receiving port of the communication subject may be SGMII ports or SRIO ports or MII ports.
The communication main body can be a digital signal processor, a general processor, a hundred mega optical module, or a DDR2\ Flash memory, etc.
In this embodiment, step S4 specifically includes: the framing module checks the communication data packet in the receiving module in real time, initiates reading of a frame of communication data packet when a frame of complete communication data packet is found to be stored in the receiving module, and converts the communication data packet into bus time sequence sending data.
In the present embodiment, the bus timing transmission data in step S4 and the bus timing reception data in step S6 each include, transmitted in parallel: a communication bus clock, a receive end ready signal, a frame data start signal, a frame data end signal, a frame data valid signal, a data bit signal, a destination port signal, a source port signal, and a frame length signal.
The bus time sequence receiving data and the bus time sequence sending data comprise parallel transmission: a communication bus clock (frame _ bus _ clk), a receive side ready signal (frame _ bus _ trdy), a frame start signal (frame _ bus _ sof), an end signal (frame _ bus _ eof), a frame valid signal (frame _ bus _ dval), a data bit signal (frame _ bus _ data), a destination port signal (frame _ bus _ dport), a source port signal (frame _ bus _ sport), and a frame length signal (frame _ bus _ len);
in each transmission cycle:
for the receive-side ready signal (frame _ bus _ trdy): both the first clock and the second clock of the communication bus clock (frame _ bus _ clk) are high; the (frame _ bus _ clk) third clock from the communication bus clock is always low;
for the frame data start signal (frame _ bus _ sof): low at the first clock of the communication bus clock (frame _ bus _ clk); at the second clock of the communication bus clock (frame _ bus _ clk), high indicating that valid data in the data bit signal (frame _ bus _ data) begins to be transferred; low from the third clock of the communication bus clock (frame _ bus _ clk);
for frame end signal (frame _ bus _ eof): the first clock to the second last clock of the communication bus clock (frame _ bus _ clk) are always low; a high level at the last clock of the communication bus clock (frame _ bus _ clk) indicating that the valid data transfer in the data bit signal (frame _ bus _ data) is finished;
for a frame data valid signal (frame _ bus _ dval): at the first clock of the communication bus clock (frame _ bus _ clk), the communication bus clock is low, which indicates that the data bit signal (frame _ bus _ data) is transmitting valid data which is not formed by the communication data segment and the check field; from the second clock of the communication bus clock (frame _ bus _ clk), the frame data valid signal (frame _ bus _ dval) is always high, indicating that the current communication bus clock, and the data bit signal (frame _ bus _ data) carries valid data consisting of a header field, a communication data segment and a check field;
for the data bit signal (frame _ bus _ data), at the second clock of the communication bus clock (frame _ bus _ clk) is a header field in the communication data packet, the header field including a destination port number, a source port number, and a packet length; the data bit signal (frame _ bus _ data) is a communication data segment of the communication data packet from the third clock to the second last clock of the communication bus clock (frame _ bus _ clk); at the last clock of the communication bus clock (frame _ bus _ clk), the data bit signal (frame _ bus _ data) is a check field of the communication data packet;
for the target port signal (frame _ bus _ dport), continuing for the target port number in the communication packet at the second clock to the last clock of the communication bus clock (frame _ bus _ clk);
for the source port signal (frame _ bus _ sport), continuing for the source port number in the communication packet at the second clock to the last clock of the communication bus clock (frame _ bus _ clk);
for the frame length signal (frame _ bus _ len), the length of the data bit signal (frame _ bus _ data) continues from the second clock to the last clock of the communication bus clock (frame _ bus _ clk) (i.e. the sum of the length of the header field in the communication data packet, the length of the communication data section of the communication data packet, the length of the check field of the communication data packet).
The frequency of the communication bus clock (frame _ bus _ clk) is 100Mhz or 125 Mhz.
In this embodiment, in step S5, the bus timing transmission data is transmitted to each frame determination module through the corresponding transmission bus, and the frame determination module parses the target port signal (frame _ bus _ dport) or the data bit signal (frame _ bus _ data) transmitted by the second clock of the communication bus clock (frame _ bus _ clk) in each transmission cycle, obtains the target port number, and determines whether the target port number is consistent with the receiving port of the communication master corresponding to the frame determination module. If the bus time sequence sending data are consistent, the bus time sequence sending data are converted into sending cache data to be cached in a sending cache module, and if the bus time sequence sending data are inconsistent, the bus time sequence sending data are discarded.
The sending cache module comprises a content cache module and a frame header cache module, the sending cache data comprises effective cache data and effective cache data length, the effective cache data comprises a head field, a communication data section and a check field, and the effective cache data length is the length of the effective cache data in the corresponding sending cache data; the effective cache data is stored in the content cache module, and the effective cache data length and the first address of the effective cache data in the content cache module are stored in the frame header cache module as frame header information.
In this embodiment, in step S6, traversing a transmission buffer module includes the following steps: the sending source selection module firstly checks whether the frame header information in the frame header caching module is empty, reads out a piece of frame header information from the frame header caching module firstly under the non-empty condition, determines the first address and the effective caching data length of effective caching data stored in the content caching module according to the frame header information, reads corresponding effective caching data in the content caching module according to the first address and the effective caching data length of the effective caching data stored in the content caching module, converts the effective caching data into bus time sequence receiving data, sends the bus time sequence receiving data to a corresponding frame decoding module of the interface adaptation module through a corresponding receiving bus, and deletes the frame header information.
Particularly, in the embodiment, when any two communication entities communicate, other communication entities can also communicate freely without being limited by other communication entities; the problem that the system bandwidth is limited due to overlarge combinational logic chain caused by adopting an address addressing mode is also solved; and an upper-layer application person does not need to pay attention to specific physical layer information, only needs to pay attention to the content of the communication data packet, and is convenient for programming and using of an application layer.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The foregoing is directed to preferred embodiments of the present invention, other and further embodiments of the invention may be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow. However, any simple modification, equivalent change and modification of the above embodiments according to the technical essence of the present invention are within the protection scope of the technical solution of the present invention.
Claims (5)
1. A virtualization and self-adaptive communication system of multiple interfaces of an optical digital tester is characterized by comprising an interface adaptation module, a sending bus, a receiving bus, a frame judgment module and a sending buffer module;
the interface adaptation module comprises a receiving module, a framing module, a deframing module and a sending module; the input end of the receiving module is connected with the corresponding sending port of the communication main body, the output end of the receiving module is connected with the input end of the framing module, and the output end of the framing module is connected with each frame judgment module through the corresponding sending bus; the input end of the deframing module is connected with the corresponding receiving bus, the output end of the deframing module is connected with the input end of the sending module, and the output end of the sending module is connected with the receiving port of the corresponding communication main body;
the output end of the frame judgment module is connected with the input end of the corresponding sending buffer module, the output end of the sending buffer module is connected with the input end corresponding to the sending source selection module, and the input end of the de-framing module of each interface adaptation module is respectively connected with the output end of the corresponding sending source selection module;
the transmission source selection module, each frame judgment module and each transmission buffer module form a virtual and self-adaptive communication interconnection module, and the virtual and self-adaptive communication interconnection module and the interface adaptation module can be realized through an FPGA (field programmable gate array);
the communication method comprises the following steps:
step S1: each communication main body establishes a communication model, the communication model comprises a head field, a communication data section and a check field, and the head field comprises a target port number, a source port number and a data packet length;
step S2: establishing a communication data packet by any communication main body according to a communication model;
step S3: the communication main body sends the communication data packet to a receiving module of an interface adaptation module corresponding to the communication main body through a sending port, and the receiving module caches the received communication data packet;
step S4: the framing module converts the communication data packet stored in the receiving module into bus time sequence sending data;
step S5: the bus time sequence sending data is transmitted to each frame judging module through the corresponding sending bus, the frame judging module judges whether the target port number of the received bus time sequence sending data is consistent with the receiving port of the communication main body corresponding to the frame judging module, if so, the bus time sequence sending data is converted into sending cache data to be cached in the sending cache module, and the step S6 is carried out; if the bus time sequence is inconsistent with the current bus time sequence, discarding the current bus time sequence sending data;
step S6: the transmission source selection module sequentially traverses each transmission buffer module, judges whether transmission buffer data are cached in the transmission buffer module, converts the transmission buffer data into bus time sequence receiving data if the transmission buffer data are cached, transmits the bus time sequence receiving data to a frame decoding module of a corresponding interface adaptation module through a corresponding receiving bus, and goes to step S7;
step S7: the frame decoding module converts bus time sequence receiving data into a communication data packet;
step S8: the sending module transmits the communication data packet converted by the deframing module to a receiving port of a corresponding communication main body;
the bus timing transmission data in step S4 and the bus timing reception data in step S6 each include, transmitted in parallel: a communication bus clock, a receive end ready signal, a frame data start signal, a frame data end signal, a frame data valid signal, a data bit signal, a destination port signal, a source port signal, and a frame length signal.
2. The virtualization and adaptive communication system for multiple interfaces of an optical digital tester according to claim 1, wherein the step S4 is specifically: the framing module checks the communication data packet in the receiving module in real time, initiates reading of a frame of communication data packet when a frame of complete communication data packet is found to be stored in the receiving module, and converts the communication data packet into bus time sequence sending data.
3. The virtualization and adaptation communication system for multiple interfaces of an optical digital tester according to claim 1, wherein in each transmission cycle:
for the receive-end ready signal: the first clock and the second clock of the communication bus clock are both high level; the third clock of the self-communication bus clock is always at a low level;
for the frame data start signal: a first clock of the communication bus clock is at a low level; the second clock of the communication bus clock is high level; continuing to be at a low level from a third clock of the communication bus clock;
for the frame end signal: the first clock to the last clock of the communication bus clock are always in low level; the last clock of the communication bus clock is high level;
for a frame data valid signal: a first clock of the communication bus clock is at a low level; from the second clock of the communication bus clock, the effective signal of the frame data is always high level;
for the data bit signal: at the second clock of the communication bus clock, a header field in the communication data packet is provided, wherein the header field comprises a target port number, a source port number and a data packet length; the data bit signals are communication data segments of communication data packets from the third clock to the last clock of the communication bus clock; at the last clock of the communication bus clock, the data bit signal is the check field of the communication data packet;
for the destination port signal: continuously setting the target port number in the communication data packet from the second clock to the last clock of the communication bus clock;
for source port signals: continuing to be the source port number in the communication data packet from the second clock to the last clock of the communication bus clock;
for the frame length signal: the second clock to the last clock of the communication bus clock lasts the length of the data bit signal.
4. The virtualization and adaptive communication system for multiple interfaces of an optical digital tester as claimed in claim 1, wherein in step S5, the sending buffer module includes a content buffer module and a frame header buffer module, the sending buffer data includes valid buffer data and a valid buffer data length, the valid buffer data includes a header field, a communication data segment, and a check field, and the valid buffer data length is the length of the valid buffer data in the corresponding sending buffer data; the effective cache data is stored in the content cache module, and the effective cache data length and the first address of the effective cache data in the content cache module are stored in the frame header cache module as frame header information.
5. The virtualization and adaptation communication system for multiple interfaces of an optical digital tester as claimed in claim 4, wherein the step S6 of traversing a transmission buffer module comprises the steps of: the sending source selection module firstly checks whether the frame header information in the frame header caching module is empty, reads out a piece of frame header information from the frame header caching module firstly under the non-empty condition, determines the first address and the effective caching data length of effective caching data stored in the content caching module according to the frame header information, reads corresponding effective caching data in the content caching module according to the first address and the effective caching data length of the effective caching data stored in the content caching module, converts the effective caching data into bus time sequence receiving data, sends the bus time sequence receiving data to a corresponding frame decoding module of the interface adaptation module through a corresponding receiving bus, and deletes the frame header information.
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