CN110545034A - Drive circuit and air conditioner - Google Patents
Drive circuit and air conditioner Download PDFInfo
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- CN110545034A CN110545034A CN201910830034.6A CN201910830034A CN110545034A CN 110545034 A CN110545034 A CN 110545034A CN 201910830034 A CN201910830034 A CN 201910830034A CN 110545034 A CN110545034 A CN 110545034A
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- level inverter
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/38—Means for preventing simultaneous conduction of switches
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Abstract
The invention discloses a driving circuit and an air conditioner, wherein the driving circuit comprises a direct-current power supply input end, a first control end, a second control end, an H-bridge switching circuit, a first level inverter circuit and a second level inverter circuit, wherein an upper bridge arm switch in the H-bridge switching circuit is a PMOS (P-channel metal oxide semiconductor) tube, a lower bridge arm switch in the H-bridge switching circuit is an NMOS (N-channel metal oxide semiconductor) tube, one bridge arm switch in the diagonal upper bridge arm switch and lower bridge arm switch is connected with one level inverter circuit and the other bridge arm switch and is simultaneously connected to the control ends, so that the simultaneous conduction and the simultaneous turn-off are realized, the staggered conduction and the turn-off of the upper bridge arm switch and the lower bridge arm switch in the same bridge arm switching circuit are avoided, the. Meanwhile, the MOS tube is adopted for driving, and the rapidity of the H-bridge switching circuit is higher, so that the driving circuit can be used for controlling various tight moving parts, such as a motor, and can also be used for driving a direct-current four-way valve, and the application range is wide.
Description
Technical Field
The invention relates to the technical field of air conditioners, in particular to a driving circuit and an air conditioner.
background
at present, most of the drives of loads (such as a motor, a direct-current four-way valve and the like) in an air conditioner are driven by an H-bridge drive circuit, four switching tubes in the H-bridge circuit need to be provided with four control signals, the control signals are more, the logic is complex, or a special drive chip is adopted to realize the dead time of switching on and off an upper tube or a lower tube, the cost of the drive chip is higher, and the circuit design of a control panel is complex easily caused.
As shown in fig. 1, fig. 1 is a schematic diagram of a conventional driving circuit, a Drive1 and a Drive2 respectively receive high and low levels to respectively control transistors Q5 and Q6 to be alternately turned on, so as to control MOS transistors Q1 and Q4 of an H-bridge switching circuit to be simultaneously turned on, MOS transistors Q2 and Q3 to be simultaneously turned on, and Q1 and Q3 to be alternately turned on, thereby implementing forward and reverse driving of the driving circuit.
however, this circuit has a shoot-through problem, specifically, the turn-on voltage of Q3 is 0.5V to 1.5V, the turn-on voltage of Q4 is-1.0V to-2.5V, and if the voltage of Q5 changes from 0 to 11.5V, it is inevitable to pass through a section (1.5V to 9V) in which both Q3 and Q4 are turned on. Because Q3 and Q4 are through in a short time, the current flowing through the MOS tube is large, the MOS tube is easy to damage, and the safety is low.
Disclosure of Invention
the main objective of the present invention is to provide a driving circuit, which aims to simplify the structure of the driving circuit and solve the problem of the drive circuit through.
in order to achieve the above object, the present invention provides the driving circuit comprising:
A DC power input terminal for inputting a DC power;
A first control terminal for inputting a first level signal;
A second control terminal for inputting a second level signal inverted from the first level signal;
The H-bridge switching circuit comprises a first bridge arm switching circuit and a second bridge arm switching circuit;
the controlled end of one of the upper bridge arm switch of the first bridge arm switch circuit and the lower bridge arm switch of the second bridge arm switch circuit is connected with the first control end, and the controlled end of the other bridge arm switch is connected with the first control end through a first level inverter circuit;
The controlled end of one of the upper bridge arm switch of the second bridge arm switch circuit and the lower bridge arm switch of the first bridge arm switch circuit is connected with the second control end, and the controlled end of the other bridge arm switch is connected with the second control end through a second level inverter circuit;
when the first level signal is received, an upper bridge arm switch of the first bridge arm switch circuit and a lower bridge arm switch of the second bridge arm switch circuit work, and a first polarity voltage signal is output to drive a load after the direct-current power supply is connected; and the number of the first and second groups,
when the second level signal is received, the lower bridge arm switch of the first bridge arm switch circuit and the upper bridge arm switch of the second bridge arm switch circuit work, and after the direct-current power supply is connected, a second polarity voltage signal with the polarity opposite to that of the first polarity voltage signal is output to drive a load to work;
The upper bridge arm switch of the first bridge arm switch circuit and the lower bridge arm switch of the second bridge arm switch circuit are PMOS tubes, and the lower bridge arm switch of the first bridge arm switch circuit and the lower bridge arm switch of the second bridge arm switch circuit are NMOS tubes.
in one embodiment, the driving circuit further includes:
the drive circuit further includes:
The first OC gate circuit is connected to the controlled end of the upper bridge arm switch of the first bridge arm switch circuit, and is used for performing level inversion output on a level signal input to the upper bridge arm switch of the first bridge arm switch circuit and pulling up the potential of the controlled end of the upper bridge arm switch of the first bridge arm switch circuit when in work;
The second OC gate circuit is connected to the controlled end of the upper bridge arm switch of the second bridge arm switch circuit, and is used for performing level inversion output on a level signal input to the upper bridge arm switch of the second bridge arm switch circuit and pulling up the potential of the controlled end of the upper bridge arm switch of the second bridge arm switch circuit when the second OC gate circuit works;
the third OC gate circuit is connected to the controlled end of the lower bridge arm switch of the first bridge arm switch circuit, and is used for performing level inversion output on a level signal input to the lower bridge arm switch of the first bridge arm switch circuit and pulling down the potential of the controlled end of the lower bridge arm switch of the first bridge arm switch circuit when the bridge is in work;
and the fourth OC gate circuit is connected to the controlled end of the lower bridge arm switch of the second bridge arm switch circuit, and is used for performing level inversion output on the level signal input to the lower bridge arm switch of the second bridge arm switch circuit and pulling down the potential of the controlled end of the lower bridge arm switch of the second bridge arm switch circuit when the second OC gate circuit works.
in an embodiment, an input end of the first level inverter circuit is connected to the first control end, an output end of the first level inverter circuit is connected to an input end of the first OC gate circuit, an output end of the first OC gate circuit is connected to a controlled end of an upper arm switch of the first arm switch circuit, an input end of the fourth OC gate circuit is connected to the first control end or an output end of the first OC gate circuit, and an output end of the fourth OC gate circuit is connected to a controlled end of a lower arm switch of the second arm switch circuit;
The input end of the second level inverter circuit is connected with the second control end, the output end of the second level inverter circuit is connected with the input end of the second OC gate circuit, the output end of the second OC gate circuit is connected with the controlled end of the upper bridge arm switch of the second bridge arm switch circuit, the input end of the third OC gate circuit is connected with the second control end or the output end of the second OC gate circuit, and the output end of the third OC gate circuit is connected with the controlled end of the lower bridge arm switch of the first bridge arm switch circuit.
in one embodiment, the first level inverter circuit and the second level inverter circuit each include a first resistor, a second resistor, a third resistor, a first PNP triode, and a first operating power input terminal;
the first end of the first resistor is the input end of the first level inverter circuit or the second level inverter circuit, the second end of the first resistor, the first end of the second resistor and the base electrode of the first PNP triode are interconnected, the emitter electrode of the first PNP triode, the second end of the second resistor and the input end of the first working voltage source are connected, the collector electrode of the first PNP triode is connected with the second end of the third resistor, the connecting node is the output end of the first level inverter circuit or the second level inverter circuit, and the second end of the third resistor is grounded.
In an embodiment, an input end of the first level inverter circuit is connected to the first control end, an output end of the first level inverter circuit is connected to an input end of the fourth OC gate circuit, an output end of the fourth OC gate circuit is connected to a controlled end of the upper arm switch of the second arm switch circuit, an input end of the first OC gate circuit is connected to the first control end or an output end of the fourth OC gate circuit, and an output end of the first OC gate circuit is connected to a controlled end of the upper arm switch of the first arm switch circuit;
the input end of the second level inverter circuit is connected with the second control end, the output end of the second level inverter circuit is connected with the input end of the third OC gate circuit, the output end of the third OC gate circuit is connected with the controlled end of the lower bridge arm switch of the first bridge arm switch circuit, the input end of the second OC gate circuit is connected with the second control end or the output end of the third OC gate circuit, and the output end of the second OC gate circuit is connected with the controlled end of the upper bridge arm switch of the second bridge arm switch circuit.
In an embodiment, each of the first level inverter circuit and the second level inverter circuit includes a fourth resistor, a fifth resistor, a sixth resistor, a first NPN transistor, and a first operating voltage input terminal;
The first end of the fourth resistor is the input end of the first level inverter circuit or the second level inverter circuit, the second end of the fourth resistor, the first end of the fifth resistor and the base of the first NPN triode are connected, the second end of the fifth resistor and the emitter of the first NPN triode are both grounded, the collector of the first NPN triode is connected with the first end of the sixth resistor, and the second end of the sixth resistor is connected with the first working voltage input end.
in an embodiment, each of the first OC gate circuit and the second OC gate circuit includes a seventh resistor, an eighth resistor, a ninth resistor, a second PNP triode, and a first working voltage input terminal;
the first end of the seventh resistor is the input end of the first level inverter circuit or the second level inverter circuit, the second end of the seventh resistor, the first end of the eighth resistor and the base of the second PNP triode are interconnected, the emitter of the second PNP triode, the second end of the eighth resistor and the input end of the first working voltage source are connected, the collector of the second PNP triode is connected with the second end of the ninth resistor, the connection node is the output end of the first level inverter circuit or the second level inverter circuit, and the second end of the ninth resistor is grounded.
In one embodiment, each of the third OC gate circuit and the fourth OC gate circuit includes a tenth resistor, an eleventh resistor, a twelfth resistor, a second NPN transistor, and a first operating voltage input terminal;
The first end of the tenth resistor is an input end of the first level inverter circuit or the second level inverter circuit, the second end of the tenth resistor, the first end of the eleventh resistor and the base of the second NPN triode are connected, the second end of the eleventh resistor and the emitter of the second NPN triode are both grounded, the collector of the second NPN triode is connected with the first end of the twelfth resistor, and the second end of the twelfth resistor is connected with the first working voltage input end.
The invention also provides an air conditioner which comprises a load and the driving circuit, wherein the power supply end of the load is connected with the power supply output end of the driving circuit.
in one embodiment, the load comprises a dc four-way valve or a motor.
the technical scheme of the invention adopts a direct-current power supply input end, a first control end, a second control end, an H-bridge switch circuit, a first level inverter circuit and a second level inverter circuit to form a drive circuit which can be used for driving a load in an air conditioner, wherein an upper bridge arm switch in the H-bridge switch circuit is a PMOS tube, a lower bridge arm switch in the H-bridge switch circuit is an NMOS tube, one bridge arm switch in the diagonal upper bridge arm switch and the diagonal lower bridge arm switch is connected with the level inverter circuit and the other bridge arm switch and is simultaneously connected to the control end, so that the simultaneous conduction and the simultaneous turn-off are realized, the staggered conduction and the turn-off of the upper bridge arm switch and the lower bridge arm switch in the same bridge arm switch circuit are avoided, the structure of the drive circuit is simplified, and the. Meanwhile, the MOS tube is adopted for driving, and the rapidity of the H-bridge switching circuit is higher, so that the driving circuit can be used for controlling various tight moving parts, such as a motor, and can also be used for driving a direct-current four-way valve, and the application range is wide.
drawings
in order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.
FIG. 1 is a schematic diagram of a conventional driving circuit;
FIG. 2 is a block diagram of a driving circuit according to a first embodiment of the present invention;
FIG. 3 is a block diagram of a driving circuit according to a second embodiment of the present invention;
FIG. 4 is a block diagram of a driving circuit according to a third embodiment of the present invention;
FIG. 5 is a block diagram of a driving circuit according to a fourth embodiment of the present invention;
FIG. 6 is a block diagram of a fifth embodiment of the driving circuit of the present invention;
FIG. 7 is a block diagram of a driving circuit according to a sixth embodiment of the present invention;
FIG. 8 is a circuit diagram of a driving circuit according to a first embodiment of the present invention;
FIG. 9 is a circuit diagram of a driving circuit according to a second embodiment of the present invention;
FIG. 10 is a circuit diagram of a driving circuit according to a third embodiment of the present invention;
Fig. 11 is a circuit structure diagram of a driving circuit according to a fourth embodiment of the invention.
The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.
it should be noted that the descriptions relating to "first", "second", etc. in the present invention are for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In addition, the meaning of "and/or" appearing throughout is: three parallel schemes are included, taking 'A/B' as an example, and the scheme comprises a scheme, or a scheme B, or a scheme which is satisfied by both A and B.
The invention provides a driving circuit.
As shown in fig. 2 and 3, the driving circuit of the present invention includes:
a dc power input terminal (not shown) for inputting dc power;
A first control terminal Drive1 for inputting a first level signal;
a second control terminal Drive2 for inputting a second level signal inverted with respect to the first level signal;
An H-bridge switching circuit 10 including a first bridge arm switching circuit 11 and a second bridge arm switching circuit 12;
the controlled end of one of the upper arm switch of the first arm switch circuit 11 and the lower arm switch of the second arm switch circuit 12 is connected with a first control end Drive1, and the controlled end of the other arm switch is connected with a first control end Drive1 through a first level inverter circuit 20;
The controlled end of one of the upper arm switch of the second arm switch circuit 12 and the lower arm switch of the first arm switch circuit 11 is connected with a second control end Drive2, and the controlled end of the other arm switch is connected with a second control end Drive2 through a second level inverter circuit 30;
When receiving the first level signal, the upper bridge arm switch of the first bridge arm switch circuit 11 and the lower bridge arm switch of the second bridge arm switch circuit 12 work, and output a first polarity voltage signal to drive a load after being connected to a direct current power supply; and the number of the first and second groups,
when receiving the second level signal, the lower bridge arm switch of the first bridge arm switch circuit 11 and the upper bridge arm switch of the second bridge arm switch circuit 12 work, and output a second polarity voltage signal with the polarity opposite to that of the first polarity voltage signal after being connected to the direct-current power supply to drive the load to work;
The upper arm switches of the first arm switch circuit 11 and the lower arm switches of the second arm switch circuit 12 are PMOS transistors, and the lower arm switches of the first arm switch circuit 11 and the lower arm switches of the second arm switch circuit 12 are NMOS transistors.
In this embodiment, the driving circuit may further include a load connection terminal J1, the load connection terminal J1 is used for connecting a load, a current of the driving circuit flows out from one of two terminals of the load connection terminal J1 to the load and flows in from the load through the other terminal, specifically, two ends of the load connection terminal J1 are connected to a power supply terminal of the load, a common end of the upper arm switch and the lower arm switch in the first arm switch circuit 11 is connected to one end of the load connection terminal J1, and a common end of the upper arm switch and the lower arm switch in the second arm switch circuit 12 is connected to the other end of the load connection terminal J1. The upper arm switch of the first arm switch circuit 11 and the upper arm switch of the second arm switch circuit 12 are connected to the input end of the dc power supply, and the lower arm switch of the first arm switch circuit 11 and the lower arm switch of the second arm switch circuit 12 are grounded, that is, the first arm switch circuit 11 and the second arm switch circuit 12 connect the load to the input end of the dc power supply and the ground through the load connection end J1, so that the connected dc power supply is output to the load through the load connection end J1, and the load is driven to operate.
The load can be a motor in an air conditioner or a direct current four-way valve, the driving circuit can output a first polarity voltage signal and a second polarity voltage signal to the load, the polarities of the first polarity voltage signal and the second polarity voltage signal are opposite, so that the working state of the load is switched and controlled, for example, the direction of direct current power supply current flowing through the direct current four-way valve is controlled by controlling the conduction of different bridge arm switches of the H-bridge circuit, so that the direct current four-way valve is opened to a corresponding refrigeration, dehumidification or heating mode, and then the bridge arm switch of the H-bridge switching circuit 10 can be turned off, so that a direct current driving power supply provided for the direct current four-way valve is turned off, the self-holding of the state of the direct current four-way valve is realized. And the direct current power supply can be converted into the alternating current power supply by controlling the conduction of different bridge arm switches of the H-bridge switching circuit 10 so as to drive the motor to operate.
In some embodiments, the driving circuit is disposed on an electric control board of an outdoor unit of an air conditioner, the electric control board is further provided with a main control chip for controlling a compressor, a fan, and other devices in the outdoor unit of the air conditioner to work, the first control end Drive1 and the second control end Drive2 of the embodiment are used for receiving a control signal output by the main control chip, and level signals output by the main control chip to the first control end Drive1 and the second control end Drive2 are a high level signal and a low level signal with opposite polarities.
Meanwhile, the upper arm switches in the first arm switch circuit 11 and the upper arm switches in the second upper arm switch circuit are both PMOS transistors, the lower arm switches in the first arm switch circuit 11 and the lower arm switches in the second upper arm switch circuit are both NMOS transistors, the upper arm switches are turned on at a low level and turned off at a high level, the lower arm switches are turned on at a high level and turned off at a low level, meanwhile, a voltage-dividing resistor, such as a resistor RS1, a resistor RS4, a resistor RS6 and a resistor RS8, is connected between the gate and the source of each MOS transistor, and a current-limiting resistor, such as a resistor RS2, a resistor RS3, a resistor RS5 and a resistor RS7, is also connected in series at the front end of the source of each MOS transistor.
In order to avoid the direct connection problem, in the embodiment, the controlled ends of the bridge arm switches in the same bridge arm switch circuit are separately arranged, and the diagonal bridge arm switches are connected with the same control end to realize diagonal conduction, that is, one of the upper arm switches in first arm switch circuit 11 and the lower arm switches in second arm switch circuit 12 is connected to first control terminal Drive1, the other arm switch is connected to first control terminal Drive1 through a level inverter circuit, one of the lower arm switches in first arm switch circuit 11 and the upper arm switches in second arm switch circuit 12 is connected to first control terminal Drive1, the other arm switch is connected to first control terminal Drive1 through a level inverter circuit, the first control terminal Drive1 and the second control terminal Drive2 respectively receive level signals with different potentials, which is two cases shown in fig. 2 and 3.
As shown in fig. 2, the controlled end of the upper arm switch in first arm switch circuit 11 is connected to first level inverter circuit 20 and then connected to first control end Drive1, and the controlled end of the upper arm switch in second arm switch circuit 12 is connected to second level inverter circuit 30 and then connected to second control end Drive 2.
When the first control end Drive1 receives a high level and the second control end Drive2 receives a low level, the lower arm switch in the second arm switch circuit 12 and the upper arm switch circuit of the first arm switch circuit 11 are turned on, the upper arm switch of the second arm switch circuit 12 and the lower arm switch of the first arm switch circuit 11 are both turned off, the direct-current power input from the input end of the direct-current power source flows into the first end of the load connecting end J1 through the common end of the first arm switch circuit and flows out from the second end of the load connecting end J1 to the common end of the second arm switch circuit 12 and the lower arm switch to the ground, the load receives the direct-current power source to work, and when the second control end Drive2 receives a high level and the first control end Drive1 receives a low level, the lower arm switch in the first arm switch circuit 11 and the upper arm switch circuit of the second arm switch circuit 12 are turned on, the upper arm switch of the first arm switch circuit 11 and the lower arm switch of the second arm switch circuit 12 are both turned off, a direct-current power supply input by an input end of the direct-current power supply flows into the second end of the load access end J1 through the common end of the second arm switch circuit, and flows out to the common end of the first arm switch circuit 11 and the lower arm switch to the ground from the first end of the load access end J1, the load receives the direct-current power supply to work, and when the level is switched, the polarities of direct-current power supplies received by the load are opposite, so that the change of the working state of the load is controlled.
Similarly, as shown in fig. 3, the controlled end of the lower arm switch of the second arm switch circuit 12 is connected to the first level inverter circuit 20 and then connected to the first control end Drive1, and the controlled end of the lower arm switch of the second arm switch circuit 12 is connected to the second level inverter circuit 30 and then connected to the second control end Drive2, which is opposite to the working process of fig. 2 and will not be described in detail here.
With the arrangement, two paths of level signals with different potentials can be output, when the upper bridge arm switch of the corresponding first bridge arm switch circuit 11 or second bridge arm switch circuit 12 is driven to be switched on, the lower bridge arm switch on the diagonal with the upper bridge arm switch is controlled to be switched on through the upper bridge arm switch, so that the four bridge arm switches can be controlled to work by outputting two paths of driving signals, and the problem of direct connection of the upper tubes and the lower tubes of the same bridge arm switch is solved.
it can be understood that the driving circuit of the present invention has a simple circuit structure, is easy to implement, and can be widely applied to driving of electrical components requiring output of a forward and reverse driving circuit, that is, the present invention includes, but is not limited to, driving of a dc four-way valve or a motor.
According to the technical scheme, a driving circuit is formed by a direct-current power supply input end, a first control end Drive1, a second control end Drive2, an H-bridge switch circuit 10, a first level inverter circuit 20 and a second level inverter circuit 30 and can be used for driving a load in an air conditioner, wherein an upper bridge arm switch in the H-bridge switch circuit 10 is a PMOS (P-channel metal oxide semiconductor) tube, a lower bridge arm switch is an NMOS (N-channel metal oxide semiconductor) tube, and one bridge arm switch in the diagonal upper bridge arm switch and the lower bridge arm switch is connected with one level inverter circuit and the other bridge arm switch and is simultaneously connected to the control ends, so that simultaneous conduction and turn-off are realized, staggered conduction and turn-off of the upper bridge arm switch and the lower bridge arm switch in the same bridge arm switch circuit are avoided, the direct connection structure of the driving circuit is simplified. Meanwhile, the driving is realized by adopting the MOS tube, and the rapidity of the H-bridge switching circuit 10 is higher, so that the driving circuit can be used for controlling various tight moving parts, such as a motor, and can also be used for driving a direct-current four-way valve, and the application range is wide.
further, as shown in fig. 4 to 11, the driving circuit further includes:
A first OC gate circuit 40 connected to the controlled terminal of the upper arm switch of the first arm switch circuit 11, and configured to perform level inversion output on a level signal input to the upper arm switch of the first arm switch circuit 11, and pull up a potential of the controlled terminal of the upper arm switch of the first arm switch circuit 11 when operating;
The second OC gate circuit 50 is connected to the controlled end of the upper arm switch of the second arm switch circuit 12, and is configured to perform level inversion output on a level signal input to the upper arm switch of the second arm switch circuit 12, and pull up the potential of the controlled end of the upper arm switch of the second arm switch circuit 12 when the second OC gate circuit operates;
A third OC gate circuit 60 connected to the controlled end of the lower arm switch of the first arm switch circuit 11, and configured to perform level inversion output on the level signal input to the lower arm switch of the first arm switch circuit 11, and pull down the potential of the controlled end of the lower arm switch of the first arm switch circuit 11 when the operation is performed;
And a fourth OC gate circuit 70 connected to the controlled terminal of the lower arm switch of the second arm switch circuit 12, and configured to perform level inversion output on the level signal input to the lower arm switch of the second arm switch circuit 12, and pull down the potential of the controlled terminal of the lower arm switch of the second arm switch circuit 12 when the second arm switch circuit operates.
In this embodiment, because the distance between the nodes of the two different potentials on the electric control board is very close, there is a problem that a very fine conductor is grown, and the nodes of the two potentials are connected with a certain impedance, for example, when an anode wire is grown between the drain and the source of the lower bridge arm switch (NMOS tube), the lower bridge arm switch will be normally on, that is, an anode wire effect problem is generated, and finally the upper and lower bridge arm switches in the bridge arm switch circuit are simultaneously turned on, so, in order to solve the anode wire effect problem, in the present invention, each of the controlled ends of the upper bridge arm switch and the lower bridge arm switch is connected with an OC gate circuit for pulling up or pulling down the grid potential of the bridge arm switch, so that the anode wire connected between the drain and the source of the bridge arm switch is burnt, for example, when an anode wire is grown between the drain and the source of the lower bridge arm switch (NMOS tube, as shown in fig. 8, the third OC gate circuit 60 is turned on, the gate potential of the lower arm switch of the first arm switch circuit 11 is pulled down, the anode wire is electrically burned, and the circuit returns to normal.
meanwhile, each OC gate circuit also has the function of level inversion, and the level input to the bridge arm switches is inverted and output to each bridge arm switch.
In an embodiment, the first OC gate circuit 40 and the second OC gate circuit 50 have the same circuit structure, and each of the first OC gate circuit and the second OC gate circuit includes a seventh resistor, an eighth resistor, a ninth resistor, a second PNP triode, and a first working voltage input terminal;
the first end of the seventh resistor is the input end of the first level inverter circuit 20 or the second level inverter circuit 30, the second end of the seventh resistor, the first end of the eighth resistor and the base of the second PNP triode are interconnected, the emitter of the second PNP triode, the second end of the eighth resistor and the input end of the first working voltage source are connected, the collector of the second PNP triode is connected with the second end of the ninth resistor, the connection node is the output end of the first level inverter circuit 20 or the second level inverter circuit 30, and the second end of the ninth resistor is grounded.
that is, the first OC gate circuit 40 includes a resistor R71, a resistor R81, a resistor R91, a PNP transistor Q51, and a first operating voltage input terminal VCC, and the second OC gate circuit 50 includes a resistor R72, a resistor R82, a resistor R92, a PNP transistor Q52, and a first operating voltage input terminal, in an embodiment, the first operating voltage VCC input by the first operating voltage input terminal is equal to the voltage of the dc power input by the dc power input terminal.
the first OC gate circuit 40 and the second OC gate circuit 50 are turned off when receiving a high level, output a low level, are turned on when receiving a low level, output a high level, and pull up the grid potential of the connected bridge arm switches when being turned on, and the grid and the source of the bridge arm switches are electrified, so that the problem of the anode wire effect can be solved, the bridge arm switches are prevented from being directly connected, and the function of level inversion is realized.
Meanwhile, in an embodiment, the third OC gate circuit 60 and the fourth OC gate circuit 70 each include a tenth resistor, an eleventh resistor, a twelfth resistor, a second NPN transistor, and a first operating voltage input terminal;
The first end of the tenth resistor is the input end of the first level inverter circuit 20 or the second level inverter circuit 30, the second end of the tenth resistor, the first end of the eleventh resistor and the base of the second NPN triode are connected, the second end of the eleventh resistor and the emitter of the second NPN triode are both grounded, the collector of the second NPN triode is connected with the first end of the twelfth resistor, and the second end of the twelfth resistor is connected with the first working voltage input end.
That is, the third OC gate circuit 60 includes a resistor R101, a resistor R111, a resistor R121, an NPN transistor Q61, and a first operating voltage input terminal, and the second OC gate circuit 50 includes a resistor R102, a resistor R112, a resistor R122, an NPN transistor Q62, and a first operating voltage input terminal.
The third OC gate circuit 60 and the fourth OC gate circuit 70 are turned off when receiving a low level and output a high level, and are turned on when receiving a high level and output a low level, and the gate potentials of the connected bridge arm switches are pulled up when being turned on, and the gates and the sources of the bridge arm switches are energized, so that the problem of the anode wire effect can be solved, and the function of level inversion can be realized.
Meanwhile, since each OC gate has a level inversion function, the connection relationship with the first level inverter circuit 20 and the second level inverter circuit 30 can be in four ways as follows.
(1) As shown in fig. 4 and 8, the input end of the first level inverter circuit 20 is connected to the first control end Drive1, the output end of the first level inverter circuit 20 is connected to the input end of the first OC gate circuit 40, the output end of the first OC gate circuit 40 is connected to the controlled end of the upper arm switch of the first arm switch circuit 11, the input end of the fourth OC gate circuit 70 is connected to the first control end Drive1, and the output end of the fourth OC gate circuit 70 is connected to the controlled end of the lower arm switch of the second arm switch circuit 12;
the input end of the second level inverter circuit 30 is connected to the second control end Drive2, the output end of the second level inverter circuit 30 is connected to the input end of the second OC gate circuit 50, the output end of the second OC gate circuit 50 is connected to the controlled end of the upper arm switch of the second arm switch circuit 12, the input end of the third OC gate circuit 60 is connected to the second control end Drive2, and the output end of the third OC gate circuit 60 is connected to the controlled end of the lower arm switch of the first arm switch circuit 11.
In this embodiment, when the high level is input from the first control terminal Drive1 and the low level is input from the second control terminal Drive2, the high level is level-inverted into the low level by the fourth OC gate circuit 70 and is output to the controlled terminal of the lower arm switch of the second arm switch circuit 12, and the high level is output to the controlled terminal of the upper arm switch of the first arm switch circuit 11 after two level conversions are performed by the first level-inverting circuit 20 and the first OC gate circuit 40, both the upper arm switch of the first arm switch circuit 11 and the lower arm switch of the second arm switch circuit 12 are kept off, while the low level is level-inverted into the high level by the third OC gate circuit 60 and is output to the controlled terminal of the lower arm switch of the first arm switch circuit 11, and the low level is output to the controlled terminal of the upper arm switch of the second arm switch circuit 12 after two level conversions are performed by the second level-inverting circuit 30 and the second OC 50, the lower arm switch of the first arm switch circuit 11 and the upper arm switch of the second arm switch circuit 12 are diagonally turned on, and the dc power is input to the second end of the load access terminal J1 through the common terminal of the second arm switch circuit 12, and is output to the common terminal of the first arm switch circuit 11 and the lower arm switch to the ground from the first end of the load access terminal J1.
similarly, when the first control terminal Drive1 inputs a low level and the second control terminal Drive2 inputs a high level, the low level is level-inverted into a high level by the fourth OC gate circuit 70 and is output to the controlled terminal of the lower arm switch of the second arm switch circuit 12, and the low level is output to the controlled terminal of the upper arm switch of the first arm switch circuit 11 after two level conversions are performed by the first level inverter circuit 20 and the first OC gate circuit 40, the upper arm switch of the first arm switch circuit 11 and the lower arm switch of the second arm switch circuit 12 are diagonally conducted, the high level is level-inverted into a low level by the third gate circuit OC 60 and is output to the controlled terminal of the lower arm switch of the first arm switch circuit 11, and the high level is output to the controlled terminal of the upper arm switch of the second arm switch circuit 12 after two level conversions are performed by the second level inverter circuit 30 and the second OC gate circuit 50, the lower arm switch of the first arm switch circuit 11 and the upper arm switch of the second arm switch circuit 12 are turned off diagonally, and the dc power is input to the first end of the load connection terminal J1 through the common terminal of the first arm switch circuit 11, and is output to the common terminal of the second arm switch circuit 12 and the lower arm switch to the ground from the second end of the load connection terminal J1.
with the arrangement, two paths of level signals with different potentials can be output, when the upper bridge arm switch of the corresponding first bridge arm switch circuit 11 or second bridge arm switch circuit 12 is driven to be switched on, the lower bridge arm switch on the diagonal with the upper bridge arm switch is controlled to be switched on through the upper bridge arm switch, so that the four bridge arm switches can be controlled to work by outputting two paths of driving signals, and the problem that the upper tube and the lower tube of the same bridge arm switch are directly connected is solved.
(2) as shown in fig. 5 and 9, the input end of the first level inverter circuit 20 is connected to the first control end Drive1, the output end of the first level inverter circuit 20 is connected to the input end of the first OC gate circuit 40, the output end of the first OC gate circuit 40 is connected to the controlled end of the upper arm switch of the first arm switch circuit 11, the input end of the fourth OC gate circuit 70 is connected to the output end of the first OC gate circuit 40, and the output end of the fourth OC gate circuit 70 is connected to the controlled end of the lower arm switch of the second arm switch circuit 12;
the input end of the second level inverter circuit 30 is connected to the second control end Drive2, the output end of the second level inverter circuit 30 is connected to the input end of the second OC gate circuit 50, the output end of the second OC gate circuit 50 is connected to the controlled end of the upper arm switch of the second arm switch circuit 12, the input end of the third OC gate circuit 60 is connected to the output end of the second OC gate circuit 50, and the output end of the third OC gate circuit 60 is connected to the controlled end of the lower arm switch of the first arm switch circuit 11.
In this embodiment, the difference from the above embodiment is that the input terminal of the third OC gate circuit 60 and the input terminal of the fourth OC gate circuit 70 are connected at different positions, and the input terminals thereof are respectively connected to the output terminals of the diagonal OC gates, namely, the level signal at the input end of the first control end Drive1 is subjected to level conversion twice by the first level inverter circuit 20 and the first OC gate circuit 40 and then output to the controlled end of the upper arm switch of the first arm switch circuit 11, and the level signal at the input end of the second control end Drive2 is subjected to level conversion twice by the second level inverter circuit 30 and the second OC gate circuit 50 and then output to the controlled end of the upper arm switch of the second arm switch circuit 12, and simultaneously, the voltage level of the third OC gate circuit 60 is converted and then output to the controlled end of the lower bridge arm switch of the second bridge arm switch circuit 12.
The operation principle and the beneficial effect of the present embodiment are the same as those of the driving circuit in the previous embodiment, that is, when the first control end Drive1 receives a high level and the second control end Drive2 receives a low level, the upper arm switch of the first arm switch circuit 11 and the lower arm switch of the second arm switch circuit 12 are turned off and the upper arm switch of the second arm switch circuit 12 and the lower arm switch of the first arm switch circuit 11 are diagonally turned on, and when the first control end Drive1 receives a low level and the second control end Drive2 receives a high level, the upper arm switch of the first arm switch circuit 11 and the lower arm switch of the second arm switch circuit 12 are diagonally turned on and the upper arm switch of the second arm switch circuit 12 and the lower arm switch of the first arm switch circuit 11 are turned off, which is not described in detail herein.
In addition, compared with the driving circuits of fig. 4 and fig. 8, the OC gates in this embodiment receive the level signals and are all subjected to level conversion and pull-up, so that the driving is more reliable.
as shown in fig. 8 and 9, when the first level inverter circuit 20 is connected between the first control terminal Drive1 and the first OC gate circuit 40, and the second level inverter circuit 30 is connected between the second control terminal Drive2 and the second OC gate circuit 50, in order to control the corresponding upper arm switches, in an embodiment, each of the first level inverter circuit 20 and the second level inverter circuit 30 includes a first resistor, a second resistor, a third resistor, a first PNP transistor, and a first operating power input terminal;
the first end of the first resistor is the input end of the first level inverter circuit 20 or the second level inverter circuit 30, the second end of the first resistor, the first end of the second resistor and the base of the first PNP triode are interconnected, the emitter of the first PNP triode, the second end of the second resistor and the input end of the first working voltage source are connected, the collector of the first PNP triode is connected with the second end of the third resistor, the connection node is the output end of the first level inverter circuit 20 or the second level inverter circuit 30, and the second end of the third resistor is grounded.
That is, the first level inverter circuit 20 includes a resistor R11, a resistor R21, a resistor R31, and a PNP transistor Q41, and the second level inverter circuit 30 includes a resistor R12, a resistor R22, a resistor R32, and a PNP transistor Q42, when the first control terminal Drive1 receives a high level and the second control terminal Drive2 receives a low level, the PNP transistor Q41 is turned off, the first level inverter circuit 20 outputs a low level, the PNP transistor Q42 is turned on, the second level inverter circuit 30 outputs a high level, and further the upper arm switch of the first arm switch circuit 11 and the lower arm switch of the second arm switch circuit 12 are controlled to be turned off, and the upper arm switch of the second arm switch circuit 12 and the lower arm switch of the second arm switch circuit 12 are controlled to be turned on, when the first control terminal Drive1 receives a low level and the second control terminal Drive2 receives a high level, the upper arm switch of the first arm switch circuit 11 and the lower arm switch of the second arm switch circuit 12 and the upper arm switch of the second arm switch 12 and the second arm switch of the second arm switch 12 are turned on The lower arm switch of the two arm switch circuit 12 is turned off.
(3) As shown in fig. 6 and 10, in an embodiment, an input end of the first level inverter circuit 20 is connected to the first control end Drive1, an output end of the first level inverter circuit 20 is connected to an input end of the fourth OC gate circuit 70, an output end of the fourth OC gate circuit 70 is connected to a controlled end of the upper arm switch of the second arm switch circuit 12, an input end of the first OC gate circuit 40 is connected to the first control end Drive1, and an output end of the first OC gate circuit 40 is connected to a controlled end of the upper arm switch of the first arm switch circuit 11;
The input end of the second level inverter circuit 30 is connected to the second control end Drive2, the output end of the second level inverter circuit 30 is connected to the input end of the third OC gate circuit 60, the output end of the third OC gate circuit 60 is connected to the controlled end of the lower arm switch of the first arm switch circuit 11, the input end of the second OC gate circuit 50 is connected to the second control end Drive2, and the output end of the second OC gate circuit 50 is connected to the controlled end of the upper arm switch of the second arm switch circuit 12.
In this embodiment, the first level inverter circuit 20 is connected between the first control terminal Drive1 and the fourth OC gate circuit 70, the input terminal of the first OC gate circuit 40 is connected to the first control terminal Drive1, the second level inverter circuit 30 is connected between the second control terminal Drive2 and the third OC gate circuit 60, the input terminal of the second OC gate circuit 50 is connected to the second control terminal Drive2, the level signal input by the first control terminal Drive1 is output to the controlled terminal of the upper arm switch of the first arm switch circuit 11 after being level-inverted by the first OC gate circuit 40, and is output to the controlled terminal of the upper arm switch of the first arm switch circuit 11 after being level-inverted twice by the first level inverter circuit 20 and the fourth OC gate circuit 70, and the level signal input by the second control terminal Drive2 is output to the controlled terminal of the upper arm switch of the second arm switch circuit 12 after being level-inverted by the second OC gate circuit 50, and is output to the controlled terminal of the first arm switch after being level-inverted twice by the second level inverter circuit 30 and the third OC gate circuit 60 And turning off the controlled end of the lower arm switch of the circuit 11, thereby realizing the simultaneous conduction and the turn-off of the opposite angles.
(4) as shown in fig. 7 and fig. 11, in an embodiment, an input end of the first level inverter circuit 20 is connected to the first control end Drive1, an output end of the first level inverter circuit 20 is connected to an input end of the fourth OC gate circuit 70, an output end of the fourth OC gate circuit 70 is connected to a controlled end of the upper arm switch of the second arm switch circuit 12, an input end of the first OC gate circuit 40 is connected to an output end of the fourth OC gate circuit 70, and an output end of the first OC gate circuit 40 is connected to a controlled end of the upper arm switch of the first arm switch circuit 11;
the input end of the second level inverter circuit 30 is connected to the second control end Drive2, the output end of the second level inverter circuit 30 is connected to the input end of the third OC gate circuit 60, the output end of the third OC gate circuit 60 is connected to the controlled end of the lower arm switch of the first arm switch circuit 11, the input end of the second OC gate circuit 50 is connected to the output end of the third OC gate circuit 60, and the output end of the second OC gate circuit 50 is connected to the controlled end of the upper arm switch of the second arm switch circuit 12.
The operation principle and the beneficial effect of the present embodiment are the same as those of the driving circuit in the previous embodiment, that is, when the first control end Drive1 receives a high level and the second control end Drive2 receives a low level, the upper arm switch of the first arm switch circuit 11 and the lower arm switch of the second arm switch circuit 12 are turned on and the upper arm switch of the second arm switch circuit 12 and the lower arm switch of the first arm switch circuit 11 are turned off, and when the first control end Drive1 receives a low level and the second control end Drive2 receives a high level, the upper arm switch of the first arm switch circuit 11 and the lower arm switch of the second arm switch circuit 12 are turned off and the upper arm switch of the second arm switch circuit 12 and the lower arm switch of the first arm switch circuit 11 are turned on, which is not described in detail herein.
compared with the driving circuits of fig. 6 and 10, the OC gates in this embodiment receive the level signals, and are driven more reliably after level conversion and pull-up.
in one embodiment, as shown in fig. 10 and 11, when the first level inverter circuit 20 is connected between the first control terminal Drive1 and the fourth OC gate circuit 70, and the second level inverter circuit 30 is connected between the second control terminal Drive2 and the third OC gate circuit 60, in order to control the corresponding lower arm switches, the first level inverter circuit 20 and the second level inverter circuit 30 each include a fourth resistor, a fifth resistor, a sixth resistor, a first NPN transistor, and a first operating voltage input terminal;
The first end of the fourth resistor is the input end of the first level inverter circuit 20 or the second level inverter circuit 30, the second end of the fourth resistor, the first end of the fifth resistor and the base of the first NPN triode are connected, the second end of the fifth resistor and the emitter of the first NPN triode are both grounded, the collector of the first NPN triode is connected with the first end of the sixth resistor, and the second end of the sixth resistor is connected with the first working voltage input end.
that is, first level inverter circuit 20 includes resistor R41, resistor R51, resistor R51, and NPN transistor Q71, and second level inverter circuit 30 includes resistor R42, resistor R52, resistor R62, and NPN transistor Q72, and when first control terminal Drive1 receives a high level and second control terminal Drive2 receives a low level, NPN transistor Q71 is turned on, first level inverter circuit 20 outputs a low level, NPN transistor Q72 is turned off, and second level inverter circuit 30 outputs a high level, thereby controlling upper arm switch of first arm switch circuit 11 and lower arm switch of second arm switch circuit 12 to be turned on, and controlling upper arm switch of second arm switch circuit 12 and lower arm switch of second arm switch circuit 12 to be turned off, and when first control terminal Drive1 receives a low level and second control terminal Drive2 receives a high level, upper arm switch of first arm switch circuit 11 and lower arm switch of second arm switch circuit 12 and upper switch of second arm switch circuit 12 and second control terminal Drive 3556 turns off The lower arm switch of the two-arm switch circuit 12 is turned on.
the present invention further provides an air conditioner, which includes a load and a driving circuit, and the specific structure of the driving circuit refers to the above embodiments, and since the air conditioner employs all technical solutions of all the above embodiments, the air conditioner at least has all beneficial effects brought by the technical solutions of the above embodiments, and details are not repeated herein. The power supply end of the load is connected with the power supply output end of the driving circuit, and the load comprises a direct-current four-way valve or a motor.
When the direct-current four-way valve is controlled, the conduction of an upper bridge arm switch of a first bridge arm switch circuit 11 and the conduction of an upper bridge arm switch of a second bridge arm switch circuit 12 in an H bridge switch circuit 10 are controlled to control the conduction of a lower bridge arm switch on a diagonal line so as to form the direction of the current of a direct-current power supply for driving the four-way valve to work to flow through the four-way valve, so that the four-way valve is opened to a corresponding refrigeration, dehumidification or heating mode, then all bridge arm switches in the H bridge circuit can be turned off to turn off the direct-current driving power supply for the four-way valve, the self-holding of the state of the four-.
When the motor is controlled, PWM signals with preset duty ratios can be input through the first control end and the second control end to control the conduction of the upper arm switch of the first arm switch circuit 11 and the upper arm switch of the second arm switch circuit 12 in the H-bridge switch circuit 10 to control the conduction of the lower arm switch on the diagonal line, so that the direct-current power supply is converted into an alternating-current power supply to drive the motor to rotate, a sine wave alternating-current signal or a cosine wave alternating-current signal can be output to the motor, the motor is driven to operate at high speed, and the compressor or the fan blades are driven to operate.
The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and all modifications and equivalents of the present invention, which are made by the contents of the present specification and the accompanying drawings, or directly/indirectly applied to other related technical fields, are included in the scope of the present invention.
Claims (10)
1. A driver circuit, characterized in that the driver circuit comprises:
A DC power input terminal for inputting a DC power;
A first control terminal for inputting a first level signal;
A second control terminal for inputting a second level signal inverted from the first level signal;
the H-bridge switching circuit comprises a first bridge arm switching circuit and a second bridge arm switching circuit;
The controlled end of one of the upper bridge arm switch of the first bridge arm switch circuit and the lower bridge arm switch of the second bridge arm switch circuit is connected with the first control end, and the controlled end of the other bridge arm switch is connected with the first control end through a first level inverter circuit;
the controlled end of one of the upper bridge arm switch of the second bridge arm switch circuit and the lower bridge arm switch of the first bridge arm switch circuit is connected with the second control end, and the controlled end of the other bridge arm switch is connected with the second control end through a second level inverter circuit;
when the first level signal is received, an upper bridge arm switch of the first bridge arm switch circuit and a lower bridge arm switch of the second bridge arm switch circuit work, and a first polarity voltage signal is output to drive a load after the direct-current power supply is connected; and the number of the first and second groups,
When the second level signal is received, the lower bridge arm switch of the first bridge arm switch circuit and the upper bridge arm switch of the second bridge arm switch circuit work, and after the direct-current power supply is connected, a second polarity voltage signal with the polarity opposite to that of the first polarity voltage signal is output to drive a load to work;
The upper bridge arm switch of the first bridge arm switch circuit and the lower bridge arm switch of the second bridge arm switch circuit are PMOS tubes, and the lower bridge arm switch of the first bridge arm switch circuit and the lower bridge arm switch of the second bridge arm switch circuit are NMOS tubes.
2. the drive circuit of claim 1, wherein the drive circuit further comprises:
the first OC gate circuit is connected to the controlled end of the upper bridge arm switch of the first bridge arm switch circuit, and is used for performing level inversion output on a level signal input to the upper bridge arm switch of the first bridge arm switch circuit and pulling up the potential of the controlled end of the upper bridge arm switch of the first bridge arm switch circuit when in work;
the second OC gate circuit is connected to the controlled end of the upper bridge arm switch of the second bridge arm switch circuit, and is used for performing level inversion output on a level signal input to the upper bridge arm switch of the second bridge arm switch circuit and pulling up the potential of the controlled end of the upper bridge arm switch of the second bridge arm switch circuit when the second OC gate circuit works;
the third OC gate circuit is connected to the controlled end of the lower bridge arm switch of the first bridge arm switch circuit, and is used for performing level inversion output on a level signal input to the lower bridge arm switch of the first bridge arm switch circuit and pulling down the potential of the controlled end of the lower bridge arm switch of the first bridge arm switch circuit when the bridge is in work;
And the fourth OC gate circuit is connected to the controlled end of the lower bridge arm switch of the second bridge arm switch circuit, and is used for performing level inversion output on the level signal input to the lower bridge arm switch of the second bridge arm switch circuit and pulling down the potential of the controlled end of the lower bridge arm switch of the second bridge arm switch circuit when the second OC gate circuit works.
3. The driving circuit according to claim 2, wherein an input terminal of the first level inverter circuit is connected to the first control terminal, an output terminal of the first level inverter circuit is connected to an input terminal of the first OC gate circuit, an output terminal of the first OC gate circuit is connected to a controlled terminal of an upper arm switch of the first arm switch circuit, an input terminal of the fourth OC gate circuit is connected to the first control terminal or an output terminal of the first OC gate circuit, and an output terminal of the fourth OC gate circuit is connected to a controlled terminal of a lower arm switch of the second arm switch circuit;
the input end of the second level inverter circuit is connected with the second control end, the output end of the second level inverter circuit is connected with the input end of the second OC gate circuit, the output end of the second OC gate circuit is connected with the controlled end of the upper bridge arm switch of the second bridge arm switch circuit, the input end of the third OC gate circuit is connected with the second control end or the output end of the second OC gate circuit, and the output end of the third OC gate circuit is connected with the controlled end of the lower bridge arm switch of the first bridge arm switch circuit.
4. The driving circuit of claim 3, wherein the first level inverter circuit and the second level inverter circuit each comprise a first resistor, a second resistor, a third resistor, a first PNP transistor, and a first operating power supply input;
the first end of the first resistor is the input end of the first level inverter circuit or the second level inverter circuit, the second end of the first resistor, the first end of the second resistor and the base electrode of the first PNP triode are interconnected, the emitter electrode of the first PNP triode, the second end of the second resistor and the input end of the first working voltage source are connected, the collector electrode of the first PNP triode is connected with the second end of the third resistor, the connecting node is the output end of the first level inverter circuit or the second level inverter circuit, and the second end of the third resistor is grounded.
5. the driving circuit according to claim 2, wherein an input terminal of the first level inverter circuit is connected to the first control terminal, an output terminal of the first level inverter circuit is connected to an input terminal of the fourth OC gate circuit, an output terminal of the fourth OC gate circuit is connected to a controlled terminal of the upper arm switch of the second arm switch circuit, an input terminal of the first OC gate circuit is connected to the first control terminal or an output terminal of the fourth OC gate circuit, and an output terminal of the first OC gate circuit is connected to a controlled terminal of the upper arm switch of the first arm switch circuit;
the input end of the second level inverter circuit is connected with the second control end, the output end of the second level inverter circuit is connected with the input end of the third OC gate circuit, the output end of the third OC gate circuit is connected with the controlled end of the lower bridge arm switch of the first bridge arm switch circuit, the input end of the second OC gate circuit is connected with the second control end or the output end of the third OC gate circuit, and the output end of the second OC gate circuit is connected with the controlled end of the upper bridge arm switch of the second bridge arm switch circuit.
6. The driving circuit of claim 5, wherein the first level inverter circuit and the second level inverter circuit each comprise a fourth resistor, a fifth resistor, a sixth resistor, a first NPN transistor, and a first operating voltage input terminal;
the first end of the fourth resistor is the input end of the first level inverter circuit or the second level inverter circuit, the second end of the fourth resistor, the first end of the fifth resistor and the base of the first NPN triode are connected, the second end of the fifth resistor and the emitter of the first NPN triode are both grounded, the collector of the first NPN triode is connected with the first end of the sixth resistor, and the second end of the sixth resistor is connected with the first working voltage input end.
7. the driving circuit according to any one of claims 2-6, wherein the first OC gate circuit and the second OC gate circuit each comprise a seventh resistor, an eighth resistor, a ninth resistor, a second PNP transistor and a first operating voltage input terminal;
the first end of the seventh resistor is the input end of the first level inverter circuit or the second level inverter circuit, the second end of the seventh resistor, the first end of the eighth resistor and the base of the second PNP triode are interconnected, the emitter of the second PNP triode, the second end of the eighth resistor and the input end of the first working voltage source are connected, the collector of the second PNP triode is connected with the second end of the ninth resistor, the connection node is the output end of the first level inverter circuit or the second level inverter circuit, and the second end of the ninth resistor is grounded.
8. the driver circuit according to any of claims 2-6, wherein the third OC gate circuit and the fourth OC gate circuit each comprise a tenth resistor, an eleventh resistor, a twelfth resistor, a second NPN transistor, and a first operating voltage input;
the first end of the tenth resistor is an input end of the first level inverter circuit or the second level inverter circuit, the second end of the tenth resistor, the first end of the eleventh resistor and the base of the second NPN triode are connected, the second end of the eleventh resistor and the emitter of the second NPN triode are both grounded, the collector of the second NPN triode is connected with the first end of the twelfth resistor, and the second end of the twelfth resistor is connected with the first working voltage input end.
9. An air conditioner comprising a load and a driving circuit according to any one of claims 1 to 8, wherein a power supply terminal of the load is connected to a power supply output terminal of the driving circuit.
10. the air conditioner according to claim 9, wherein the load comprises a dc four-way valve or a motor.
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| CN201910830034.6A CN110545034B (en) | 2019-09-03 | 2019-09-03 | Drive circuit and air conditioner |
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| Publication number | Publication date |
|---|---|
| CN110545034B (en) | 2020-10-20 |
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