CN110544687B - 半导体封装结构及用于形成半导体封装结构的方法 - Google Patents

半导体封装结构及用于形成半导体封装结构的方法 Download PDF

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CN110544687B
CN110544687B CN201910146963.5A CN201910146963A CN110544687B CN 110544687 B CN110544687 B CN 110544687B CN 201910146963 A CN201910146963 A CN 201910146963A CN 110544687 B CN110544687 B CN 110544687B
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tim layer
semiconductor
layer
package structure
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CN110544687A (zh
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叶庭聿
许家豪
陈伟铭
丁国强
俞笃豪
侯上勇
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明实施例涉及一种半导体封装结构及用于形成半导体封装结构的方法，所述半导体封装结构包含：衬底；第一半导体裸片及第二半导体裸片，其位于所述衬底上方；及多热接口材料TIM结构，其经安置于所述第一半导体裸片及所述第二半导体裸片上方。所述第一半导体裸片包含第一热输出，且所述第二半导体裸片包含小于所述第一热输出的第二热输出。所述多TIM结构包含经安置于所述第一半导体裸片的至少一部分上方的第一TIM层及第二TIM层。所述第一TIM层的导热系数高于所述第二TIM层的导热系数。所述第一TIM层覆盖所述第一半导体裸片。

Description

半导体封装结构及用于形成半导体封装结构的方法
技术领域
本发明实施例涉及半导体封装结构及用于形成半导体封装结构的方法。
背景技术
半导体集成电路(IC)产业已经历快速成长。IC材料及设计的技术进步已产生一代又一代IC，其中每代IC包含比前一代IC更小且更复杂的电路。更小且更复杂的电路具二维(2D)性，因为由集成IC组件占用的面积位于半导体晶片的表面上。然而，2DIC形成面临物理限制。此些限制之一为容纳集成组件所需的最小面积。另外，当更多装置包含于芯片或裸片中时，需要更复杂设计。
已开发三维集成电路(3DIC)来实现进一步提高电路密度。例如堆叠式封装(PoP)的3DIC封装应用变得越来越流行且广泛用于移动装置，这是因为其可通过集成逻辑芯片(例如应用程序处理器(AP))、高容量/带宽存储器芯片(例如宽输入/输出(WIO)芯片、低功率双倍数据速率X(LPDDRx)芯片等等)及/或其它异质芯片(例如传感器、微机电系统(MEM)、网络装置等等)来提高电气性能。
在使用封装期间产生热量。热量会引起3DIC封装结构的热应力及翘曲以导致焊球破裂。即使在3DIC封装结构中使用模塑料，仍无法完全消除过热及翘曲的问题。
发明内容
本发明的实施例公开一种半导体封装结构，其包括：衬底；多个半导体裸片，其位于所述衬底上方；及多热接口材料(TIM)结构，其位于所述多个半导体裸片上方，其中所述多TIM结构包括第一TIM层及第二TIM层，且所述第一TIM层的导热系数(Tk)不同于所述第二TIM层的导热系数。
本发明的实施例公开一种半导体封装结构，其包括：衬底；第一半导体裸片及第二半导体裸片，其安置于所述衬底上方，其中所述第一半导体裸片包含第一热输出且所述第二半导体裸片包含小于所述第一热输出的第二热输出；及多TIM结构，其安置于所述第一半导体裸片及所述第二半导体裸片上方，所述多TIM结构包括安置于所述第一半导体裸片的至少一部分上方的第一TIM层及第二TIM层，其中所述第一TIM层的导热系数大于所述第二TIM层的导热系数。
本发明的实施例公开一种用于形成半导体封装结构的方法，其包括：接收包括裸片区域及安置于所述裸片区域中的第一半导体裸片及第二半导体裸片的衬底；在所述裸片区域中界定其中需要导热性的第一区域及其中需要粘着性的第二区域；及将第一TIM层安置于所述第一区域中且将第二TIM层安置于所述第二区域中，其中所述第一TIM层的导热系数大于所述第二TIM层的导热系数，且所述第二TIM层的粘着性大于所述第一TIM层的粘着性。
附图说明
从结合附图来阅读的[具体实施方式]最优选理解本公开的方面。应注意，根据行业标准做法，各种构件未按比例绘制。事实上，为使讨论清楚，可任意增大或减小各种构件的尺寸。
图1是表示根据本公开的方面的用于形成半导体封装结构的方法的流程图。
图2A到图2D是绘示根据本公开的一或多个实施例的方面所构建的各种制造阶段中的半导体封装结构的示意图。
图3是根据本公开的一或多个实施例的方面的半导体封装结构的横截面图。
图4是根据本公开的一或多个实施例的方面的半导体封装结构的横截面图。
图5是绘示根据本公开的一或多个实施例的方面的半导体封装结构的示意图。
图6是绘示根据本公开的一或多个实施例的方面的半导体封装结构的示意图。
图7是绘示根据本公开的一或多个实施例的方面的另一半导体封装结构的示意图。
图8是绘示根据本公开的一或多个实施例的方面的另一半导体封装结构的示意图。
具体实施方式
以下揭露提供用于实施所提供标的的不同特征的诸多不同实施例或实例。下文将描述元件及布置的特定实例以简化本公开。当然，此些仅为实例且不意在限制。例如，在以下描述中，使第一构件形成于第二构件上方或第二构件上可包含其中形成直接接触的所述第一构件及所述第二构件的实施例，且还可包含其中额外构件可形成于所述第一构件与所述第二构件之间使得所述第一构件及所述第二构件可不直接接触的实施例。另外，本公开可在各种实例中重复元件符号及/或字母。此重复是为了简单及清楚且其本身不指示所讨论的各种实施例及/或配置之间的关系。
此外，为便于描述，空间相对术语(例如“底下”、“下方”、“下”、“上方”、“上”、“在…上”等等)可在本文中用于描述元件或构件与另一(些)元件或构件的关系，如图中所绘示。空间相对术语除涵盖图中所描绘的定向之外，还打算涵盖装置在使用或操作中的不同定向。可依其它方式定向设备(旋转90度或依其它定向)，且还可因此解译本文中所使用的空间相对描述词。
如本文中所使用，例如“第一”、“第二”及“第三”的术语描述各种元件、组件、区域、层及/或区段，但此些元件、组件、区域、层及/或区段不应受限于此些术语。此些术语可仅用于使元件、组件、区域、层或区段彼此区分。除非内文清楚指示，否则本文中所使用的例如“第一”、“第二”及“第三”的术语不隐含序列或顺序。
如本文中所使用，术语“近似”、“大体上”、“实质”及“约”用于描述及考量小变动。当结合事件或情形使用时，术语可涉及其中精确发生所述事件或情形的例项及其中大致发生所述事件或情形的例项。例如，当结合数值使用时，术语可涉及小于或等于所述数值的±10％的变动范围，例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％或小于或等于±0.05％。例如，如果两个数值之间的差小于或等于所述值的平均数的±10％(例如小于或等于±5％、小于或等于±4％、小于或等于±3％、小于或等于±2％、小于或等于±1％、小于或等于±0.5％、小于或等于±0.1％或小于或等于±0.05％)，那么可认为所述值“大体上”相同或相等。例如，“大体上”平行可涉及相对于0°的角变动范围，其小于或等于±10°，例如小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°或小于或等于±0.05°。例如，“大体上”垂直可涉及相对于90°的角变动范围，其小于或等于±10°，例如小于或等于±5°、小于或等于±4°、小于或等于±3°、小于或等于±2°、小于或等于±1°、小于或等于±0.5°、小于或等于±0.1°或小于或等于±0.05°。
还可包含其它构件及过程。例如，可包含测试结构来促进3D封装或3DIC装置的验证测试。测试结构可包含(例如)形成于重布层中或衬底上的测试垫，其允许测试3D封装或3DIC、使用探针及/或探针卡等等。可对中间结构及最终结构执行验证测试。另外，本文中所公开的结构及方法可与并入已知良好裸片的中间验证的测试方法一起使用以提高良率且降低成本。
在3DIC中，携载集成电路的芯片或封装通常安装于提供从芯片(也指称裸片)到封装外部的电连接的封装载体(例如衬底或电路板)上。因为由3DIC封装结构的内部或中心区域中的裸片产生的热量不易高效率耗散，所以散热是3DIC封装结构的挑战。在一些实施例中，例如CPU裸片的裸片产生比其它裸片多的热量，因此，区域的温度会高于另一区域的温度。因此，热量会被拦截且引起局部温度尖峰(有时指称热点)。热点会负面影响整个3DIC封装结构的电气性能及可靠性。
因此，需要耗散装置裸片在操作期间产生的热量。在一些实施例中，为耗散热量，透过热接口材料(TIM)层将散热片或散热器附接到裸片，所述TIM层具有用于将由裸片产生的热量有效耗散到散热器中的高导热系数。各TIM可设计有特定特性以满足特定要求。例如，一些TIM具有较高导热系数，而其它TIM具有优选粘着性。在一些例项中，TIM经选择以牺牲导热系数来满足热要求。然而，由于封装结构可包含具有不同温度的区域且因此可经受各种应力，所以需要不同散热效率及不同粘着性。难以使单一TIM层满足全部要求。
因此，本公开提供一种包含多TIM结构的半导体封装结构及其形成方法。在一些实施例中，所述多TIM结构包含具有不同导热系数及粘着性的至少两个TIM层。在一些实施例中，所述多TIM结构包含取决于施加于所述半导体封装结构的应力的不同TIM层。例如，所述多TIM结构可包含暴露于较大应力的区域中的具有较大粘着性的TIM层及接收较小应力的其它区域中的具有较小粘着性的另一TIM层。在一些实施例中，所述多TIM结构包含取决于操作期间所产生的热量的不同TIM层。例如，所述多TIM结构可包含容纳产生较多热量的裸片的区域中的具有较大导热系数的TIM层及容纳产生较少热量的裸片的区域中的具有较小导热系数的另一TIM层。
图1是根据本公开的方面的用于形成半导体封装结构10的方法。方法10包含操作12：接收包含裸片区域及安置于裸片区域中的第一半导体裸片及第二半导体裸片的衬底。方法10包含操作14：在裸片区域中界定其中需要导热性的第一区域及其中需要粘着性的第二区域。方法10包含操作16：将第一TIM层安置于第一区域中且将第二TIM层安置于第二区域中。在一些实施例中，第一TIM层的导热系数大于第二TIM层的导热系数，且第二TIM层的粘着性大于第一TIM层的粘着性。方法10包含操作18：将散热器安置于第一TIM层及第二TIM层上方。将根据一或多个实施例来进一步描述方法10。应注意，可在各种方面的范围内重新布置或依其它方式修改方法10的操作。应进一步注意，可在方法10之前、方法10期间及方法10之后提供额外过程且本文中可仅简要描述一些其它过程。因此，其它实施方案可在本文中所描述的各种方面的范围内。
图2A到图2D是绘示根据本公开的一或多个实施例的方面所构建的各种制造阶段中的半导体封装结构100a的示意图，且图3及图4是沿图2D的线I-I'取得的横截面图。半导体封装结构100a包含第一封装。在一些实施例中，第一封装可为一或多个封装的载体或衬底110。在一些实施例中，第一封装是层叠衬底110。层叠衬底110可以是塑料衬底或陶瓷衬底。替代地，衬底110可以是堆积衬底。在一些实施例中，第一衬底110包含至少第一区域112a及第二区域112b。第一区域112a经界定及配置以容纳一或多个封装或裸片的区域，因此，第一区域112a可指称裸片区域。衬底110的第一区域112a可包含用于与封装或裸片接合的多个第一接合垫(图中未展示)。衬底110的第二区域112b未被配置为容纳封装或裸片的区域。在一些实施例中，第二区域112b包围第一区域112a(如图2A中所展示)，但本公开不受限于此。
仍参考图2A，半导体封装结构100a可包含多个第二封装。在一些实施例中，多个第二封装可以是多个半导体裸片。在一些实施例中，根据操作12，接收包含裸片区域112a及安置于裸片区域112a中的第一半导体裸片120及第二半导体裸片122的衬底110。例如(但不限于)，在一些实施例中提供至少第一半导体裸片120及至少第二半导体裸片122。在一些实施例中，第一半导体裸片120及第二半导体裸片122是具有相同大小及功能的裸片。在一些实施例中，第一半导体裸片120具有不同于第二半导体裸片122的大小。在一些实施例中，第一半导体裸片120具有不同于第二半导体裸片122的功能。第一半导体裸片120及第二半导体裸片122可各为集成电路(IC)芯片、单芯片系统(SoC)或其一部分。例如，第一半导体裸片120可以是专用集成电路(ASIC)裸片、应用程序处理(AP)裸片、逻辑裸片(其可进一步为中央处理单元(CPU)裸片或图形处理单元(GPU)裸片)等等。第二半导体裸片122可以是例如高带宽存储器(HBM)裸片等等的存储器裸片。
在一些实施例中，第一半导体裸片120及第二半导体裸片122的各者包含晶片。晶片可以是(例如但不限于)硅(Si)晶片。替代地，晶片可由以下各者制成：某一其它适合元素半导体，例如金刚石或锗(Ge)；适合化合物半导体，例如碳化硅(SiC)、砷化铟(InAs)或磷化铟(InP)；或适合合金半导体，例如SiGeC、磷化镓砷(GaAsP)或GaInP。晶片可包含各种掺杂区域(图中未展示)、隔离结构(图中未展示)、其它装置或其组合。第一半导体裸片120及第二半导体裸片122可包含各种被动及主动微电子装置，例如电阻器、电容器、电感器、二极管、金属氧化物半导体场效晶体管(MOSFET)、互补金属氧化物半导体(CMOS)装置、双极接面晶体管(BJT)、侧向扩散MOS(LDMOS)晶体管、高功率MOS晶体管或其它类型的晶体管。其可包含微机电系统(MEMS)装置及/或纳机电系统(NEMS)装置。
第一半导体裸片120及第二半导体裸片122透过多个连接器130接合到衬底110的第一区域112a(如图3及图4中所展示)。在一些实施例中，第一半导体裸片120及第二半导体裸片122可经上下翻转，使得第一半导体裸片120及第二半导体裸片122的主动表面面向衬底110且接合到衬底110。通过任何适合机构来接合第一半导体裸片120及第二半导体裸片122。例如，例如焊球(也指称焊料凸块)的连接器130可被安置在形成于第一半导体裸片120及第二半导体裸片122的主动表面上的接合垫上。接着，连接器130与衬底110上方的接合垫对准及接触，以产生衬底110与第一半导体裸片120及第二半导体裸片122之间的电耦合。另外，可沿第一方向D1来布置第一半导体裸片120及第二半导体裸片122(如图2A中所展示)，但本公开不受限于此。
仍参考图2A，接着将底胶132施配或注入到衬底110、第一半导体裸片120及第二半导体裸片122之间的空间中。注入底胶132以填充空间来减少在接合之后施加于接合结构上的应力。在一些实施例中，底胶132可包含聚合物(例如环氧树脂)或其它适合材料。在一些实施例中，底胶132可包含例如二氧化硅的填料以调整底胶132的机械强度。
半导体封装结构100a可包含经安置于衬底110的第二区域112b中的粘着材料134，如图2A中所展示。在一些实施例中，粘着材料134可包含例如散热膏、银浆或焊料的粘性凝胶或液体材料。在一些实施例中，例如间隔件或加强板的支撑元件(图中未展示)可被安置于衬底110上方。在一些实施例中，支撑元件通过粘着材料134附接到衬底110。
参考图2B，根据操作14，在第一区域112a(即，裸片区域112a)中界定第一区域114-1及第二区域114-2。在一些实施例中，将第一区域114-1界定为其中需要导热性的区域，而将第二区域114-2界定为其中需要粘着性的区域。应注意，可取决于不同产品要求来修改第一区域114-1及第二区域114-2的界定。例如，可将第一区域114-1界定为对应于第一半导体裸片120，且可将第二区域114-2界定为对应于第二半导体裸片122(如图2B中所展示)，但本公开不受限于此。
参考图2C，根据操作16，将第一TIM层142安置于第一区域114-1中，且将第二TIM层144安置于第二区域114-2中。因此，半导体封装结构100a包含经安置于多个半导体裸片120及122上方的多TIM结构140a。在一些实施例中，多TIM结构140a包含第一TIM层142及第二TIM层144。沿第二方向D2来布置第一TIM层142及第二TIM层144。在一些实施例中，第二方向D2相同于第一方向D1(如图2C中所展示)，但本公开不受限于此。在一些实施例中，第一TIM层142形成于多个半导体裸片中的一个(例如第一半导体裸片120)上，而第二TIM层144形成于多个第二半导体裸片中的另一个(例如第二半导体裸片122)上，但本公开不受限于此。
如图2C及图3中所展示，在一些实施例中，第一TIM层142及第二TIM层144彼此间隔气隙143。气隙143可进一步减少第一半导体裸片120与第二半导体裸片122之间的侧向热相互作用。然而，在一些实施例中，第一TIM层142及第二TIM层144可彼此接触，如图4中所展示。尽管图中未展示，但在其它实施例中，第一TIM层142可与第二TIM层144的一部分重叠，或反之亦然。
多TIM结构140a的第一TIM层142及第二TIM层144安置于第一半导体裸片120及第二半导体裸片122上。在一些实施例中，第一TIM层142及第二TIM层144的各者与第一半导体裸片120及第二半导体裸片122的顶面物理接触。在示范性实施例中，第一TIM层142及第二TIM层144各具有约20μm到约200μm之间的厚度，但本公开不受限于此。
接着参考图2D及图3，根据操作18，将散热器150安置于第一TIM层142及第二TIM层144上方。因此，半导体封装结构100a进一步包含与第一TIM层142及第二TIM层144接触的散热器(也指称盖)150。例如，散热器150可具有约200瓦特/米·克耳文(W/mK)到约400W/mK或更大之间的高导热系数且可使用金属、金属合金、石墨烯、碳纳米管(CNT)等等来形成。散热器150透过多TIM结构140a安装于且热耦合到第一半导体裸片120及第二半导体裸片122上方。多TIM结构140a不仅将散热器150耦合到第一半导体裸片120及第二半导体裸片122，且还有助于将由第一半导体裸片120及第二半导体裸片122产生的热量耗散到散热器150中。
值得注意的是，第一TIM层142的导热系数(Tk)不同于第二TIM层144的导热系数。例如，第一TIM层142的导热系数大于第二TIM层144的导热系数。在一些实施例中，第一TIM层142的导热系数大于约10W/mK，但本公开不受限于此。在一些实施例中，第二TIM层144的导热系数小于约10W/mK。在其它实施例中，第二TIM层144的导热系数小于约5W/mK，但本公开不受限于此。例如，第二TIM层144可以是具有约3W/mK到约5W/mK之间的导热系数的聚合物。第一TIM层142可包含具有导热填料的基底材料。在一些实施例中，基底材料可包含塑料、粘着剂、胶水、环氧树脂、聚合物、热塑性塑料、硅酮、滑脂、油脂、树脂等等的一或多个。导热填料可使第一TIM层142的导热系数增大到约10W/mK到约50W/mK或更大之间。适用导热填料可包含氧化铝(AlO)、氮化硼(BN)、氮化铝(AlN)、铝(Al)、铜(Cu)、银(Ag)、铟(In)、其组合等等。在其它实施例中，TIM层142可包含其它材料，例如包括Ag、铟浆等等的基于金属或基于焊料的材料。具有大于10W/mK的导热系数的第一TIM层142有助于更高效率地传递或耗散热量。例如，当在半导体裸片(例如CPU裸片)(其热输出大于存储器裸片)上方采用具有小于10W/mK的导热系数的TIM层时，无法实时传递或耗散由半导体裸片产生的热量且封装因此会遭受热机械应力。因此，会在半导体裸片与散热器之间或甚至在半导体裸片本身中出现破裂。
在一些实施例中，第一半导体裸片120包含第一热输出且第二半导体裸片122包含小于第一热输出的第二热输出。例如，当第一半导体裸片120是CPU裸片且第二半导体裸片122是存储器裸片时，第一半导体裸片120的第一热输出大于第二半导体裸片122的第二热输出。如上文所提及，界定为其中需要导热性的第一区域114-1还界定为对应于第一半导体裸片120。因此，安置于第一区域114-1中的具有较大导热系数的第一TIM层142还安置于第一半导体裸片120上，而具有较小导热系数但优选粘着性的第二TIM层144安置于第二半导体裸片122上。因此，可由第一TIM层142将由第一半导体裸片120产生的热量更高效率地耗散到散热器。
由于采用多TIM结构140a，所以将具有不同导热系数的TIM层142及144提供到具有不同热输出的半导体裸片120及122。因此，提高散热效率且使散热均匀，且因此可减少由热量引起的翘曲。
图5是绘示根据本公开的一或多个实施例的方面的半导体封装结构100b的示意图。应注意，图2C及图5中的类似元件由相同元件符号标示。此外，图2C及图5中的类似元件可包含类似材料且可通过方法10的操作12到18来形成；因此，为了简洁起见，省略此些冗余细节且仅提及差异。另外，从图5省略散热器150，然而，所属领域的技术人员将易于根据以上描述来了解散热器150的布置。在一些实施例中，半导体封装结构100a与半导体封装结构100b之间的差异在于：其中需要导热性的第一区域114-1界定于其中需要粘着性的两个第二区域114-2之间。此外，半导体封装结构100a与半导体封装结构100b之间的差异在于：半导体封装结构100b的TIM结构140b进一步包含第三TIM层146。
如图5中所展示，沿第一方向D1布置第一半导体裸片120及第二半导体裸片122。沿第二方向D2界定第一区域114-1及第二区域114-2，且第二方向D2可相同于第一方向D1，如图5中所展示。因此，沿相同方向D1/D2布置第一半导体裸片120及第二半导体裸片122、安置于第一区域114-1中的第一TIM层142及安置于第二区域114-2中的第二TIM层144及第三TIM层146。在一些实施例中，第一TIM层142、第二TIM层144及第三TIM层146彼此间隔气隙143，此可进一步减少第一半导体裸片120与第二半导体裸片122之间的侧向热相互作用。然而，在一些实施例中，第一TIM层142、第二TIM层144及第三TIM层146可彼此接触。在其它实施例中，第一TIM层142、第二TIM层144及第三TIM层146可彼此重叠。
在一些实施例中，第一TIM层142安置于第一区域114-1中，而第二TIM层144及第三TIM层146安置于第二区域114-2中。因此，从俯视视角看，第一TIM层142安置于第二TIM层144与第三TIM层146之间，如图5中所展示。在一些实施例中，第一TIM层142覆盖第一半导体裸片120的一部分及第二半导体裸片122的一部分，而第二TIM层144覆盖第一半导体裸片120的另一部分且第三TIM层146覆盖第二半导体裸片122的另一部分。在一些实施例中，第二TIM层144及第三TIM层146安置于裸片区域112a的至少四个隅角上方，如图5中所展示。此外，第二TIM层114覆盖第一半导体裸片120的两个隅角且第三TIM层146覆盖第二半导体裸片122的两个隅角。
在一些实施例中，第一TIM层142的导热系数大于第二TIM层144的导热系数。此外，第一TIM层142的导热系数还大于第三TIM层146的导热系数。在一些实施例中，第三TIM层146的导热系数可相同于第二TIM层144的导热系数。在其它实施例中，第二TIM层144及第三TIM层146的导热系数彼此不同。值得注意的是，TIM材料的粘着性与TIM材料的导热系数成反比。因此，具有较大导热系数的第一TIM层142具有较小粘着性。换句话说，第二TIM层144及第三TIM层146具有较小导热系数但较大粘着性。
如上文所提及，热量会引起3DIC封装结构的热应力及翘曲以导致连接器130破裂。在一些实施例中，翘曲似乎发生于裸片的周边处，尤其是隅角处；因此，将具有较大粘着性的第二TIM层144及第三TIM层146安置于第一区域112a的隅角处。因此，即使发生翘曲，但可通过第二TIM层144及第三TIM层146将第一半导体裸片120及第二半导体裸片122固定到散热器。同时，具有较大导热系数的第一TIM层142有助于将热量耗散到散热器150。
由于采用多TIM结构140b，所以将具有不同粘着性的TIM层142到146提供到暴露于不同应力的不同区域。因此，由第一TIM层142提高散热效率且减少由热量引起的翘曲，同时由第二TIM层144及第三TIM层146增强第一半导体裸片120及第二半导体裸片122与散热器之间的粘着性。
图6是绘示根据本公开的一或多个实施例的方面的半导体封装结构100c的示意图。应注意，图5及图6中的类似元件由相同元件符号标示。此外，图5及图6中的类似元件可包含类似材料且可通过方法10的操作12到18来形成；因此，为了简洁起见，省略此些冗余细节且仅提及差异。另外，从图6省略散热器150，然而，所属领域的技术人员将易于根据以上描述来了解散热器150的布置。在一些实施例中，半导体封装结构100b与半导体封装结构100c之间的差异在于：半导体封装结构100c的第一区域114-1及第二区域114-2的界定及多TIM结构140c的布置不同于半导体封装结构100b的第一区域114-1及第二区域114-2的界定及多TIM结构140b的布置。
在一些实施例中，半导体封装结构100c的多TIM结构140c包含第一TIM层142、第二TIM层144及第三TIM层146。沿第一方向D1布置第一半导体裸片120及第二半导体裸片122。沿第二方向D2界定第一区域114-1及第二区域114-2。因此，沿第二方向D2布置第一TIM层142、第二TIM层144及第三TIM层146。在一些实施例中，第二方向D2不同于第一方向D1，如图6中所展示。在一些实施例中，第一方向D1及第二方向D2彼此垂直，但本公开不受限于此。第一TIM层142与半导体裸片120及122的各者的一部分重叠，第二TIM层144与半导体裸片120及122的各者的另一部分重叠，且第三TIM层146与半导体裸片120及122的各者的其它部分重叠，但本公开不受限于此。在一些实施例中，第一TIM层142、第二TIM层144及第三TIM层146彼此间隔气隙143。气隙143可进一步减少第一半导体裸片120与第二半导体裸片122之间的侧向热相互作用。然而，在一些实施例中，第一TIM层142、第二TIM层144及第三TIM层146可彼此接触。在其它实施例中，第一TIM层142、第二TIM层144及第三TIM层146可彼此重叠。
在一些实施例中，第一TIM层142的导热系数大于第二TIM层144的导热系数。此外，第一TIM层142的导热系数还大于第三TIM层146的导热系数。在一些实施例中，第三TIM层146的导热系数可相同于第二TIM层144的导热系数。在其它实施例中，第二TIM层144及第三TIM层146的导热系数彼此不同。值得注意的是，TIM材料的粘着性与TIM材料的导热系数成反比。因此，具有较大导热系数的第一TIM层142具有较小粘着性。换句话说，第二TIM层144及第三TIM层146具有较小导热系数但较大粘着性。
如上文所提及，热量会引起3DIC封装结构的热应力及翘曲以导致连接器130破裂。在一些实施例中，观察到翘曲发生于裸片的周边处，尤其是隅角处。因此，具有较大粘着性的第二TIM层144及第三TIM层146安置于第一区域112a的周边上方。例如，第二TIM层144及第三TIM层146安置于第一区域112a的至少四个隅角上方，如图6中所展示。此外，第二TIM层144覆盖第一半导体裸片120的两个隅角及第二半导体裸片122的两个隅角，而第三TIM层146覆盖第一半导体裸片120的另两个隅角及第二半导体裸片122的另两个隅角，如图6中所展示。因此，第二TIM层144及第三TIM层146不仅将第一区域112a的全部隅角且还将第一半导体裸片120及第二半导体裸片122的全部隅角固定到散热器。同时，具有较大导热系数的第一TIM层142有助于将热量耗散到散热器150。
通过采用多TIM结构140c，将具有不同粘着性的TIM层142到146提供到暴露于不同应力的不同区域。因此，通过第一TIM层142来提高散热效率且减少由热量引起的翘曲，同时通过第二TIM层144及第三TIM层146来增强第一半导体裸片120及第二半导体裸片122与散热器之间的粘着性。
图7是绘示根据本公开的一或多个实施例的方面的半导体封装结构100d的示意图。应注意，图2C及图7中的类似元件是由相同元件符号标示。此外，图2C及图7中的类似元件可包含类似材料，且可通过方法10的操作12到18来形成；因此，为了简洁起见，省略此些冗余细节且仅提及差异。另外，从图7省略散热器150，然而，所属领域的技术人员将易于根据以上描述来了解散热器150的布置。在一些实施例中，半导体封装结构100a与半导体封装结构100d之间的差异在于：半导体封装结构100d的第一区域114-1及第二区域114-2的界定及多TIM结构140d的布置不同于半导体封装结构100a的第一区域114-1及第二区域114-2的界定及多TIM结构140a的布置。在一些实施例中，第二区域114-2经界定为包围第一区域114-1，如图7中所展示。在一些实施例中，第一区域114-1经界定于裸片区域(第一区域)112a的中心中，而第二区域114-2则经界定于裸片区域112a的周边中。
如图7中所展示，半导体封装结构100d的多TIM结构140d包含经安置于第一区域114-1中的第一TIM层142及经安置于第二区域114-2中的第二TIM层144。然而，可调整TIM层的数量来满足不同产品要求。因此，第一TIM层142安置于第一区域112a的中心中，且TIM层144安置于第一区域112a的周边中。如图7中所展示，从俯视视角看，第二TIM层144包围第一TIM层142，但本公开不受限于此。此外，第二TIM层144不仅覆盖第一区域112a的隅角，且还覆盖第一区域112a的整个周边，如图7中所展示。在一些实施例中，第一TIM层142及第二TIM层144彼此间隔气隙143。然而，在一些实施例中，第一TIM层142及第二TIM层144可彼此接触。在其它实施例中，尽管图中未展示，但第一TIM层142可与第二TIM层144的一部分重叠，或反之亦然。
在一些实施例中，第一TIM层142的导热系数大于第二TIM层144的导热系数。因此，定位于第一区域112a的中心中的第一TIM层142用于将热量耗散到散热器中。如上文所提及，TIM材料的粘着性与TIM材料的导热系数成反比；因此，具有较大导热系数的第一TIM层142具有较小粘着性。换句话说，第二TIM层144具有较小导热系数但较大粘着性。在一些实施例中，第二TIM层144安置于第一区域112a的周边上方。因此，即使发生翘曲，但可将第一半导体裸片120及第二半导体裸片122固定到散热器150。
由于采用多TIM结构140d，所以将具有不同粘着性的TIM层142及144提供到暴露于不同应力的不同区域。因此，由第一TIM层142提高散热效率且减少翘曲，同时由第二TIM层144增强第一半导体裸片120及第二半导体裸片122与散热器之间的粘着性。
图8是绘示根据本公开的一或多个实施例的方面的半导体封装结构100e的示意图。应注意，图7及图8中的类似元件由相同元件符号标示。此外，图7及图8中的类似元件可包含类似材料且可通过方法10的操作12到18来形成；因此，为了简洁起见，仅提及差异。在一些实施例中，半导体封装结构100d与半导体封装结构100e之间的差异在于半导体封装结构100e的第一区域114-1及第二区域114-2的界定及多TIM结构140e的布置。如图8中所展示，第二区域114-2包围第一区域114-1。在一些实施例中，第一区域114-1经界定于裸片区域(第一区域)112a的中心中，而第二区域114-2经界定于裸片区域112a的周边中。此外，第一区域114-1界定为对应于第一半导体裸片120，如图8中所展示。另外，从图8省略散热器150；然而，所属领域的技术人员将易于根据以上描述来了解散热器150的布置。在一些实施例中，半导体封装结构100e包含多个半导体裸片。例如，半导体封装结构100e包含例如CPU裸片的至少第一半导体裸片120及例如HBM裸片的多个第二半导体裸片122。第一半导体裸片120及第二半导体裸片122安置于衬底110的第一区域112a中。在一些实施例中，从俯视视角看，第二半导体裸片122安置于第一半导体裸片120的两侧处(如图8中所展示)，但本公开不受限于此。第一半导体裸片120可包含第一热输出且第二半导体裸片122可包含第二热输出。如上文所提及，第一半导体裸片120(即，CPU裸片)的第一热输出大于第二半导体裸片122(即，HBM裸片)的第二热输出。
仍参考图8，半导体封装结构100e的多TIM结构140e包含第一TIM层142及第二TIM层144。然而，可调整TIM层的数量以满足不同产品要求。在一些实施例中，从俯视视角看，第一TIM层142安置于第一区域112a的中心中的第一区域114-1中且第二TIM层144安置于第一区域112a的周边中的第二区域114-2中以包围第一TIM层142。此外，第一区域114-1中的第一TIM层142覆盖第一半导体裸片120，而第二区域114-2中的第二TIM层144覆盖第二半导体裸片122，如图8中所展示。在一些实施例中，第二TIM层144覆盖第一半导体裸片120的隅角及第二半导体裸片122的隅角，但本公开不受限于此。在一些实施例中，第一TIM层142及第二TIM层144彼此间隔气隙143。然而，在一些实施例中，第一TIM层142及第二TIM层144可彼此接触。在其它实施例中，尽管图中未展示，但第一TIM层142可与第二TIM层144的一部分重叠，或反之亦然。
在一些实施例中，第一TIM层142的导热系数大于第二TIM层144的导热系数。因此，安置于具有较大热输出的第一半导体裸片120上方的第一TIM层142用于将较多热量耗散到散热器中。如上文所提及，TIM材料的粘着性与TIM材料的导热系数成反比。因此，具有较大导热系数的第一TIM层142具有较小粘着性。换句话说，第二TIM层144具有较小导热系数但较大粘着性。如图8中所展示，第二TIM层144安置于暴露于较大应力的第一区域112a的周边上方。由于第二半导体裸片122的第二热输出小于第一热输出，所以第二TIM层144具有足以将热量耗散到散热器中的导热系数，同时满足周边的粘着性要求。因此，即使发生翘曲，但可通过第二TIM层144将第一半导体裸片120及第二半导体裸片122固定到散热器。
由于采用多TIM结构140e，所以将具有不同导热系数的TIM层142及144提供到具有不同热输出的半导体裸片120及122。因此，由第一TIM层142提高散热效率及使散热均匀且因此减少翘曲。此外，将具有不同粘着性的TIM层142及144提供到暴露于不同应力的不同区域。因此，由第二TIM层144增强第一半导体裸片120/第二半导体裸片122与散热器之间的粘着性。
因此，本公开提供一种半导体封装结构，其包含多TIM结构。在一些实施例中，所述多TIM结构包含具有不同导热系数及粘着性的至少两个TIM层。在一些实施例中，所述多TIM结构包含取决于施加于所述半导体封装结构的应力的不同TIM层。例如，所述多TIM结构可包含暴露于较大应力的区域中的具有较大粘着性的TIM层及接收较小应力的其它区域中的具有较小粘着性的另一TIM层。在一些实施例中，所述多TIM结构包含取决于操作期间所产生的热量的不同TIM层。例如，所述多TIM结构可包含容纳产生较多热量的裸片的区域中的具有较大导热系数的TIM层及容纳产生较少热量的裸片的区域中的具有较小导热系数的另一TIM层。
本公开提供一种半导体结构，其包含：衬底；多个半导体裸片，其位于所述衬底上方；及多TIM结构，其位于所述多个半导体裸片上方。所述多TIM结构包含第一TIM层及第二TIM层。所述第一TIM层的导热系数不同于所述第二TIM层的导热系数。
在一些实施例中，提供一种半导体封装结构。所述半导体封装结构包含：衬底；第一半导体裸片及第二半导体裸片，其位于所述衬底上方；及多TIM结构，其位于所述第一半导体裸片及所述第二半导体裸片上方。所述第一半导体裸片包含第一热输出且所述第二半导体裸片包含小于所述第一热输出的第二热输出。所述多TIM结构包含安置于所述第一半导体裸片的至少一部分上方的第一TIM层及第二TIM层。所述第一TIM层的导热系数大于所述第二TIM层的导热系数。
在一些实施例中，提供一种用于形成半导体封装结构的方法。所述方法包含以下操作。接收包含裸片区域及安置于所述裸片区域中的第一半导体裸片及第二裸片的衬底。在所述裸片区域中界定其中需要导热性的第一区域及其中需要粘着性的第二区域。将第一TIM层安置于所述第一区域中且将第二TIM层安置于所述第二区域中。在一些实施例中，所述第一TIM层的导热系数大于所述第二TIM层的导热系数，且所述第二TIM层的粘着性大于所述第一TIM层的粘着性。
上文已概述若干实施例的特征，使得所属领域的技术人员可优选理解本公开的方面。所属领域的技术人员应了解，其可易于将本公开用作用于设计或修改用于实施相同目的及/或达成本文中所引入的实施例的相同优点的其它过程及结构的基础。所属领域的技术人员还应认知，此些等效构建不应背离本公开的精神及范围，且其可在不背离本公开的精神及范围的情况下对本文作出各种改变、替换及更改。
符号说明
10 方法
12 操作
14 操作
16 操作
18 操作
100a 半导体封装结构
100b 半导体封装结构
100c 半导体封装结构
100d 半导体封装结构
100e 半导体封装结构
110 衬底
112a 第一区域/裸片区域
112b 第二区域
114-1 第一区域
114-2 第二区域
120 第一半导体裸片
122 第二半导体裸片
130 连接器
132 底胶
134 粘着材料
140a 多热接口材料(TIM)结构
140b 多TIM结构
140c 多TIM结构
140d 多TIM结构
140e 多TIM结构
142 第一TIM层
143 气隙
144 第二TIM层
146 第三TIM层
150 散热器
D1 第一方向
D2 第二方向

Claims (18)

1.一种半导体封装结构，其包括：
衬底；
多个半导体裸片，其位于所述衬底上方；及
多TIM结构，其位于所述多个半导体裸片上方，
其中所述多TIM结构包括第一TIM层及第二TIM层，所述第一TIM层的导热系数(Tk)不同于所述第二TIM层的导热系数，所述第一TIM层与所述多个半导体裸片中的各者的一部分重叠，且所述第二TIM层与所述多个半导体裸片中的各者的另一部分重叠。
2.根据权利要求1所述的半导体封装结构，其中所述第一TIM层与所述第二TIM层间隔气隙。
3.根据权利要求1所述的半导体封装结构，其中所述第一TIM层与所述第二TIM层接触。
4.根据权利要求1所述的半导体封装结构，其中从俯视视角看，所述第二TIM层包围所述第一TIM层。
5.根据权利要求1所述的半导体封装结构，其中沿第一方向布置所述多个半导体裸片，且沿不同于所述第一方向的第二方向布置所述第一TIM层及所述第二TIM层。
6.根据权利要求1所述的半导体封装结构，其中沿相同方向布置所述多个半导体裸片、所述第一TIM层及所述第二TIM层。
7.根据权利要求1所述的半导体封装结构，其中所述多TIM结构进一步包括第三TIM层，且从俯视视角看，所述第一TIM层安置于所述第二TIM层与所述第三TIM层之间。
8.一种半导体封装结构，其包括：
衬底；
第一半导体裸片及第二半导体裸片，其经安置于所述衬底上方，其中所述第一半导体裸片包含第一热输出，且所述第二半导体裸片包含小于所述第一热输出的第二热输出；及
多TIM结构，其经安置于所述第一半导体裸片及所述第二半导体裸片上方，所述多TIM结构包括经安置于所述第一半导体裸片的至少一部分上方的第一TIM层及第二TIM层，
其中所述第一TIM层的导热系数大于所述第二TIM层的导热系数。
9.根据权利要求8所述的半导体封装结构，其中所述第一TIM层的所述导热系数大于10W/mK。
10.根据权利要求8所述的半导体封装结构，其中所述第二TIM层的所述导热系数小于10W/mK。
11.根据权利要求8所述的半导体封装结构，其中所述第一TIM层包括基底材料及导热填料，所述基底材料包括聚合物或树脂，且所述导热填料包括氧化铝(AlO)、氮化硼(BN)、氮化铝(AlN)、铝(Al)、铜(Cu)、银(Ag)或铟(In)。
12.根据权利要求8所述的半导体封装结构，其中所述第二TIM层包括聚合物。
13.根据权利要求8所述的半导体封装结构，其中所述第一TIM层的粘着性不同于所述第二TIM层的粘着性。
14.根据权利要求8所述的半导体封装结构，进一步包括经安置于所述多TIM结构上方且与所述多TIM结构接触的散热器。
15.一种用于形成半导体封装结构的方法，其包括：
接收包括裸片区域及经安置于所述裸片区域中的第一半导体裸片及第二半导体裸片的衬底；
在所述裸片区域中界定其中需要导热性的第一区域及其中需要粘着性的第二区域；及
将第一TIM层安置于所述第一区域中，且将第二TIM层安置于所述第二区域中，
其中所述第一TIM层的导热系数大于所述第二TIM层的导热系数，所述第二TIM层的粘着性大于所述第一TIM层的粘着性，且所述第二TIM层安置于所述第一区域的隅角上方。
16.根据权利要求15所述的方法，其中所述第二区域包围所述第一区域。
17.根据权利要求15所述的方法，其中所述第一半导体裸片包含第一热输出，所述第二半导体裸片包含小于所述第一热输出的第二热输出，且所述第一区域经界定为对应于所述第一半导体裸片。
18.根据权利要求15所述的方法，进一步包括：将散热器安置于所述第一TIM层及所述第二TIM层上方，其中所述散热器与所述第一TIM层及所述第二TIM层接触。
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