CN110534425B - Deep silicon etching method, deep silicon groove structure and semiconductor device - Google Patents
Deep silicon etching method, deep silicon groove structure and semiconductor device Download PDFInfo
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- CN110534425B CN110534425B CN201811087025.4A CN201811087025A CN110534425B CN 110534425 B CN110534425 B CN 110534425B CN 201811087025 A CN201811087025 A CN 201811087025A CN 110534425 B CN110534425 B CN 110534425B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
Abstract
The invention discloses a deep silicon etching method, a deep silicon groove junction and a semiconductor device. The method comprises the following steps: step 1, inputting deposition into a reaction chamberGas, glow starting and depositing; step 2, starting to introduce etching gas, and reducing the electrode power P Initiation of Carrying out physical bombardment; step 3, carrying out chemical etching on the substrate; step 4, judging whether the current cycle number reaches the total cycle number, if so, ending the process, otherwise, circularly executing the step 1 to the step 3, wherein after the cycle number reaches the initial cycle number, the current deposition time is increased, and/or the current lower electrode power is increased; and keeping the etching time unchanged when the step 3 is executed. According to the invention, through the progressive deposition time in the deposition step and the progressive lower electrode power in the physical bombardment step, a deep silicon groove structure with deeper depth, higher verticality and smaller bottom fillet can be manufactured, and the deep silicon groove structure is beneficial to device processing and can improve the product yield.
Description
Technical Field
The invention relates to the field of manufacturing of semiconductor integrated circuits or discrete devices, in particular to a deep silicon etching method, a deep silicon groove structure and a semiconductor device.
Background
In the field of microelectronics, deep silicon etching is an important process in the device processing process. For example, etching a trench gate in a transistor can inhibit the short channel effect of a device, solve the problems of mobility reduction caused by channel electron scattering and the like, and etching a super junction in the transistor can effectively reduce the on-resistance and improve the switching rate of the device, and then etching a Through Silicon Via (TSV) structure in advanced packaging can improve the performance of the device, reduce the power consumption and reduce the volume of the device.
Because deep silicon etching has a large depth-to-width ratio, the traditional wet etching process cannot be realized, and a dry etching process is required. Dry etching is a technique based on low-temperature plasma, and the process is accompanied by physical bombardment and chemical reaction. Since the chemical reaction is an isotropic etching process, the bottom topography of the process will appear as a circular arc, i.e., a rounded bottom corner. Such bottom rounded corners should be avoided during device design, for example, if the bottom rounded corners occur in the TSV process, the on-resistance of the device may be increased, and even abnormal open-circuit of the device may be caused.
In the conventional deep silicon etching (BOSCH) process, an etch stop layer is used, and after the etching reaches an end point, lateral etching is continued to reduce a bottom rounded corner, and the etching result is shown in fig. 1a and 1 b. However, the lateral etching in this method is difficult to control, and once over-etching will generate an abnormal profile of lateral undercutting, as shown in fig. 1 c.
The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.
Disclosure of Invention
In order to solve the technical problems in the prior art, the invention provides a deep silicon etching method, a deep silicon trench structure and a semiconductor device comprising the deep silicon trench structure.
According to one aspect of the invention, a deep silicon trench etching method is provided, which comprises the following steps:
Step 2, stopping inputting the deposition gas, starting to introduce the etching gas, and reducing the electrode power P Initiation of Carrying out physical bombardment;
step 3, continuously introducing etching gas to carry out chemical etching on the substrate for etching time t Etching of Then stopping introducing the etching gas;
step 4, judging whether the current cycle number reaches the total cycle number, if so, ending the process, otherwise, circularly executing the step 1 to the step 3, wherein after the cycle number reaches the initial cycle number, when the step 1 is executed, the current deposition time is increased on the basis of the deposition time executed last time, and/or when the step 2 is executed, the current lower electrode power is increased on the basis of the lower electrode power executed last time; and keeping the etching time unchanged when the step 3 is executed.
Preferably, after the number of cycles reaches the initial number of cycles, when the step 1 is performed, the current deposition time is increased by a first preset value on the basis of the deposition time last performed, and/or when the step 2 is performed, the current lower electrode power is increased by a second preset value on the basis of the lower electrode power last performed.
Preferably, said first preset value is a function of said deposition time t Initiation of A predetermined deposition termination time t Terminate And a preset total cycle number n General assembly Calculating and obtaining a preset relation between the two;
the second preset value is based on the lower electrode power P Initiation of Presetting the lower electrode power P Terminate And a preset total cycle number n General assembly And calculating to obtain the preset relational expression between the two.
Preferably, the deposition time in step 1 is increased stepwise from 3.5s to 6 s.
Preferably, the lower electrode power P in the step 2 Initiation of Not less than 100W.
Preferably, the lower electrode power P in the step 2 Initiation of Gradually increased from 100W to 120W.
Preferably, the execution time of step 2 is not greater than 2 s.
Preferably, the etching time t in the step 3 Etching of Between 1s and 5 s.
According to another aspect of the present invention, a deep silicon trench structure is provided, which is etched by using the deep silicon etching method as described above.
According to a further aspect of the present invention, a semiconductor device is proposed, which comprises a deep silicon trench structure as described above.
The invention has the following beneficial technical effects:
the invention circularly executes the deposition step, the physical bombardment step and the chemical etching step, and can manufacture the deep silicon groove structure with deeper depth, higher verticality and smaller bottom fillet through the progressive deposition time in the deposition step and the progressive lower electrode power in the physical bombardment step.
The method of the present invention has other features and advantages which will be apparent from or are set forth in detail in the accompanying drawings and the following detailed description, which are incorporated herein, and which together serve to explain certain principles of the invention.
Drawings
The above and other objects, features and advantages of the present invention will become more apparent by describing in detail exemplary embodiments thereof with reference to the attached drawings, wherein like reference numerals generally represent like parts in the exemplary embodiments of the present invention.
FIGS. 1 a-1 c show the bottom features of a deep silicon trench etched by an etch stop layer method in the prior art;
FIG. 2 shows a flow diagram of a method of deep silicon etching according to an example embodiment of the invention;
FIGS. 3 a-3 e illustrate etch results of a deep silicon etch method according to an exemplary embodiment of the present invention;
fig. 4 shows a schematic view of the substrate area division of fig. 3 a-3 e.
Detailed Description
The invention will be described in more detail below with reference to the accompanying drawings. While the preferred embodiments of the present invention are shown in the drawings, it should be understood that the present invention may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
Fig. 2 is a flowchart illustrating a deep silicon etching method according to an exemplary embodiment of the present invention. As shown in fig. 2, the method includes:
Step 2, stopping inputting the deposition gas, starting to introduce the etching gas, and reducing the electrode power P Initiation of Carrying out physical bombardment;
step 3, continuously introducing etching gas to carry out chemical etching on the substrate for etching time t Etching of Then stopping introducing etching gas;
step 4, judging whether the current cycle number reaches the total cycle number, if so, ending the process, otherwise, circularly executing the step 1 to the step 3, wherein after the cycle number reaches the initial cycle number, when the step 1 is executed, the current deposition time is increased on the basis of the deposition time executed last time, and/or when the step 2 is executed, the current lower electrode power is increased on the basis of the lower electrode power executed last time; and keeping the etching time unchanged when the step 3 is executed.
The dry etching process is accompanied by physical bombardment and chemical reaction, and the bottom appearance of the process is in a circular arc shape due to the isotropy of the chemical reaction, namely, a bottom fillet is generated, and the bottom fillet is avoided in the design of some devices.
In order to solve the problem, the bottom fillet of deep silicon etching is directly reduced by optimizing the BOSCH process formula on the premise that the hardware condition of the etching machine is not changed. The etching process of the invention is divided into three steps, specifically a deposition step, a physical bombardment step and a chemical etching step, which are alternately carried out according to the cycle times. In the whole etching process, the program (recipe) of the chemical etching part is kept unchanged, and after the cycle number reaches the set initial cycle number, the following improvements are made in the programs of the deposition step and the physical bombardment step: the physical bombardment step uses larger lower electrode power, preferably not less than 100W; and gradually increasing the lower electrode power of the physical bombardment step to enable more plasmas to enter the bottom of the deep silicon groove, and gradually prolonging the deposition time of the deposition step to keep the side wall verticality.
Specifically, when step 1 is executed, increasing the current deposition time by a first preset value on the basis of the deposition time executed last time; and/or when step 2 is executed, increasing the current lower electrode power by a second preset value on the basis of the lower electrode power executed last time; and the etching time is kept unchanged when step 3 is performed.
Wherein the first preset value is determined according to the deposition time t Initiation of Presetting a deposition termination time t Terminate And a preset total cycle number n General (1) In a preset off stateIs obtained by calculation of the following formula (1):
Δt＝(t terminate –t Initiation of )/(n General assembly -n First stage ) (1)。
The second preset value is based on the lower electrode power P Initiation of Presetting the lower electrode power P Terminate And a preset total cycle number n General (1) The preset relation between the two is calculated to obtain:
ΔP＝(P terminate –P Initiation of )/(n General assembly -n First stage ) (2).
Wherein the total number of cycles n General assembly Including reaching an initial number of cycles n First stage The number of cycles of the front lower electrode power and the single step deposition time are kept unchanged and the number n of initial cycles is reached First stage The power of the back lower electrode and the deposition time of a single step are gradually changed. The initial cycle number and the total cycle number can be determined according to the specific requirements of the etched deep silicon groove.
In this embodiment, the deposition time in step 1 may be increased stepwise from 3.5s to 6 s. That is, the initial deposition time may be set to 3.5s, the deposition time is increased by the first preset value every cycle after the number of cycles reaches the initial number of cycles, and the etching time may reach 6s at the end of the process. In this way, the verticality of the etched side wall of the deep silicon trench can be maintained.
The power of the lower electrode for physical bombardment in the step 2 is not less than 100W, and can be gradually increased from 100W to 120W. That is, the lower electrode power P is initiated Initiation of The power of the electrode can be set to be 100W, after the number of cycles reaches the initial number of cycles, the power of the electrode is increased by a second preset value every cycle, and the power of the electrode can reach 120W at the end of the process.
The execution time of step 2 is not more than 2s, i.e. the physical bombardment is not more than 2s, preferably 1.2 s.
Etching time t in step 3 Etching of The supply of etching gas can be stopped between 1s and 5s, i.e. between 1s and 5s, preferably 3.6 s.
Exemplary process parameters for the process steps of this example are shown in the following table.
TABLE 1
The invention also provides a deep silicon groove structure which is etched by using the deep silicon etching method so as to manufacture the deep silicon groove structure with deeper depth, higher verticality and smaller bottom fillet.
Preferably, the depth of the deep silicon trench structure is greater than 100 μm, the verticality is 90 ° ± 2 °, and the bottom fillet height accounts for less than 10% of the trench depth, i.e. the bottom fillet height from the bottom plane < target depth x 10%.
The resulting deep silicon trench structure etched using the deep silicon trench etching method according to an exemplary embodiment of the present invention is shown in fig. 3 a-3 e. 3 a-3 e are the deep silicon trench profile of the substrate divided into five regions, i.e., upper, middle, lower, left, and right regions, respectively. Fig. 4 shows a schematic view of the substrate area division of fig. 3 a-3 e.
The data statistics for fig. 3 a-3 e are shown in the following table:
TABLE 2
The invention also provides a device comprising the deep silicon groove structure, such as a groove gate IGBT, a groove gate MOSFET, a groove gate JFET, a capacitor and the like. According to the deep silicon groove structure, the depth is deep, the verticality is high, the bottom fillet is small, device processing is facilitated, and the product yield can be improved.
Having described embodiments of the present invention, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen in order to best explain the principles of the embodiments, the practical application, or improvements made to the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
Claims (8)
1. A deep silicon etching method is characterized by comprising the following steps:
step 1, inputting deposition gas into a reaction chamber, starting to deposit, wherein the deposition time is t Initiation of ；
Step 2, stopping inputting the deposition gas, starting to introduce the etching gas, and reducing the electrode power P Initiation of Carrying out physical bombardment;
step 3, continuously introducing etching gas to carry out chemical etching on the substrate for etching time t Etching of Then stopping introducing etching gas;
step 4, judging whether the current cycle number reaches the total cycle number, if so, ending the process, otherwise, circularly executing the step 1 to the step 3, wherein after the cycle number reaches the initial cycle number, when the step 1 is executed, the current deposition time is increased on the basis of the deposition time executed last time, and when the step 2 is executed, the current lower electrode power is increased on the basis of the lower electrode power executed last time; keeping the etching time unchanged when the step 3 is executed;
wherein, in the step 4, the deposition time of the step 1 is gradually increased from 3.5s to 6s after the cycle number reaches the initial cycle number.
2. The deep silicon etching method according to claim 1, wherein in the step 4,
after the cycle number reaches the initial cycle number, when the step 1 is executed, increasing the current deposition time by a first preset value on the basis of the deposition time executed last time, and when the step 2 is executed, increasing the current lower electrode power by a second preset value on the basis of the lower electrode power executed last time;
wherein the first preset value is based on the weightProduct time t Initiation of Presetting a deposition termination time t Terminate And a preset total cycle number n General assembly Calculating a preset relational expression between the two groups;
the second preset value is based on the lower electrode power P Initiation of Presetting the lower electrode power P Terminate And a preset total cycle number n General assembly And calculating to obtain the preset relational expression.
3. The deep silicon etching method according to claim 1, wherein in the step 2, the lower electrode power P is Initiation of Not less than 100W.
4. The method of claim 3, wherein in the step 4, the power of the lower electrode in the step 2 is gradually increased from 100W to 120W after the number of cycles reaches the initial number of cycles.
5. The deep silicon etching method as claimed in claim 1, wherein the execution time of step 2 is not more than 2 s.
6. The deep silicon etching method as claimed in claim 1, wherein the etching time t in the step 3 is Etching of Between 1s and 5 s.
7. A deep silicon trench structure characterized in that etching is performed by the deep silicon etching method as claimed in any one of claims 1 to 6.
8. A semiconductor device comprising the deep silicon trench structure of claim 7.
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