CN110532220A - AES based on UVM verification methodology verifies device - Google Patents
AES based on UVM verification methodology verifies device Download PDFInfo
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- CN110532220A CN110532220A CN201910712530.1A CN201910712530A CN110532220A CN 110532220 A CN110532220 A CN 110532220A CN 201910712530 A CN201910712530 A CN 201910712530A CN 110532220 A CN110532220 A CN 110532220A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/263—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/76—Architectures of general purpose stored program computers
- G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
- G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
- G06F15/7871—Reconfiguration support, e.g. configuration loading, configuration switching, or hardware OS
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols the encryption apparatus using shift registers or memories for block-wise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
- H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
- H04L9/0631—Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms
Abstract
Disclose the AES verifying device based on UVM verification methodology, the device includes: sequence generation module, register model, adapter, AHB System Agent, ahb bus interface, ahb bus Input Monitor Connector agency, ahb bus output monitor agent, AES the reference module and scoring board, AES is connect with ahb bus and the AES includes AES internal register, and the sequence generation module is configured as generating the test vector sequence of randomization；Register model receives the test vector sequence and maps AES internal register；The test vector sequence is converted to the identifiable AHB sequence of the AHB System Agent by adapter；AHB System Agent includes that AHB sequence transmitter and ahb bus drive；Ahb bus interface operation information is sent to the aes algorithm model of the AES the reference module, and the calculated result of the aes algorithm model is sent to scoring board；The operation result of AES is output to the scoring board by the ahb bus output monitor agent；Scoring board is compared to verify AES the calculated result of aes algorithm model and the operation result of AES.
Description
Technical field
This disclosure relates to which communication technique field more particularly to a kind of AES based on UVM verification methodology verify device.
Background technique
Moore's Law points out that the open ended transistor size of integrated chip will about be doubled every 18 months, performance
Promote one times.With the improvement of semiconductor fabrication process, the appearance of extensive system on chip SOC and multi core design are dedicated integrated
The complexity of chip design is increased with exponential form, this to verify work as the bottleneck in chip design cycle.In design
There is an urgent need to have new techniques and methodology in terms of functional verification for the raising of complexity.
AES technology is that a kind of symmetrical block encryption technology is provided using 128 block encryption data and compared WEP/TKIPS
The higher encryption intensity of RC4 algorithm.The encryption code table reconciliation cipher table of AES is separated, and sub-key is supported to encrypt, this
Kind way is better than in the past with the way of a special key decryption.Aes algorithm supports any packet size, initial time fast.
Processor resource can be effectively utilized in the concurrency that especially it has.Due to there is a large amount of operation and a variety of inside AES
The switching of mode needs just to can guarantee the coverage rate of code and the coverage rate of function by the trial of a large amount of different data, from
And realize the raising of verification quality.
Generic validation methodology (Universal Verification Methodology, UVM) be one with
Verification platform Development Framework based on SystemVerilog class libraries, verifying engineer can use the building of its Reusable Module
Functional verification environment with standardization hierarchical structure and interface.
However, traditional verification method is to build simple verification platform using verilog, excitation is directly write.It is this
Method reusability is low, and verification efficiency is low and cumbersome.
Summary of the invention
In view of this, the embodiment of the present disclosure provides a kind of AES verifying device based on UVM verification methodology, at least portion
Decompose problems of the prior art of determining.
According to the one aspect of the embodiment of the present disclosure, a kind of AES verifying device based on UVM verification methodology is provided,
The device includes sequence generation module, register model, adapter, AHB System Agent, ahb bus interface, ahb bus input
Monitor agent, ahb bus output monitor agent, AES the reference module and scoring board, the AES and the ahb bus interface connect
It connects and the AES includes AES internal register, wherein
The sequence generation module is configured as generating the test vector sequence of randomization, and the test vector sequence includes
To the read-write operation of AES internal register；
The register model receives the test vector sequence and maps AES internal register；
The test vector sequence is converted to the identifiable AHB sequence of the AHB System Agent by the adapter；
The AHB System Agent includes that AHB sequence transmitter and ahb bus drive, and the AHB sequence transmitter will be described
AHB sequence is sent to the ahb bus driving and is written and read with controlling the ahb bus interface to AES internal register；
The ahb bus Input Monitor Connector agency receives ahb bus interface operation information, and the ahb bus interface is grasped
The aes algorithm model of the AES the reference module is sent to as information, the calculated result of the aes algorithm model is sent to institute
State scoring board；
The operation result of AES is output to the scoring board by the ahb bus output monitor agent；And
The scoring board is compared to test the calculated result of the aes algorithm model and the operation result of the AES
Demonstrate,prove the AES.
According to a kind of specific implementation of the embodiment of the present disclosure, described device further include:
Coverage rate collection module, the coverage rate collection module include that coverage rate collects model, and the coverage rate collects mould
Type is used for statistical function coverage rate.
According to a kind of specific implementation of the embodiment of the present disclosure, described device further include:
Virtual sequence sending module, the test vector sequence that the sequence generation module generates are sent out via the virtual sequence
Module is sent to be sent to the register model, to operate to AES internal register.
According to a kind of specific implementation of the embodiment of the present disclosure, the register model is generated by writing script, institute
It states script and reads in the table containing AES internal register information, and corresponding register model is generated according to the content of table.
According to a kind of specific implementation of the embodiment of the present disclosure, the AES the reference module includes the conversion of AHB configuration information
Ahb bus interface operation information is converted into aes algorithm mould by module and aes algorithm model, the AHB configuration information conversion module
The identifiable input data of type, the input data are sent to the scoring board by the calculating of aes algorithm model.
According to a kind of specific implementation of the embodiment of the present disclosure, the ahb bus interface is defined by the interface of SV
Virtual interface configuration, and for AHB sequence to be transferred to AES and the operation result of AES is output to the scoring board.
According to a kind of specific implementation of the embodiment of the present disclosure, the test vector sequence of the randomization includes secret key bits
The encrypted work mode of wide, plaintext, encryption or decryption and AES.
According to a kind of specific implementation of the embodiment of the present disclosure, the test vector sequence includes depositing to the inside AES
The read operation of device and write operation, and the method by calling adapter inner different realizes different read operation and write operation.
It is described suitable after completing the read operation and write operation according to a kind of specific implementation of the embodiment of the present disclosure
Orchestration gives true AES internal register operational feedback to the register model, and the information that AES internal register is operated turns
It changes the identifiable format of the register model into, modifies the value inside register model, so that deposit inside true AES
Device value and the value of register model are consistent.
According to a kind of specific implementation of the embodiment of the present disclosure, after the completion of the verification process of AES verifying device,
Pass through the key message of script crawl log.
The AES based on UVM verification methodology in the embodiment of the present disclosure verifies device, including sequence generation module, deposit
Device model, adapter, AHB System Agent, ahb bus interface, ahb bus Input Monitor Connector agency, ahb bus output monitoring generation
Reason, AES the reference module and scoring board, the AES is connect with the ahb bus interface and the AES includes to post inside AES
Storage, wherein the sequence generation module is configured as generating the test vector sequence of randomization, the test vector sequence packet
Containing the read-write operation to AES internal register；The register model receives the test vector sequence and maps and posts inside AES
Storage；The test vector sequence is converted to the identifiable AHB sequence of the AHB System Agent by the adapter；The AHB
System Agent includes that AHB sequence transmitter and ahb bus drive, and the AHB sequence is sent institute by the AHB sequence transmitter
Ahb bus driving is stated to be written and read AES internal register to control the ahb bus interface；The ahb bus input
Monitor agent receives ahb bus interface operation information, and sends the AES for the ahb bus interface operation information and refer to
The calculated result of the aes algorithm model of module, the aes algorithm model is sent to the scoring board；The ahb bus output
The operation result of AES is output to the scoring board by monitor agent；And calculating of the scoring board to the aes algorithm model
As a result it is compared with the operation result of the AES to verify the AES.By the scheme of the disclosure, due to having used UVM to test
Methodology is demonstrate,proved, even if AES function is modified, also only needs simply adjustment test case setting that can continue to use, greatly improves
The reusability of verification environment.In addition, the method for the embodiment of the present disclosure uses a large amount of arbitrary excitation, it is randomly provided AES's
Register configuration, while the automatic comparison with reference model is realized, and realize the statistics of function coverage, finally use
Script extracts the key message of log, improves the reliability of functional verification.
Detailed description of the invention
It, below will be to needed in the embodiment attached in order to illustrate more clearly of the technical solution of the embodiment of the present disclosure
Figure is briefly described, it should be apparent that, the accompanying drawings in the following description is only some embodiments of the present disclosure, for this field
For those of ordinary skill, without creative efforts, it can also be obtained according to these attached drawings other attached drawings.
Fig. 1 is the block diagram for the verification environment that the embodiment of the present disclosure provides；And
Fig. 2 is the block diagram that the AES based on UVM verification methodology that the embodiment of the present disclosure provides verifies device.
Specific embodiment
The embodiment of the present disclosure is described in detail with reference to the accompanying drawing.
Illustrate embodiment of the present disclosure below by way of specific specific example, those skilled in the art can be by this specification
Disclosed content understands other advantages and effect of the disclosure easily.Obviously, described embodiment is only the disclosure
A part of the embodiment, instead of all the embodiments.The disclosure can also be subject to reality by way of a different and different embodiment
It applies or applies, the various details in this specification can also be based on different viewpoints and application, in the spirit without departing from the disclosure
Lower carry out various modifications or alterations.It should be noted that in the absence of conflict, the feature in following embodiment and embodiment can
To be combined with each other.Based on the embodiment in the disclosure, those of ordinary skill in the art are without creative efforts
Every other embodiment obtained belongs to the range of disclosure protection.
It should be noted that the various aspects of embodiment within the scope of the appended claims are described below.It is aobvious and
Be clear to, aspect described herein can be embodied in extensive diversified forms, and any specific structure described herein and/
Or function is only illustrative.Based on the disclosure, it will be understood by one of ordinary skill in the art that one aspect described herein
It can be independently implemented with any other aspect, and the two or both in these aspects or more can be combined in various ways.It lifts
For example, carrys out facilities and equipments in terms of any number set forth herein can be used and/or practice method.In addition, can be used
Other structures and/or function other than one or more of aspect set forth herein implement this equipment and/or practice
The method.
It should also be noted that, diagram provided in following embodiment only illustrates the basic structure of the disclosure in a schematic way
Think, component count, shape and the size when only display is with component related in the disclosure rather than according to actual implementation in schema are drawn
System, when actual implementation kenel, quantity and the ratio of each component can arbitrarily change for one kind, and its assembly layout kenel can also
It can be increasingly complex.
In addition, in the following description, specific details are provided for a thorough understanding of the examples.However, fields
The skilled person will understand that the aspect can be practiced without these specific details.
In the following description, many specific details are proposed.However, it is understood that in the case where without these specific details,
The embodiment of the present invention still can be implemented.In other cases, well known circuit, structure and technology has not been shown in detail, with not
Cause the understanding in obstruction to description.Those skilled in the art utilize included description will without excessive experiment energy
Enough realize function appropriate.
Citation instruction to " one embodiment ", " embodiment ", " example embodiment " etc., described embodiment can wrap
Special characteristic, structure or feature are included, each embodiment of but not necessarily includes the special characteristic, structure or feature.And
And such phrase not necessarily refers to identical embodiment.Furthermore when describing special characteristic, structure or feature in conjunction with the embodiments, reason
No matter solve to realize that this category feature, structure or feature belong to the knowledge of those skilled in the art in conjunction with other embodiments
Whether clearly it is described.Be described below in claim, may use to term " coupling " and " connection " and
Their derivation.It is construed as these terms and is not construed as synonym for each other." coupling " is used to indicate may object directly with one another
Reason or electrical contact or two or more units that may do not contacted physically or electrically directly each other cooperate or interact with." even
Connect " it is used to indicate the foundation communicated between two or more units coupled to each other.
Herein, initialism UVM indicates generic validation methodology, is one based on SystemVerilog class libraries
The verification platform Development Framework of body, verifying engineer can use the building of its Reusable Module (module) with standardization level knot
The functional verification environment of structure and interface.Initialism AES indicates Advanced Encryption Standard, is a kind of block encryption standard.Initialism
AHB indicates Advanced High-Performance Bus, and AHB is as APB (peripheral bus) and a kind of bus interface.AHB is mainly used for height
Connection between performance module (such as CPU, DMA and DSP), the system on chip bus as SoC.
It should be noted that in the embodiments of the present disclosure, the present invention is described with Advanced High-Performance Bus AHB, but it is of the invention
It is without being limited thereto, but other buses of such as APB etc can be used.
Firstly, it illustrates the AES verifying devices based on UVM verification methodology of the embodiment of the present disclosure to be transported with reference to Fig. 1
Capable verification environment 100.As shown in Figure 1, verification environment 100 includes test case module 101, interface module 102 and test pair
As 103.
For test case module 101 for generating test case, which worked out for validation test object 103
One group of test input, execute condition and expected results, to test whether test object 103 meets particular demands or item
Part.Specifically, test case module 101 is used to generate the excitation of the randomization to test object 103.
In addition, interface module 102 makes 103 communication connection of test case module 101 and test object, to realize the two
Data exchange.
In the embodiments of the present disclosure, verification environment 100 is used for validation test object 103.Specifically, verification environment 100 is right
Test case module 101 carries out example and realizes the verification operation of test object 103.
In the following description, using AES as the example of test object 103 and using ahb bus as interface module 102
Example describe the present invention.It it is understood that test object 103 is not limited to AES, but may include any other system
System or module, for example, the shutdown procedures module of chip system.In addition, interface module 102 is not limited to ahb bus, but can be with
Other buses comprising such as APB etc.
Then, with reference to Fig. 2, using AES as the example of test object 103 and using ahb bus as interface module 102
Example describes the verification environment 200 of the embodiment of the present disclosure.As shown in Fig. 2, verification environment 200 include test case module 201,
Ahb bus interface 202 and AES 203.
In the embodiments of the present disclosure, test case module 201 includes sequence generation module 2011, virtual sequence sending module
2012 and register model 2013, and the excitation for generating the randomization to AES.
Sequence generation module 2011 can generate different sequences, to complete the randomization configuration of test case.Also
It is to say institute, sequence generation module 2011 is by generating list entries of the different sequences as randomization.
Virtual sequence sending module 2012 is connect with sequence generation module 2011, receives what sequence generation module 2011 generated
Sequence simultaneously sends register model 2013 for received sequence.
Register model 2013 maps register (hereinafter referred to as AES internal register) all inside AES, from virtual sequence
Column sending module 2012 receives sequence caused by sequence generation module 2011, and is completed by the received sequence of institute in AES
The operation of portion's register.
In the embodiments of the present disclosure, register model 2013 is generated by writing script, and script can be read in containing register
The Excel table of information generates corresponding system verilog register model 2013 according to the content of Excel table.
It should be noted that in the embodiments of the present disclosure, the table containing register information is not limited to Excel table, but can
To include other tables.
Since the 2013 received sequence of institute of register model may not be able to directly operate AES internal register.Cause
This, in the embodiments of the present disclosure, test case module 201 further includes adapter 2014, AHB System Agent 2015, AES with reference to mould
Block 2016, ahb bus Input Monitor Connector agency 2017, coverage rate collection module 2018, ahb bus output monitor agent 2019 and
Scoring board 2020.
Adapter 2014 is for the affairs conversion between register model 2013 and AHB System Agent 2015, so that posting
Buffer model 2013 can be with 2015 normal communication of AHB System Agent.
AHB System Agent 2015 is packaged with the UVM subenvironment with ahb bus driving, and ahb bus driving can be total to AHB
Line interface 202 is operated, in addition, UVM subenvironment further includes AHB sequence transmitter, AHB sequence transmitter is used for AHB sequence
Column are sent to ahb bus interface 202 via ahb bus driving.
AES the reference module 2016 include AHB configuration information conversion module and aes algorithm model, aes algorithm model include but
It is not limited to verilog, c and MATLAB.
The AHB that ahb bus Input Monitor Connector agency 2017 is packaged with the input information for monitoring ahb bus interface 202 is total
Line Input Monitor Connector device, furthermore ahb bus Input Monitor Connector agency 2017 also sends AES ginseng for the configuration information of ahb bus interface
Examine module 2016.
Coverage rate collection module 2018 is packaged with coverage rate model, and coverage rate model is used to collect the functional coverage of verifying
Rate.
The AHB that ahb bus output monitor agent 2019 is packaged with the output information for detecting ahb bus interface 202 is total
Line output detector, and the output information from ahb bus interface 202 is sent to by ahb bus output monitor agent 2019
Scoring board 2020.
Scoring board 2020 receives the output of output information and aes algorithm model from AES, and believes the output of AES
The output of breath and aes algorithm model is compared.In addition, scoring board 2020 includes that AES model output queue and ahb bus export
Queue, the output information of AES and the output of aes algorithm model are by defeated by income AES model output queue and ahb bus respectively
Dequeue.
Ahb bus interface 202 can be configured by the virtual interface that the interface of system Verilog (SV) is defined,
And it is transferred to AES for that will motivate and the output information of AES is transferred to scoring board 2020.
More than, the AES verifying dress based on UVM verification methodology according to the embodiment of the present disclosure is described by reference to attached drawing
The structure set.Hereinafter, describing the AES verifying dress based on UVM verification methodology of the embodiment of the present disclosure with reference to AES verification process
It sets.
Firstly, calling the class libraries of UVM to write out each mould of verification environment as shown in Figure 2 using system Verilog
Block, and the data communication realized between modules is modeled by transaction-level.
Test case is write, the test vector sequence of randomization is defined, the test vector sequence of the randomization includes key
The encrypted work mode of bit wide, plaintext, encryption or decryption and AES.
After completion test case is write, call test case with runtime verification environment by test platform.
Specifically, after verification environment operation, sequence generation module 2011 is tested according to the Test cases technology write
Sequence vector, test vector sequence generated are called by virtual sequence sending module 2012.
Virtual sequence sending module 2012 transmits received test vector sequence after receiving test vector sequence
To register model 2013, in register model 2013, test vector sequence, which can be converted into adapter 2014, to be known
Other format.
In addition, test vector sequence includes read operation and the write operation to AES internal register, and different operations can adjust
With the different method in 2014 inside of adapter.
Specifically, test vector sequence is converted into the identifiable AHB sequence of AHB System Agent 2015 by adapter 2014,
AHB System Agent 2015 can send AHB sequence transmitter for the AHB sequence received, and AHB sequence transmitter can be by AHB sequence
Column are sent to ahb bus driving, and ahb bus driving can directly control ahb bus 208, to realize AES internal register
Read-write operation.
After completing read-write operation, adapter 2014 can feed back true AES internal register and operate to register model
2013, the information that AES internal register operates is converted into the identifiable format of register model 2013, modifies register model
Value inside 2013, so that true AES internal register value and the value of register model 2013 are consistent.
While AHB System Agent 2015 operates AES internal register, ahb bus Input Monitor Connector agency
2017 real-time reception ahb bus interface operation information, it is total that ahb bus interface operation information via ahb bus 208 is input to AHB
Line Input Monitor Connector device simultaneously sends AES the reference module for ahb bus interface operation information via ahb bus Input Monitor Connector device
2016。
In AES the reference module 2016, ahb bus interface operation information is converted into AES by AHB configuration information conversion module
The identifiable input data of algorithm model, input data are sent in scoring board 2020 by the calculating of aes algorithm model
AES model output queue.
In addition, being packaged with ahb bus output monitor in ahb bus output monitor agent, the operation result of AES can lead to
The output of ahb bus interface 202 is crossed, and the ahb bus that monitor agent 2019 is input to scoring board 2020 is exported by ahb bus
Output queue.
In scoring board 2020, the result of aes algorithm model and true AES are designed to the result of output by comparator
It is compared, prints the information successfully or to fail.
In addition, all input information can be output to coverage rate collection module simultaneously by ahb bus Input Monitor Connector agency 2017
In 2018.Coverage rate collection module 2018 includes that coverage rate collects model, to realize the function of statistical function coverage rate.
That is be only verified and function coverage reach 100% could indicate verifying completion.
In the embodiments of the present disclosure, function coverage is closely coupled with design idea, is described in detail and sets in design specification
It is standby how to run, and corresponding function is then listed in demonstration plan how to be motivated, verify and measure, functional coverage
The purpose of rate verifying is to ensure that the behavior of design in the actual environment is correct.
After the completion of operation, the information of log can in a jumble and data are huge, the key message of script meeting crawl log
And count the various situations occurred in printing verification process.
In the AES verifying device based on UVM verification methodology of the embodiment of the present disclosure, due to having used UVM authentication
The science of law also only needs simply adjustment test case setting that can continue to use, greatly improved and test even if AES function is modified
Demonstrate,prove the reusability of environment.
In addition, the method for the embodiment of the present disclosure uses a large amount of arbitrary excitation, it is randomly provided the register configuration of AES, together
When realize automatic comparison with reference model, and realize the statistics of function coverage, script finally used to extract log
Key message, improve the reliability of functional verification.
Although describing the present invention by reference to exemplary embodiment, it should be appreciated that, the present invention is not limited to disclosed
Exemplary embodiment.Scope of the appended claims should be endowed broadest explanation to cover all such modifications and wait
Same structure and function.
Claims (10)
1. a kind of AES based on UVM verification methodology verifies device, which is characterized in that including sequence generation module, register mould
Type, adapter, AHB System Agent, ahb bus interface, ahb bus Input Monitor Connector agency, ahb bus export monitor agent, AES
The reference module and scoring board, the AES is connect with the ahb bus interface and the AES includes AES internal register,
Wherein
The sequence generation module is configured as generating the test vector sequence of randomization, and the test vector sequence includes pair
The read-write operation of AES internal register；
The register model receives the test vector sequence and maps AES internal register；
The test vector sequence is converted to the identifiable AHB sequence of the AHB System Agent by the adapter；
The AHB System Agent includes that AHB sequence transmitter and ahb bus drive, and the AHB sequence transmitter is by the AHB
Sequence is sent to the ahb bus driving and is written and read with controlling the ahb bus interface to AES internal register；
The ahb bus Input Monitor Connector agency receives ahb bus interface operation information, and the ahb bus interface operation is believed
Breath is sent to the aes algorithm model of the AES the reference module, and the calculated result of the aes algorithm model is sent to the meter
Scoreboard；
The operation result of AES is output to the scoring board by the ahb bus output monitor agent；And
The scoring board is compared to verify the calculated result of the aes algorithm model and the operation result of the AES
State AES.
2. the AES according to claim 1 based on UVM verification methodology verifies device, which is characterized in that described device is also
Include:
Coverage rate collection module, the coverage rate collection module include that coverage rate collects model, and the coverage rate is collected model and used
In statistical function coverage rate.
3. the AES according to claim 1 or 2 based on UVM verification methodology verifies device, which is characterized in that the dress
It sets further include:
Virtual sequence sending module, the test vector sequence that the sequence generation module generates send mould via the virtual sequence
Block is sent to the register model, to operate to AES internal register.
4. the AES according to claim 1 or 2 based on UVM verification methodology verifies device, which is characterized in that described to post
Buffer model is generated by writing script, and the script reads in the table containing AES internal register information, and according to table
Content generates corresponding register model.
5. the AES according to claim 1 or 2 based on UVM verification methodology verifies device, which is characterized in that the AES
The reference module includes AHB configuration information conversion module and aes algorithm model, and the AHB configuration information conversion module is by ahb bus
Interface operation information is converted into the identifiable input data of aes algorithm model, and the input data passes through the meter of aes algorithm model
Calculation is sent to the scoring board.
6. the AES according to claim 1 or 2 based on UVM verification methodology verifies device, which is characterized in that the AHB
The virtual interface that bus interface is defined by the interface of SV configures, and for AHB sequence to be transferred to AES and by AES
Operation result be output to the scoring board.
7. AES according to claim 1 or 2 based on UVM verification methodology verifies device, which is characterized in that it is described with
The test vector sequence of machine includes key bit wide, plaintext, encryption or decryption and the encrypted work mode of AES.
8. the AES according to claim 1 or 2 based on UVM verification methodology verifies device, which is characterized in that the survey
Examination sequence vector includes read operation and the write operation to AES internal register, and passes through the method for calling adapter inner different
Realize different read operation and write operation.
9. the AES according to claim 8 based on UVM verification methodology verifies device, which is characterized in that described in completion
After read operation and write operation, the adapter gives true AES internal register operational feedback to the register model, will
The information of AES internal register operation is converted into the identifiable format of the register model, modifies inside register model
Value, so that true AES internal register value and the value of register model are consistent.
10. the AES according to claim 1 based on UVM verification methodology verifies device, which is characterized in that as the AES
After the completion of the verification process for verifying device, pass through the key message of script crawl log.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111611767A (en) * | 2020-05-21 | 2020-09-01 | 北京百度网讯科技有限公司 | Verification method and device |
| CN112286746A (en) * | 2020-10-31 | 2021-01-29 | 拓维电子科技(上海)有限公司 | Universal verification platform and method for AXI slave device interface |
| CN116611125A (en) * | 2023-07-20 | 2023-08-18 | 中国电子信息产业集团有限公司第六研究所 | High-speed reconfigurable password processing system and method |
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| CN112286746A (en) * | 2020-10-31 | 2021-01-29 | 拓维电子科技(上海)有限公司 | Universal verification platform and method for AXI slave device interface |
| CN112286746B (en) * | 2020-10-31 | 2023-01-24 | 拓维电子科技(上海)有限公司 | Universal verification platform and method for AXI slave device interface |
| CN116611125A (en) * | 2023-07-20 | 2023-08-18 | 中国电子信息产业集团有限公司第六研究所 | High-speed reconfigurable password processing system and method |
| CN116611125B (en) * | 2023-07-20 | 2023-12-05 | 中国电子信息产业集团有限公司第六研究所 | High-speed reconfigurable password processing system and method |
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