CN110521098A - The method and apparatus that dead time tunes in inverter - Google Patents
The method and apparatus that dead time tunes in inverter Download PDFInfo
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- CN110521098A CN110521098A CN201980000221.XA CN201980000221A CN110521098A CN 110521098 A CN110521098 A CN 110521098A CN 201980000221 A CN201980000221 A CN 201980000221A CN 110521098 A CN110521098 A CN 110521098A
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/38—Means for preventing simultaneous conduction of switches
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
- H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
- H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/38—Means for preventing simultaneous conduction of switches
- H02M1/385—Means for preventing simultaneous conduction of switches with means for correcting output voltage deviations introduced by the dead time
Abstract
A method of it prevents input source from overloading in the inverter circuit with Power MOSFET and reduces parasitic inductance.Capacitor sensor senses the temperature of transistor in inverter circuit.Delay generator changes delay time according to from the received temperature of transistor of capacitor sensor.Dead time generates the dead time that unit changes transistor according to the variation of delay time.
Description
Cross reference to related applications
The application is the part continuation application for the U.S. non-provisional application 15/459,003 submitted on March 15th, 2017,
Full content is incorporated herein by reference for all purposes.
Technical field
The present invention relates to prevent breakdown current (shoot-through current) by changing dead time and reduce
The method and apparatus of the body diode turn-on time of power device in inverter circuit.
Background technique
Power inverter is the electronic equipment or circuit that direct current (DC) is changed into exchange (AC).Inverter is in hyundai electronics
It plays an important role, has a wide range of applications in equipment, including uninterruptible power supply, solar energy, induction heating, wireless power pass
Defeated and many other technologies.Unfortunately, some inverters are subjected to the influence of breakdown current, this may cause countless ask
Topic.
It prevents breakdown current and the new method and system for reducing body diode turn-on time in inverter will be helpful to improve
Technical need and solution technical problem.
Summary of the invention
One exemplary embodiment be it is a kind of prevented in the inverter circuit with Power MOSFET input source overload simultaneously
The method for reducing parasitic inductance.This method comprises: sensing high side device in the inverter circuit using the first capacitor sensor
Temperature senses the temperature of downside device in the inverter circuit using the second capacitor sensor, according to electric from first sensing
The temperature that container reception arrives, the first delay generator change the first dead band time interval；According to from second capacitor sensor
The temperature received, the second delay generator change the second dead band time interval；By the way that first capacitor sensor is connected
Between the output and ground of first delay generator, second capacitor sensor is connected to second delay and is occurred
Between the output and ground of device, prevents the input source from overloading and reduce parasitic inductance.First dead band time interval corresponds to
Dead time before the connection of high side device.When second dead band time interval corresponds to the dead zone before downside device is connected
Between.The Power MOSFET includes generating dead zone based on first dead band time interval and second dead band time interval
Time.
Another exemplary embodiment is a kind of inverter circuit, prevents input source from overloading in inverter circuit and reduces parasitism
Inductance.The inverter circuit includes: the first capacitor sensor, the high side device being thermally connected in the inverter circuit；Second
Capacitor sensor, the downside device being thermally connected in the inverter circuit；Dead time generates unit, by being respectively
It states high side device and the downside device and generates dead time to prevent breakdown current and reduce body diode turn-on time, it is described
Dead time includes the first dead band time interval and the second dead band time interval.It includes changing institute that the dead time, which generates unit,
State the first delay generator and the second delay generator of the first dead band time interval.First capacitor sensor is connected to institute
It states between the output and ground of the first delay generator.Second capacitor sensor is connected to the defeated of second delay generator
Out between ground.First dead band time interval correspond to the high side device connect before dead time, described second
Dead band time interval corresponds to the dead time before the downside device is connected.
Another exemplary embodiment be it is a kind of prevented in the inverter circuit with Power MOSFET input source overload simultaneously
The method for reducing parasitic inductance.This method comprises: sensing in the inverter circuit temperature of at least one high side device and described
The temperature of at least one downside device in inverter circuit；Unit is generated using at least one dead time, and according to receiving
The temperature of the temperature of at least one high side device and at least one downside device, change the first dead band time interval and
Second dead band time interval；There is the inverter circuit of dead time by operation to prevent breakdown current and reduce body diode
Turn-on time, the dead time is in maximum dead time and minimum dead time.First dead band time interval is corresponding
Dead time before the connection of at least one high side device, second dead band time interval correspond at least one downside device
Dead time before part connection.The maximum dead time depends on the electricity of at least one capacitor sensor under rated temperature
Hold, the minimum dead time depends on the capacitor of at least one capacitor sensor under Curie temperature.
Other exemplary embodiments are also discussed herein.
Detailed description of the invention
What Fig. 1 showed an exemplary embodiment prevents input source from overloading in the inverter circuit with Power MOSFET
And the method for reducing parasitic inductance.
Fig. 2 shows the block diagram of D class inverter circuit in the half-bridge configuration of an exemplary embodiment.
Fig. 3 shows the block diagram of the delay generator of an exemplary embodiment.
Fig. 4 shows the block diagram of the delay generator of an exemplary embodiment.
Fig. 5 shows the percentage of some certain dielectric materials for capacitor sensor an of exemplary embodiment to temperature
The curve graph of the rate of change of capacitance of degree.
Fig. 6 shows song of the signal voltage to the time of the inverter of existing inverter and an illustrative embodiment of the invention
Line chart.
Specific embodiment
As it is used herein, " body diode turn-on time " refers to when the high side and downside device in power inverter
When channel all closes (such as dead zone interval), electric current via the high resistance parasitic body diode path in parallel with device channel when
Section.
As used herein and in the claims, " comprising ", which means, to be included following element but is not excluded for other element.
As it is used herein, " Curie temperature " refers to that PTC material changes its characteristic (for example, capacitor sharply increases
Add) a threshold temperature.The characteristic of Curie temperature is used to limit the maximum current of power device, to prevent breakdown current.
As it is used herein, " only " being referred between capacitor sensor and delay generator by a conducting wire or strip conductor connection
Be directly connected to.
As it is used herein, " dead time generation unit " refers to dead time insertion pulse width modulator (PWM) letter
A circuit in number, for example, conducted signal will not be overlapped in two or more power transistors in half-bridge or full-bridge.
As it is used herein, " device ", " high side device ", " downside device " refer to the power crystal in inverter circuit
Pipe.
As it is used herein, " inverter circuit " refers to the electronic circuit that direct current (DC) is changed into exchange (AC).
As it is used herein, " printed circuit board (PCB) cabling ", which refers to, enables current to flow in and out integrated electricity
The strip conductor on road.PCB is made of the IC network that PCB trace interconnects.
As it is used herein, " breakdown current " refers to the electric current punching occurred when two devices are all connected in inverter circuit
It hits, " breakdown " refers to the electric current by two devices in inverter circuit from Vamp to ground.
As it is used herein, " overshoot " (overshoot) means that instantaneous value is more than ideal value, " undershoot "
(undershoot) mean instantaneous value lower than ideal value.Ideal value is the load voltage of exact matching condition." overshoot " and " under
Both punchings " occur during transient state, this is the short duration of signal ring or oscillation under unmatched load.
Example embodiment is related to preventing input source from overloading in the inverter circuit with Power MOSFET and reducing parasitism
The device and method of inductance.
Power inverter (or inverter) is the electronic equipment or circuit that direct current (DC) is converted to exchange (AC).Inverter
It is widely used in different applications, such as induction heating, power amplifier, uninterruptible power supply and many other applications.There is a type
The inverter of type, referred to as D class inverter are used for wireless power transmission system, because this inverter efficiency with higher, right
Load variation is more steady, and provides higher output power.
For D class inverter and other inverters, it is instead important to avoid that when the high side device and downside device in inverter circuit
The case where part is also turned on.Such case can generate low impedance path and generate big breakdown current.For example, when two function
When rate device is completely or partially connected, this is provided from VINTo the path of the high current surge of ground GND, breakdown current occurs.Knot
Fruit, the device in inverter circuit heat up and waste electric power and even damage.
A kind of method that breakdown current is mitigated or eliminated is to generate unit using dead time generator or dead time.It should
Generator generation time delay between device input, to avoid breakdown current.The time interval that two devices are all closed is known as
Dead time.
When inverter is in desired operation, the input of device should not be simultaneously height.For example, when being used to drive high side device
When the input A of part (such as transistor 1) is connected, for driving the input B of downside device (such as transistor 2) to close, vice versa.
But when inputting A and input B is in switch step, device can be potentially encountered undesirable operation.It is short accordingly, there exist one
Period, two of them device is all in the " on " stage and short circuit occurs.In dead time, inputs A and input B locates
In " closing " stage.
As dead time TDEqual to one predetermined critical time TcritWhen, there is no power loss in circuit.Work as TDLess than zero
When, it may occur that breakdown current.Work as TDMore than or equal to zero and it is less than TcritWhen, there are some switching losses in circuit.Work as TDIt is greater than
TcritWhen, negative current will lead to body diode conducting.
Example embodiment provides the technical solution that dead time generates using new method and device to solve above-mentioned ask
Topic, prevents breakdown current and reduces body diode turn-on time in inverter circuit.Particularly, when dead zone in exemplary embodiment
Between generation be not limited to generate the fixation dead time for being appropriate only for a loading condition.
Exemplary embodiment includes changing the method and apparatus of the length of dead time, avoids device fault, power conversion
Low efficiency, device overheat, system operating temperatures increase and the driver malfunction as caused by serious undershoot voltage.Exemplary embodiment
The breakdown current occurred in inverter circuit, including D class inverter circuit is also mitigated or eliminated.
Exemplary embodiment is beneficial to the operation of inverter circuit and improves the transfer efficiency of DC to AC, this is in a variety of differences
Electronic device and application in be useful.
For example, the effect of the power device (such as enhancement mode GaN HEMT) with high body diode forward bias
Rate will receive seriously affecting for dead time length.Device temperature is proportional to the power loss of these power devices.According to inspection
The minimum device temperature measured, the optimum dead time value of inverter reach minimum power loss.Exemplary embodiment provides
Adjust automatically dead time and the method and apparatus that inverter circuit is maintained into optimum dead time value.
Exemplary embodiment of the present prevents input source from overloading, so that the present invention is suitable for simplifying the low-voltage of circuit design
With high driving current application.
In electrical network, parasitic antenna be in circuit it is not expected that have its expected purpose, be treated as electronic device
Circuit part.Conducting wire has parasitic inductance, because any conducting wire for having electric current to flow through can all generate magnetic field around it.Parasitic electricity
Sense is determined by track lengths and working frequency.Track lengths are longer, and parasitic inductance is higher.For with the inverse of Power MOSFET
Power transformation road, parasitic inductance can generate significant impact to the validity of control.If this circuit undergoes high parasitic inductance, believing
In the case where number mistake, voltage is allowed to overshoot significantly, not protection component.Exemplary embodiment reduces wiring
Parasitic inductance.
Different loads need to control different dead times, to realize optimum efficiency in inverter circuit.It is exemplary
Embodiment, which can be realized to control from the optimum dead zone time according to device temperature, to be arranged.
As further benefit, exemplary embodiment reduces the material cost and big heat dissipation of purchase higher level component
The operating cost of device and space.For example, exemplary embodiment reduces the importance for implementing radiator in inverter circuit and disappears
In addition to the demand of cooling-part expensive in inverter circuit.
With reference to Fig. 1, exemplary embodiment includes a kind of method, and this method is in the inverter circuit with Power MOSFET
It prevents input source from overloading and reduces parasitic inductance.
As an example, Power MOSFET includes being generated extremely based on the first dead band time interval and the second dead band time interval
Area's time.For example, the first dead band time interval corresponds to the dead time before high side device is connected, the second dead band time interval
Dead time before being connected corresponding to downside device.
Box 110 is shown: using the temperature of high side device in the first capacitor sensor sensing inverter circuit.
As an example, the first capacitor sensor is thermally connected to high side device by metal wire or any Heat Conduction Material.
As an example, high side device surrounds or be thermally connected to radiator by radiator, the first capacitor sensor is also radiated
Device surrounds or is thermally connected to radiator.
Box 120 is shown: using the temperature of downside device in the second capacitor sensor sensing inverter circuit.
As an example, the second capacitor sensor is thermally connected to downside device by metal wire or Heat Conduction Material.
As an example, downside device surrounds or be thermally connected to radiator by radiator, the second capacitor sensor is also dissipated
Hot device surrounds or is thermally connected to radiator.
As an example, high side device and downside device can be selected from the transistor of one or more types, including but unlimited
In enhanced GaN, GaN power transistor and MOSFET.The device of high power density will lead to apparent temperature change.
As an example, source voltage is connected to the drain electrode of high side device.The source electrode of high side device is connected to the leakage of downside device
Pole.The source electrode of downside device is grounded.
Box 130 is shown: by the first delay generator and according to the temperature received from the first capacitor sensor, being changed
Become the first dead band time interval.
For example, changing the capacitor of the first capacitor sensor according to the temperature for the high side device for detecting or sensing.According to
The capacitance variations of first capacitor sensor, automatic the first delay time for changing the first delay generator and generating.With high side device
The variation of the sensing temperature of part, these changes continuously or real-time continuously occur.First dead band time interval is according to RC retardation ratio
Generate the first delay time change and change.R is the resistance for the first fixed resistor that dead time generates in unit,
It includes the first delay generator and the second delay generator that middle dead time, which generates unit,.C is the capacitor of the first capacitor sensor.
Box 140 is shown: by the second delay generator and according to the temperature received from the second capacitor sensor, being changed
Become the second dead band time interval.
For example, changing the capacitor of the second capacitor sensor according to the temperature for the downside device for detecting or sensing.According to
The variation of the capacitor of second capacitor sensor, automatic the second delay time for changing the second delay generator and generating.With downside
The variation of the sensing temperature of device, these change continuous or occur continuously in real time.Second dead band time interval is according to R'C'
Postpone the change of the second delay time generated and changes.R' is the electricity for the second fixed resistor that dead time generates in unit
Resistance.C' is the capacitor of the second capacitor sensor.
Box 150 is shown: it is exported between ground by the way that the first capacitor sensor is connected to the first delay generator, and
Second capacitor sensor is connected between the output of the second delay generator and ground, prevent input source from overloading and reduces parasitic electricity
Sense.
As an example, the first fixed resistor is connected between the outputting and inputting of the first delay generator.
As an example, the second fixed resistor is connected between the outputting and inputting of the second delay generator.
It is connect as an example, the first delay generator only passes through a conducting wire or strip conductor with the first capacitor sensor.
It is connect as an example, the second delay generator only passes through a conducting wire or strip conductor with the second capacitor sensor.
As an example, the first capacitor sensor includes the first negative temperature coefficient capacitor being connected in series and the first positive temperature
Coefficient capacitor, the second sense resistor include the second negative temperature coefficient capacitor being connected in series and the second positive temperature coefficient electricity
Container.
As an example, the first negative temperature coefficient capacitor has dielectric constantFirst positive temperature coefficient
Capacitor has dielectric constantWherein T is the temperature of high side device, TCIt is Curie temperature, α1It is constant value,
A, B and C is Steinhart-Hart coefficient, ε0It is permittivity of vacuum.
As an example, the second negative temperature coefficient capacitor has dielectric constantSecond positive temperature coefficient
Capacitor has dielectric constantWherein T is the temperature of downside device, TCIt is Curie temperature, α1It is constant value,
A, B and C is Steinhart-Hart coefficient, ε0It is permittivity of vacuum.
Fig. 2 shows the block diagram of the D class inverter circuit in the half-bridge configuration of an exemplary embodiment.The common skill in this field
Art personnel will be understood that exemplary embodiment is also applied for the configuration of other inverters, such as full bridge configuration.
Circuit 200 includes pulse width modulator (PWM) input node 201, dead time generation unit (DT Gen.) 206, drives
Dynamic device 202, high side device 203 and downside device 204, the first capacitor sensor 210 and the second capacitor sensor 220.When dead zone
Between generate unit 206 input be connected to PWM input node 201.Dead time generates the first output HI and second of unit 206
Output L1 is connected respectively to high side device 203 and downside device 204 by driver 202.First output of the enhancing of driver 202 HI
With the second output L1.For example, high side device 203 and downside device 204 are N-channel transistors.Therefore, dead time generates
First output HI of unit 206 is connected to the grid of high side device 203 via driver 202, and dead time generates unit 206
Second output LI is connected to the grid of downside device 204 via driver 202.Source voltage (VAMP) is connected to high side device 203
Drain electrode, the source electrode of high side device is connected to the drain electrode of downside device 204.The source electrode of downside device 204 is grounded.High side device
Node between the drain electrode of 203 source electrode and downside device 204 is connected to filter network 205 and any impedance load
Such as resistor, capacitor, inductor (Zload),.
As an example, high side device 203 is surrounded by radiator or covering 208, downside device 204 is by radiator or covering
Object 209 surrounds.First capacitor sensor 210 is embedded in radiator or covering 208, and is thermally connected to high side device 203, with
Sense the temperature of high side device 203.Second capacitor sensor 220 is embedded in radiator or covering 209, and is thermally connected to low
Side device 204, to sense the temperature of downside device 204.Dead time generates unit 206 and is only electrically connected to by a strip conductor
First capacitor sensor 210, dead time generate unit 206 and are also only electrically connected the second capacitor sensor by a strip conductor
220。
As an example, the first capacitor sensor 210 includes the first negative temperature coefficient (NTC) capacitor being connected in series and the
One positive temperature coefficient (PTC) capacitor.Second capacitor sensor 220 includes the second negative temperature coefficient (NTC) electricity being connected in series
Container and the second positive temperature coefficient (PTC) capacitor.Dead time generates unit 206 according to from 210 He of the first capacitor sensor
The temperature that second capacitor sensor 220 receives changes dead time, and dead time includes the first dead zone of high side device 203
Second dead band time interval of time interval and downside device 204.First dead band time interval is connected corresponding to high side device 203
Dead time before, the second dead band time interval correspond to the dead time before downside device 204 is connected.
As an example, the dielectric constant of capacitor is respectively as follows:
Wherein, A, B and C are Steinhart-Hart (S-H) coefficients, and T is the temperature of capacitor sensor, TCIt is sense capacitance
The Curie temperature of device, α1It is steady state value.
Fig. 3 shows the block diagram of the delay generator 300 of an exemplary embodiment.Sensing including two types capacitor
Capacitor 310 is connected between the output and ground of delay generator 300.Since transducing signal return path can be directly connected to
Ground, this mode greatly reduce the parasitic inductance of circuit lead, and prevent gate voltage overshoot and undershoot.Capacitor is selected from negative
Temperature coefficient (NTC) capacitor and positive temperature coefficient (PTC) capacitor.For example, at least one NTC capacitor and at least one
A PTC capacitor is connected in series.Fixed resistor 303 is connected between the outputting and inputting of delay generator 300, to generate one
A RC retardation ratio circuit.For example, since resistor 302 limits the output voltage of load, it can choose fixed value resistance
Device 302 is with low resistance, such as 1 to 5 ohm.Capacitor sensor 310 is located at the outside of delay generator 300, with inversion
The transistor of circuit is thermally connected, to sense their temperature.PTC capacitor execute overheating protection, it is this overheat be by breakdown or
Caused by serious switching loss.And NTC capacitor is used to finely tune the delay time generated from delay generator 300.
Fig. 4 shows the block diagram of the delay generator 400 an of exemplary embodiment to provide the circuit design of flexibility.Packet
The capacitor sensor 410 for including two types capacitor is connected between the output and ground of delay generator 400.Capacitor is selected from
NTC capacitor and PTC capacitor.For example, at least one NTC capacitor and at least one PTC capacitor are connected in series.Packet
The sense resistor 403 for including two types resistor is connected between the outputting and inputting of delay generator 400, and is prolonged with generating RC
Slow circuit.Resistor is selected from NTC sensor and PTC sensor.Capacitor sensor 410 and sense resistor 403 are located at delay hair
The outside of raw device 400 is used for sensing temperature to be thermally connected with transistor.For example, at least one NTC sensor and at least
One PTC sensor series connection.PTC capacitor and/or PTC sensor execute overheating protection, this overheat be by breakdown or
Caused by serious switching loss.NTC capacitor and/or NTC sensor are used to finely tune the delay generated from delay generator 400
Time.
Fig. 5 shows the capacitance variations of some particular dielectric materials for capacitor sensor an of exemplary embodiment
The curve graph 500 of rate (percentage (%) is to temperature (DEG C)).These materials have specific temperature characterisitic, based on alone or in combination
The requirement of dead time select, used with constructing based on a predetermined temperature coefficient curve positive or negative temperature coefficient capacitor
In capacitor sensor.
Fig. 6 shows the signal voltage (V) of the inverter of existing inverter and exemplary embodiment of the present to time (μ s)
Curve graph 600.Printed circuit board (PCB) track lengths of existing inverter are twice of inverter track lengths of the present invention.
As shown in fig. 6, the present invention substantially eliminates the ring of voltage signal.For example, the present invention eliminates negative overshoot and undershoot electricity
It presses 2V and eliminates positive overshoot and undershoot voltage 0.5V.
Therefore, exemplary embodiment of the present invention is fully described.Although the description is related to specific embodiment, this
Field technical staff can understand, can practice the present invention by changing these details.Therefore, the present invention should not be construed
To be limited to embodiments set forth here.
Claims (20)
1. a kind of method for preventing input source from overloading in the inverter circuit with Power MOSFET and to reduce parasitic inductance, should
Method includes:
The temperature of high side device in the inverter circuit is sensed using the first capacitor sensor；
The temperature of downside device in the inverter circuit is sensed using the second capacitor sensor；
By the first delay generator and according to the temperature received from first capacitor sensor, change the first dead time
Interval, first dead band time interval correspond to the dead time before the high side device is connected；
By the second delay generator and according to the temperature received from second capacitor sensor, change the second dead time
Interval, second dead band time interval correspond to the dead time before the downside device is connected；With
By the way that first capacitor sensor is connected between the output and ground of first delay generator, and by described
Two capacitor sensors are connected between the output and ground of second delay generator, are prevented the input source from overloading and reducing and are posted
Raw inductance；
Wherein, the Power MOSFET includes being produced based on first dead band time interval and second dead band time interval
Raw dead time.
2. according to the method described in claim 1, further include:
According to the temperature of the high side device sensed, change the capacitor of first capacitor sensor；
According to the temperature of the downside device sensed, change the capacitor of second sense resistor.
3. according to the method described in claim 1, further include:
According to the capacitance variations of first capacitor sensor, when changing the first delay generated from first delay generator
Between；With
According to the capacitance variations of second capacitor sensor, when changing the second delay generated from second delay generator
Between.
4. according to the method described in claim 1, wherein the first fixed resistor is connected to the defeated of first delay generator
Between entering and exporting, the second fixed resistor is connected between the outputting and inputting of second delay generator.
5. according to the method described in claim 1, wherein first capacitor sensor includes the first negative temperature being connected in series
Coefficient capacitor and the first positive temperature coefficient capacitor, second sense resistor include the second negative temperature system being connected in series
Number capacitor and the second positive temperature coefficient capacitor.
6. according to the method described in claim 5, wherein the first negative temperature coefficient capacitor has dielectric constantThe first positive temperature coefficient capacitor has dielectric constantWherein T is institute
State the temperature of high side device, TCIt is Curie temperature, α1It is constant value, A, B and C are Steinhart-Hart coefficient, ε0It is that vacuum is situated between
Electric constant.
7. according to the method described in claim 1, further include: only pass through a strip conductor for first delay generator and institute
The connection of the first capacitor sensor is stated, only passes through a strip conductor for second delay generator and second capacitor sensor
Connection.
8. a kind of inverter circuit prevents input source from overloading and reduces parasitic inductance in inverter circuit, comprising:
First capacitor sensor, the high side device being thermally connected in the inverter circuit；
Second capacitor sensor, the downside device being thermally connected in the inverter circuit；
Dead time generates unit, is prevented by being respectively the high side device and downside device generation dead time
Breakdown current simultaneously reduces body diode turn-on time, wherein the dead time includes the first dead band time interval and the second dead zone
Time interval, the dead time generate unit and include:
First delay generator changes first dead band time interval, wherein first capacitor sensor is connected to institute
It states between the output and ground of the first delay generator；
Second delay generator changes second dead band time interval, wherein second capacitor sensor is connected to institute
It states between the output and ground of the second delay generator；
Wherein, first dead band time interval corresponds to the dead time before the high side device is connected, and described second is dead
Area's time interval corresponds to the dead time before the downside device is connected.
9. inverter circuit according to claim 8, wherein the first fixed resistor is connected to first delay generator
Output and input between；Second fixed resistor is connected between the outputting and inputting of second delay generator.
10. inverter circuit according to claim 8 is electrically connected wherein first delay generator only passes through a strip conductor
It is connected to first capacitor sensor, second delay generator only passes through a strip conductor and is electrically connected to second sensing
Capacitor.
11. inverter circuit according to claim 8, wherein first capacitor sensor include be connected in series it is first negative
Temperature coefficient capacitor and the first positive temperature coefficient capacitor, second sense resistor include the second subzero temperature being connected in series
Spend coefficient capacitor and the second positive temperature coefficient capacitor.
12. inverter circuit according to claim 11, wherein the second negative temperature coefficient capacitor has dielectric constantThe second positive temperature coefficient capacitor has dielectric constantWherein T is institute
State the temperature of the second capacitor sensor, TCIt is Curie temperature, α1It is constant value, A, B and C are Steinhart-Hart coefficient, ε0It is
Permittivity of vacuum.
13. inverter circuit according to claim 8, wherein the inverter circuit is D class half-bridge circuit.
14. inverter circuit according to claim 8, wherein the inverter circuit is D class full-bridge circuit.
15. inverter circuit according to claim 8, wherein the high side device and the downside device are selected from: enhanced
GaN, GaN power transistor and silicon MOSFET.
16. a kind of method for preventing input source from overloading in the inverter circuit with Power MOSFET and to reduce parasitic inductance,
This method comprises:
Sense in the inverter circuit at least one downside device in the temperature of at least one high side device and the inverter circuit
Temperature；
Using at least one dead time generate unit and the temperature of at least one high side device according to receiving and
The temperature of at least one downside device changes the first dead band time interval and the second dead band time interval, and described first is dead
Area's time interval corresponds to the dead time before at least one described high side device is connected, second dead band time interval pair
Dead time before the connection of at least one downside device described in Ying Yu；
By operation have the inverter circuit of dead time prevent breakdown current and reduce body diode turn-on time, it is described
Dead time in maximum dead time and minimum dead time, wherein the maximum dead time depend on rated temperature down toward
The capacitor of a few capacitor sensor, the minimum dead time depend at least one described capacitor sensor under Curie temperature
Capacitor.
17. according to the method for claim 16, further includes:
The temperature of at least one high side device according to sensing changes the capacitor of first capacitor sensor；
The temperature of at least one downside device according to sensing changes the capacitor of second capacitor sensor；
According to the capacitance variations of first capacitor sensor, the first delay generator generated for the first delay time；
According to the capacitance variations of second capacitor sensor, the second delay generator generated for the second delay time；
Wherein first capacitor sensor is connected between the output and ground of first delay generator；Second sensing
Capacitor is connected between the output and ground of second delay generator.
18. according to the method for claim 17, further includes:
First fixed resistor is connected between the outputting and inputting of first delay generator, by the second fixed resistor
It is connected between the outputting and inputting of second delay generator.
19. according to the method for claim 16, wherein at least one described capacitor sensor includes the subzero temperature being connected in series
Coefficient capacitor and positive temperature coefficient capacitor are spent, wherein the negative temperature coefficient sensor is with dielectric constantCapacitor, the positive temperature coefficient sensor is with dielectric constantElectricity
Container, wherein T is the temperature of at least one sense resistor, TCIt is Curie temperature, α1It is constant value, A, B and C are
Steinhart-Hart coefficient, ε0It is permittivity of vacuum.
20. according to the method for claim 16, further includes:
At least one described dead time generation unit is only passed through into a strip conductor and is connected at least one described sense capacitance
Device.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US16/254,633 | 2019-01-23 | ||
| US16/254,633 US10468974B2 (en) | 2017-03-15 | 2019-01-23 | Method and apparatus of dead time tuning in an inverter |
| PCT/CN2019/073887 WO2020151020A1 (en) | 2019-01-23 | 2019-01-30 | Method and apparatus of dead time tuning in an inverter |
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| CN110521098B CN110521098B (en) | 2021-01-08 |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020001342A1 (en) * | 2000-05-25 | 2002-01-03 | Marco Berkhout | Carrousel handshake |
| CN102315770A (en) * | 2010-07-01 | 2012-01-11 | 佳能株式会社 | DC/DC transducer and electronic installation |
| CN105229907A (en) * | 2013-05-14 | 2016-01-06 | 罗伯特·博世有限公司 | The control appliance of half-bridge |
| CN107005152A (en) * | 2017-03-15 | 2017-08-01 | 香港应用科技研究院有限公司 | Method and apparatus for tuning dead time in inverter |
| CN107888056A (en) * | 2013-07-10 | 2018-04-06 | 株式会社电装 | Drive dynamic control device |
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2019
- 2019-01-30 CN CN201980000221.XA patent/CN110521098B/en active Active
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020001342A1 (en) * | 2000-05-25 | 2002-01-03 | Marco Berkhout | Carrousel handshake |
| CN102315770A (en) * | 2010-07-01 | 2012-01-11 | 佳能株式会社 | DC/DC transducer and electronic installation |
| CN105229907A (en) * | 2013-05-14 | 2016-01-06 | 罗伯特·博世有限公司 | The control appliance of half-bridge |
| CN107888056A (en) * | 2013-07-10 | 2018-04-06 | 株式会社电装 | Drive dynamic control device |
| CN107005152A (en) * | 2017-03-15 | 2017-08-01 | 香港应用科技研究院有限公司 | Method and apparatus for tuning dead time in inverter |
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