CN110521098B - Method and apparatus for dead time tuning in an inverter - Google Patents

Method and apparatus for dead time tuning in an inverter Download PDF

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CN110521098B
CN110521098B CN201980000221.XA CN201980000221A CN110521098B CN 110521098 B CN110521098 B CN 110521098B CN 201980000221 A CN201980000221 A CN 201980000221A CN 110521098 B CN110521098 B CN 110521098B
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dead time
capacitor
side device
sensing capacitor
delay generator
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CN110521098A (en
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李恒生
刘燕
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Hong Kong Applied Science and Technology Research Institute ASTRI
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Hong Kong Applied Science and Technology Research Institute ASTRI
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/32—Means for protecting converters other than automatic disconnection
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/38—Means for preventing simultaneous conduction of switches
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
    • H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
    • H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/38—Means for preventing simultaneous conduction of switches
    • H02M1/385—Means for preventing simultaneous conduction of switches with means for correcting output voltage deviations introduced by the dead time

Abstract

A method for preventing an input source from being overloaded and reducing parasitic inductance in an inverter circuit having dead time control. The sensing capacitor senses the temperature of a transistor in the inverter circuit. The delay generator varies the delay time according to the transistor temperature received from the sensing capacitor. The dead time generation unit changes the dead time of the transistor according to the variation of the delay time.

Description

Method and apparatus for dead time tuning in an inverter
Cross Reference to Related Applications
This application is a continuation-in-part application of U.S. non-provisional application 15/459,003 filed on 3, 15, 2017, the entire contents of which are incorporated herein by reference for all purposes.
Technical Field
The present invention relates to a method and apparatus for preventing a shoot-through current and reducing a body diode conduction time of a power device in an inverter circuit by varying a dead time.
Background
A power inverter is an electronic device or circuit that converts Direct Current (DC) to Alternating Current (AC). Inverters play an important role in modern electronic devices, having a wide range of applications including uninterruptible power supplies, solar power, induction heating, wireless power transfer and many other technologies. Unfortunately, some inverters are often subject to breakdown currents, which can lead to countless problems.
A new method and system for preventing shoot-through currents and reducing body diode conduction times in inverters would help to increase the technical demands and solve the technical problems.
Disclosure of Invention
An exemplary embodiment is a method of preventing an input source from being overloaded and reducing parasitic inductance in an inverter circuit having dead time control. The method comprises the following steps: sensing a temperature of a high-side device in the inverter circuit using a first sensing capacitor, sensing a temperature of a low-side device in the inverter circuit using a second sensing capacitor, and varying a first dead time interval by a first delay generator according to the temperature received from the first sensing capacitor; a second delay generator varying a second dead time interval as a function of the temperature received from the second sensing capacitor; by connecting the first sensing capacitor between the output of the first delay generator and ground and the second sensing capacitor between the output of the second delay generator and ground, the input source is prevented from being overloaded and parasitic inductance is reduced. The first dead time interval corresponds to a dead time before the high-side device is turned on. The second dead time interval corresponds to a dead time before the low side device turns on. The dead-time control includes generating dead-time based on the first dead-time interval and the second dead-time interval.
Another exemplary embodiment is an inverter circuit that prevents an input source from being overloaded and reduces parasitic inductance in the inverter circuit. The inverter circuit includes: a first sensing capacitor thermally connected to a high-side device in the inverter circuit; a second sensing capacitor thermally connected to a low-side device in the inverter circuit; a dead time generation unit that prevents a breakdown current and reduces a body diode conduction time by generating dead times for the high-side device and the low-side device, respectively, the dead times including a first dead time interval and a second dead time interval. The dead time generation unit includes a first delay generator that changes the first dead time interval and a second delay generator that changes the second dead time interval. The first sensing capacitor is connected between the output of the first delay generator and ground. The second sensing capacitor is connected between the output of the second delay generator and ground. The first dead time interval corresponds to a dead time before the high-side device is turned on, and the second dead time interval corresponds to a dead time before the low-side device is turned on.
Another exemplary embodiment is a method of preventing an input source from being overloaded and reducing parasitic inductance in an inverter circuit having dead time control. The method comprises the following steps: sensing a temperature of at least one high-side device in the inverter circuit and a temperature of at least one low-side device in the inverter circuit; changing, using at least one dead time generating unit, a first dead time interval and a second dead time interval in dependence on the received temperature of the at least one high side device and the temperature of the at least one low side device; preventing a breakdown current and reducing a body diode conduction time by operating the inverter circuit with a dead time within a maximum dead time and a minimum dead time. The first dead time interval corresponds to a dead time before the at least one high-side device is turned on, and the second dead time interval corresponds to a dead time before the at least one low-side device is turned on. The maximum dead time depends on the capacitance of the at least one sensing capacitor at the nominal temperature and the minimum dead time depends on the capacitance of the at least one sensing capacitor at the curie temperature.
Other exemplary embodiments are also discussed herein.
Drawings
Fig. 1 illustrates a method of preventing an input source from being overloaded and reducing parasitic inductance in an inverter circuit having dead time control according to an exemplary embodiment.
Fig. 2 shows a block diagram of a class D inverter circuit in a half-bridge configuration of an exemplary embodiment.
Fig. 3 shows a block diagram of a delay generator of an exemplary embodiment.
Fig. 4 shows a block diagram of a delay generator of an exemplary embodiment.
FIG. 5 shows a graph of percentage versus rate of change in capacitance with temperature for some particular dielectric materials of the sensing capacitor of an example embodiment.
Fig. 6 shows a graph of signal voltage versus time for a prior art inverter and an inverter in accordance with an exemplary embodiment of the present invention.
Detailed Description
As used herein, "body diode on-time" refers to the period of time when the channels of both the high-side and low-side devices in the power inverter are off (e.g., dead space), current flows through the high-resistance parasitic body diode path in parallel with the device channels.
As used herein and in the claims, "comprising" means including the following elements but not excluding others.
As used herein, "curie temperature" refers to a threshold temperature at which a positive temperature coefficient material changes its properties (e.g., a sharp increase in capacitance). The characteristic of the curie temperature is used to limit the maximum current of the power device, thereby preventing a breakdown current.
As used herein, connected by a wire or strip conductor "only" refers to a direct connection between the sensing capacitor and the delay generator.
As used herein, "dead time generation unit" refers to a circuit that inserts dead time into a Pulse Width Modulator (PWM) signal, e.g., the conduction signals do not overlap in two or more power transistors in a half-bridge or a full-bridge.
As used herein, "device," "high-side device," "low-side device" refers to a power transistor in an inverter circuit.
As used herein, "inverter circuit" refers to an electronic circuit that converts Direct Current (DC) to Alternating Current (AC).
As used herein, "Printed Circuit Board (PCB) trace" refers to a strip conductor that enables current to flow into and out of an integrated circuit. The PCB is made up of a network of integrated circuits interconnected by PCB traces.
As used herein, "breakdown current" refers to the current surge that occurs when both devices in the inverter circuit are turned on, and "breakdown" refers to the current through both devices in the inverter circuit from Vamp to ground.
As used herein, "overshoot" (overshoot) means that the instantaneous value exceeds the ideal value, and "undershoot" (undershoot) means that the instantaneous value is below the ideal value. The ideal value is a load voltage that exactly matches the conditions. Both "overshoot" and "undershoot" occur during transients, which is the short duration of ringing or oscillation of a signal under an unmatched load.
Example embodiments relate to an apparatus and method for preventing an input source from being overloaded and reducing parasitic inductance in an inverter circuit having dead time control.
A power inverter (or inverter) is an electronic device or circuit that converts Direct Current (DC) to Alternating Current (AC). Inverters are widely used in different applications such as induction heating, power amplifiers, uninterruptible power supplies and many other applications. One type of inverter, referred to as a class D inverter, is used in wireless power transfer systems because such inverters have higher efficiency, are more robust to load variations, and provide higher output power.
For class D inverters and other inverters, it is important to avoid the situation that occurs when the high-side device and the low-side device in the inverter circuit are turned on at the same time. This condition creates a low impedance path and produces a large breakdown current. This provides for example a slave V when both power devices are fully or partially onINA breakdown current occurs in the path of a large current surge to ground GND. As a result, the devices in the inverter circuit heat up and waste power or even damage.
One way to mitigate or eliminate the breakdown current is to use a dead-time generator or a dead-time generating unit. The generator generates a time delay between device inputs to avoid breakdown currents. The time interval during which both devices are off is called the dead time.
When the inverter is in desired operation, the input of the device should not be high at the same time. For example, when input a for driving a high side device (e.g., transistor 1) is on, input B for driving a low side device (e.g., transistor 2) is off, and vice versa. However, when input a and input B are in the switching phase, the device may experience undesirable operation. Thus, there is a short period of time in which both devices are in the "on" phase and a short circuit occurs. During the dead time, both input A and input B are in the "off" phase.
When dead time TDEqual to a predetermined critical time TcritThere is no power loss in the circuit. When T isDBelow zero, a breakdown current occurs. When T isDGreater than or equal to zero and less than TcritThere are some switching losses in the circuit. When T isDGreater than TcritThe negative current will cause the body diode to conduct.
Example embodiments solve the above problems with new methods and apparatus providing a technical solution to dead time generation, preventing shoot through currents and reducing body diode conduction times in inverter circuits. In particular, the generation of dead time in the exemplary embodiment is not limited to generating a fixed dead time that is suitable for only one load condition.
Exemplary embodiments include methods and apparatus to vary the length of dead time to avoid device failure, power conversion inefficiencies, device overheating, elevated system operating temperatures, and driver failures caused by severe undershoot voltage. Exemplary embodiments also mitigate or eliminate shoot-through currents that occur in inverter circuits, including class D inverter circuits.
The exemplary embodiments are useful for operation of inverter circuits and for improving DC to AC conversion efficiency, which is useful in a variety of different electronic devices and applications.
For example, the efficiency of a power device with a high body diode forward bias (e.g., an enhancement mode GaN HEMT) can be severely affected by the length of the dead time. The device temperature is proportional to the power loss of these power devices. The optimum dead time value of the inverter achieves a minimum power loss based on the detected minimum device temperature. Exemplary embodiments provide methods and apparatus to automatically adjust dead time and maintain an inverter circuit at an optimal dead time value.
Exemplary embodiments of the present invention prevent input sources from being overloaded, and thus the present invention is suitable for low voltage and high drive current applications that simplify circuit design.
In an electrical network, parasitic elements are undesirable in circuits for their intended purpose, and are considered circuit portions of electronic devices. The wires have parasitic inductance because any wire through which current flows will generate a magnetic field around it. The parasitic inductance is determined by the length of the trace and the operating frequency. The longer the trace length, the higher the parasitic inductance. For inverter circuits with dead time control, parasitic inductance can have a significant impact on the effectiveness of the control. If such a circuit experiences high parasitic inductance, in the event of a signal error, the voltage is allowed to overshoot significantly, not protecting the components at all. The exemplary embodiments reduce the parasitic inductance of the circuit wiring.
Different loads require different dead time control in order to achieve optimal efficiency in the inverter circuit. Exemplary embodiments may achieve self-optimal dead time control settings as a function of device temperature.
As a further benefit, the exemplary embodiments reduce the material cost of purchasing higher-level components and the operating cost of large heat sinks and spaces. For example, the exemplary embodiments reduce the importance of implementing a heat sink in the inverter circuit and eliminate the need for expensive cooling components in the inverter circuit.
Referring to fig. 1, an exemplary embodiment includes a method of preventing an input source from being overloaded and reducing parasitic inductance in an inverter circuit having dead time control.
As an example, dead-time control includes generating dead-time based on a first dead-time interval and a second dead-time interval. For example, the first dead time interval corresponds to the dead time before the high-side device is turned on, and the second dead time interval corresponds to the dead time before the low-side device is turned on.
Block 110 shows: the temperature of the high side device in the inverter circuit is sensed using the first sensing capacitor.
As an example, the first sensing capacitor is thermally connected to the high-side device by a metal wire or any thermally conductive material.
As an example, the high-side device is surrounded by or thermally connected to a heat sink, as is the first sensing capacitor.
Block 120 shows: the temperature of the low-side device in the inverter circuit is sensed using a second sensing capacitor.
As an example, the second sensing capacitor is thermally connected to the low-side device by a metal wire or a thermally conductive material.
As an example, the low-side device is surrounded by or thermally connected to a heat sink, the second sensing capacitor also being surrounded by or thermally connected to the heat sink.
As an example, the high-side device and the low-side device may be selected from one or more types of transistors, including but not limited to enhancement mode GaN, GaN power transistors, and MOSFETs. High power density devices can result in significant temperature variations.
As an example, the source voltage is connected to the drain of the high-side device. The source of the high-side device is connected to the drain of the low-side device. The source of the low side device is grounded.
Block 130 shows: the first dead time interval is varied by the first delay generator and in accordance with the temperature received from the first sensing capacitor.
For example, the capacitance of the first sensing capacitor is changed in accordance with the detected or sensed temperature of the high-side device. The first delay time generated by the first delay generator is automatically changed according to the capacitance change of the first sensing capacitor. These changes occur continuously or in real time as the sensed temperature of the high-side device changes. The first dead time interval is changed according to a change of the first delay time generated by the RC delay. R is a resistance of the first constant resistor within the dead time generating unit, wherein the dead time generating unit includes a first delay generator and a second delay generator. C is the capacitance of the first sensing capacitor.
Block 140 shows: the second dead time interval is varied by a second delay generator and in accordance with the temperature received from the second sensing capacitor.
For example, the capacitance of the second sensing capacitor is varied in dependence on the detected or sensed temperature of the low side device. The second delay time generated by the second delay generator is automatically changed according to a change in capacitance of the second sensing capacitor. These changes occur continuously or continuously in real time as the sensed temperature of the low-side device changes. The second dead time interval is changed according to a change of the second delay time generated by the R 'C' delay. R' is the resistance of the second fixed resistor within the dead time generating unit. C' is the capacitance of the second sensing capacitor.
Block 150 shows: by connecting the first sensing capacitor between the first delay generator output and ground and the second sensing capacitor between the second delay generator output and ground, input source overload is prevented and parasitic inductance is reduced.
As an example, a first fixed value resistor is connected between the input and the output of the first delay generator.
As an example, a second fixed resistor is connected between the input and the output of the second delay generator.
As an example, the first delay generator is connected to the first sensing capacitor only by a wire or strip conductor.
As an example, the second delay generator is connected to the second sensing capacitor only by a wire or strip conductor.
As an example, the first sensing capacitor includes a first negative temperature coefficient capacitor and a first positive temperature coefficient capacitor connected in series, and the second sensing capacitor includes a second negative temperature coefficient capacitor and a second positive temperature coefficient capacitor connected in series.
As an example, the first negative temperature coefficient capacitor has a dielectric constant
Figure GDA0001982798860000081
The first positive temperature coefficient capacitor has a dielectric constant
Figure GDA0001982798860000082
Where T is the temperature of the high side device, TCIs the Curie temperature, alpha1Is a constant value, A, B and C are Steinhart-Hart coefficients,. epsilon0Is the dielectric constant in vacuum.
As an example, the second negative temperature coefficient of chargeThe container has a dielectric constant
Figure GDA0001982798860000091
The second positive temperature coefficient capacitor has a dielectric constant
Figure GDA0001982798860000092
Where T is the temperature of the low side device, TCIs the Curie temperature, alpha1Is a constant value, A, B and C are Steinhart-Hart coefficients,. epsilon0Is the dielectric constant in vacuum.
Fig. 2 shows a block diagram of a class D inverter circuit in a half-bridge configuration of an exemplary embodiment. Those of ordinary skill in the art will appreciate that the exemplary embodiments are also applicable to other inverter configurations, such as a full-bridge configuration.
The circuit 200 includes a Pulse Width Modulator (PWM) input node 201, a dead time generating unit (DT Gen.)206, a driver 202, high side and low side devices 203, 204, a first sensing capacitor 210 and a second sensing capacitor 220. An input of the dead time generation unit 206 is connected to the PWM input node 201. First and second outputs HI and L1 of dead time generation unit 206 are connected to high side device 203 and low side device 204, respectively, through driver 202. The driver 202 boosts the first output HI and the second output L1. For example, the high-side device 203 and the low-side device 204 are N-channel transistors. Thus, a first output HI of the dead time generation unit 206 is connected to the gate of the high side device 203 via the driver 202, and a second output LI of the dead time generation unit 206 is connected to the gate of the low side device 204 via the driver 202. A source Voltage (VAMP) is connected to the drain of the high side device 203 and the source of the high side device is connected to the drain of the low side device 204. The source of the low side device 204 is grounded. The node between the source of the high-side device 203 and the drain of the low-side device 204 is connected to the filter network 205 and any impedance load (Zload), such as resistors, capacitors, inductors, etc.
As an example, the high-side device 203 is surrounded by a heat sink or cover 208 and the low-side device 204 is surrounded by a heat sink or cover 209. A first sensing capacitor 210 is embedded in the heat sink or cover 208 and thermally connected to the high-side device 203 to sense the temperature of the high-side device 203. A second sensing capacitor 220 is embedded in the heat sink or cover 209 and thermally connected to the low-side device 204 to sense the temperature of the low-side device 204. The dead time generation unit 206 is electrically connected to the first sensing capacitor 210 only through a strip conductor, and the dead time generation unit 206 is also electrically connected to the second sensing capacitor 220 only through a strip conductor.
As an example, the first sensing capacitor 210 includes a first Negative Temperature Coefficient (NTC) capacitor and a first Positive Temperature Coefficient (PTC) capacitor connected in series. The second sensing capacitor 220 includes a second Negative Temperature Coefficient (NTC) capacitor and a second Positive Temperature Coefficient (PTC) capacitor connected in series. The dead time generation unit 206 changes a dead time including a first dead time interval of the high-side device 203 and a second dead time interval of the low-side device 204 according to the temperatures received from the first sensing capacitor 210 and the second sensing capacitor 220. The first dead time interval corresponds to the dead time before the high-side device 203 is turned on and the second dead time interval corresponds to the dead time before the low-side device 204 is turned on.
As an example, the dielectric constants of the capacitors are:
Figure GDA0001982798860000101
Figure GDA0001982798860000102
where A, B and C are Steinhart-Hart (S-H) coefficients, T is the temperature of the sensing capacitor, and T isCIs to sense the Curie temperature, alpha, of the capacitor1Is a constant value.
Fig. 3 shows a block diagram of a delay generator 300 of an exemplary embodiment. A sensing capacitor 310, which includes two types of capacitors, is connected between the output of the delay generator 300 and ground. Since the sense signal return path can be directly connected to ground, this approach greatly reduces the parasitic inductance of the circuit conductors and prevents gate voltage overshoot and undershoot. The capacitor is selected from a Negative Temperature Coefficient (NTC) capacitor and a Positive Temperature Coefficient (PTC) capacitor. For example, the at least one NTC capacitor and the at least one PTC capacitor are connected in series. A fixed resistor 303 is connected between the input and output of the delay generator 300 to create an RC delay circuit. For example, since resistor 302 limits the output voltage of the load, fixed value resistor 302 may be selected to have a low resistance, e.g., 1 to 5 ohms. The sensing capacitor 310 is located outside the delay generator 300 to be thermally connected with the transistors of the inverter circuit to sense their temperatures. The PTC capacitor performs overheat protection, which is caused by breakdown or severe switching loss. And the NTC capacitor is used to fine-tune the delay time generated from the delay generator 300.
Fig. 4 shows a block diagram of a delay generator 400 of an example embodiment to provide a flexible circuit design. A sensing capacitor 410, comprising two types of capacitors, is connected between the output of the delay generator 400 and ground. The capacitor is selected from the group consisting of an NTC capacitor and a PTC capacitor. For example, the at least one NTC capacitor and the at least one PTC capacitor are connected in series. A sense resistor 403 comprising two types of resistors is connected between the input and output of the delay generator 400 to create an RC delay circuit. The resistor is selected from an NTC sensor and a PTC sensor. The sensing capacitor 410 and the sensing resistor 403 are located outside the delay generator 400 to be thermally connected with the transistor for sensing the temperature. For example, the at least one NTC sensor and the at least one PTC sensor are connected in series. The PTC capacitor and/or the PTC sensor perform overheat protection, which is caused by breakdown or severe switching loss. The NTC capacitor and/or the NTC sensor are used to fine-tune the delay time generated from the delay generator 400.
FIG. 5 shows a graph 500 of the rate of change of capacitance (percent (%) versus temperature (C.)) for some particular dielectric materials of a sensing capacitor, in accordance with an example embodiment. These materials have specific temperature characteristics, selected based on dead time requirements, alone or in combination, to construct a positive or negative temperature coefficient capacitor for the sensing capacitor based on a predetermined temperature coefficient curve.
Fig. 6 shows a graph 600 of signal voltage (V) versus time (μ s) for a prior art inverter and an inverter of an exemplary embodiment of the present invention. The Printed Circuit Board (PCB) trace length of the existing inverter is twice the trace length of the inverter of the present invention. As shown in fig. 6, the present invention greatly eliminates ringing of the voltage signal. For example, the present invention eliminates negative overshoot and undershoot voltages of 2V and eliminates positive overshoot and undershoot voltages of 0.5V.
Accordingly, exemplary embodiments of the present invention have been fully described. Although the description refers to particular embodiments, it will be apparent to those skilled in the art that the present invention may be practiced with modification of these specific details. Accordingly, the present invention should not be construed as limited to the embodiments set forth herein.

Claims (20)

1. A method of preventing input source overload and reducing parasitic inductance in an inverter circuit having dead time control, the method comprising:
sensing a temperature of a high-side device in the inverter circuit by using a first sensing capacitor;
sensing a temperature of a low-side device in the inverter circuit with a second sensing capacitor;
varying, by a first delay generator and in dependence on the temperature received from the first sensing capacitor, a first dead time interval corresponding to a dead time before the high side device is switched on;
varying, by a second delay generator and in accordance with the temperature received from the second sensing capacitor, a second dead time interval corresponding to a dead time before the low side device turns on; and
preventing the input source from being overloaded and reducing parasitic inductance by connecting the first sensing capacitor between the output of the first delay generator and ground and connecting the second sensing capacitor between the output of the second delay generator and ground;
wherein the dead-time control comprises generating dead-time based on the first dead-time interval and the second dead-time interval.
2. The method of claim 1, further comprising:
varying a capacitance of the first sensing capacitor in accordance with the sensed temperature of the high-side device;
varying a capacitance of the second sensing capacitor in accordance with the sensed temperature of the low side device.
3. The method of claim 1, further comprising:
changing a first delay time generated from the first delay generator according to a change in capacitance of the first sensing capacitor; and
changing a second delay time generated from the second delay generator according to a change in capacitance of the second sensing capacitor.
4. The method of claim 1, wherein a first fixed resistor is connected between the input and the output of the first delay generator and a second fixed resistor is connected between the input and the output of the second delay generator.
5. The method of claim 1, wherein the first sensing capacitor comprises a first negative temperature coefficient capacitor and a first positive temperature coefficient capacitor connected in series, and the second sensing capacitor comprises a second negative temperature coefficient capacitor and a second positive temperature coefficient capacitor connected in series.
6. The method of claim 5, wherein the first negative temperature coefficient capacitor has a dielectric constant
Figure FDA0002796520180000021
The first positive temperature coefficient capacitor has a dielectric constant
Figure FDA0002796520180000022
Wherein T is the high side deviceTemperature of TCIs the Curie temperature, alpha1Is a constant value, A, B and C are Steinhart-Hart coefficients,. epsilon0Is the dielectric constant in vacuum.
7. The method of claim 1, further comprising: the first delay generator is connected to the first sensing capacitor only by a strip conductor, and the second delay generator is connected to the second sensing capacitor only by a strip conductor.
8. An inverter circuit which prevents an input source from being overloaded and reduces parasitic inductance in the inverter circuit, comprising:
a first sensing capacitor thermally connected to a high-side device in the inverter circuit;
a second sensing capacitor thermally connected to a low-side device in the inverter circuit;
a dead time generation unit that prevents a breakdown current and reduces a body diode conduction time by generating dead times for the high-side device and the low-side device, respectively, wherein the dead times include a first dead time interval and a second dead time interval, the dead time generation unit comprising:
a first delay generator that varies the first dead time interval, wherein the first sensing capacitor is connected between an output of the first delay generator and ground;
a second delay generator that varies the second dead time interval, wherein the second sensing capacitor is connected between an output of the second delay generator and ground;
wherein the first dead time interval corresponds to a dead time before the high side device is turned on and the second dead time interval corresponds to a dead time before the low side device is turned on.
9. The inverter circuit according to claim 8, wherein a first fixed resistor is connected between an input and an output of the first delay generator; a second fixed resistor is connected between the input and the output of the second delay generator.
10. The inverter circuit of claim 8, wherein the first delay generator is electrically connected to the first sensing capacitor only by a strip conductor, and the second delay generator is electrically connected to the second sensing capacitor only by a strip conductor.
11. The inverter circuit of claim 8, wherein the first sensing capacitor comprises a first negative temperature coefficient capacitor and a first positive temperature coefficient capacitor connected in series, and the second sensing capacitor comprises a second negative temperature coefficient capacitor and a second positive temperature coefficient capacitor connected in series.
12. The inverter circuit of claim 11, wherein the second negative temperature coefficient capacitor has a dielectric constant
Figure FDA0002796520180000031
The second positive temperature coefficient capacitor has a dielectric constant
Figure FDA0002796520180000032
Where T is the temperature of the second sensing capacitor, TCIs the Curie temperature, alpha1Is a constant value, A, B and C are Steinhart-Hart coefficients,. epsilon0Is the dielectric constant in vacuum.
13. The inverter circuit of claim 8, wherein the inverter circuit is a class D half bridge circuit.
14. The inverter circuit of claim 8, wherein the inverter circuit is a class D full bridge circuit.
15. The inverter circuit of claim 8, wherein the high-side device and the low-side device are selected from the group consisting of: enhancement mode GaN, GaN power transistors, and silicon MOSFETs.
16. A method of preventing input source overload and reducing parasitic inductance in an inverter circuit having dead time control, the method comprising:
sensing a temperature of at least one high-side device in the inverter circuit with a first sensing capacitor and a temperature of at least one low-side device in the inverter circuit with a second sensing capacitor;
changing, using at least one dead time generating unit and in dependence on the received temperature of the at least one high side device and the temperature of the at least one low side device, a first dead time interval corresponding to a dead time before the at least one high side device is switched on and a second dead time interval corresponding to a dead time before the at least one low side device is switched on;
preventing a breakdown current and reducing a body diode conduction time by operating the inverter circuit with a dead time that is within a maximum dead time that depends on capacitances of the first and second sensing capacitors at a rated temperature and a minimum dead time that depends on capacitances of the first and second sensing capacitors at a curie temperature.
17. The method of claim 16, further comprising:
varying a capacitance of the first sensing capacitor in accordance with the sensed temperature of the at least one high-side device;
varying a capacitance of the second sensing capacitor in accordance with the sensed temperature of the at least one low side device;
a first delay generator generating a first delay time according to a capacitance change of the first sensing capacitor;
a second delay generator generating a second delay time according to a change in capacitance of the second sensing capacitor;
wherein the first sensing capacitor is connected between the output of the first delay generator and ground; the second sensing capacitor is connected between the output of the second delay generator and ground.
18. The method of claim 17, further comprising:
a first fixed resistor is connected between the input and the output of the first delay generator and a second fixed resistor is connected between the input and the output of the second delay generator.
19. The method of claim 16, wherein the first and second sensing capacitors each comprise a negative temperature coefficient capacitor and a positive temperature coefficient capacitor connected in series, wherein the negative temperature coefficient capacitor is of dielectric constant
Figure FDA0002796520180000041
The positive temperature coefficient capacitor has a dielectric constant
Figure FDA0002796520180000042
Wherein T is the temperature of the first and second sensing capacitors, TCIs the Curie temperature, alpha1Is a constant value, A, B and C are Steinhart-Hart coefficients,. epsilon0Is the dielectric constant in vacuum.
20. The method of claim 16, further comprising:
connecting the at least one dead time generating unit to the first sensing capacitor only through a strip conductor; the at least one dead time generating unit is connected to the second sensing capacitor only by a strip conductor.
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